Technical Brief April 2006 TB457.0 Authors: Eric Josefson Sean Ba
|
|
|
Top Searches for this datasheet
Understanding Intersil Plug Devices
Technical Brief April 2006 TB457.0
Authors: Eric Josefson Sean Barr
Overview
Plug controllers have primary responsibilities, control inrush currents during turn-on control load currents safe pre-determined level event high current fault/short during static operation.
Devices Under Observation
ISL6116 (+5V) ISL6116 (-12V) ISL6116 (-48V) ISL6115 (+12V) HIP1012A (+5V +3.3V) ISL6173 (+3.3V +2.5V) ISL6111(+12V, -12V, +3.3V, +5V) ISL6118 (+5V Setting Overcurrent Trip Point
CTIM DISCHARGED
RISET USED DEVICE'S OVERCURRENT THRESHOLD POINT* VSENSE VSET?
CURRENT THROUGH RISENSE GENERATES VOLTAGE COMPARED THRESHOLD POINT DEFINED RISET CTIM CHARGED
TIMEOUT OCCURRED?**
FAULT CONDITION
*See respective controller datasheet equations select RISET **Timeout proportional CTIM varies controller (see datasheets) OVERCURRENT TRIP POINT OPERATION
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. Rights Reserved other trademarks mentioned property their respective owners.
Technical Brief ISL6116 (+5V)
Figures show ISL6116 ISL6115 high side switch application eval board. Jumper removed from original configuration Power Source applied +12V needed bias applied overcurrent point 1.5A. Figure notice soft-start ramp GATE after PWRON initiated, thus allowing gradual ramp ILOAD. Figure starting into short shown. Upon PWRON being asserted, CTIM immediately begins charging. nominal time-out period CTIM overcurrent (OC) event occurs when current through sense resistor exceeds user programmed threshold (see data sheet). controller enters current regulation (CR) capacitor CTIM begins charging. nominal time-out period CTIM 93k. (see Figure 5A). transient event from 500mA occurs. PGOOD pulled temporary undervoltage condition occurring +5VOUT, CTIM stays true event never occurs (See Figure 5B).
ISL6116 (+5V) Figures
LOAD
+12V VBIAS ISL6116 3.3V PGOOD PWRON
FIGURE EVAL BOARD SCHEMATIC
FIGURE EVAL BOARD PICTURE
1.5A PGOOD
1.5A CTIM
PWRON
ILOAD
GATE GATE ILOAD PGOOD
FIGURE TURN PWRON INTO NOMINAL LOAD
FIGURE TURN PWRON INTO SHORT
TB457.0 April 2006
Technical Brief ISL6116 (+5V) Figures (Continued)
1.5A Ch3PGOOD PGOOD
+5VOUT IOUT GATE ILOAD
CTIM Ch2CTIM
FIGURE RESPONSE DURING OPERATION FIGURE
FIGURE RESPONSE FALSE FAULT EVENT
ISL6116 (-12V)
Figures show ISL6116 reconfigured -12V side switch application. following components were removed: RG1, R11. added (0.047µf 0805 size). Figure notice that GATE fully enhance because -12V operation. Also note that PGOOD disabled side configuration. Upon power current regulation mode entered CTIM immediately
begins charging. nominal time-out period CTIM 93k, again PGOOD disabled (see Figure event occurs when current through sense resistor exceeds user programmed threshold (see data sheet). controller enters mode capacitor CTIM begins charging. nominal time-out period CTIM (see Figure 10).
ISL6116 (-12V) Figures
+VBUS LOAD -12V APPL. -VBUS
-12V*
REMOVE: RG1,
ISL6116 3.3V 0-5V
LOGIN
FIGURE ISL6116EVAL1 NEGATIVE VOLTAGE SIDE CONTROLLER
FIGURE ISL6116 EVAL BOARD PICTURE
TB457.0 April 2006
Technical Brief ISL6116 (-12V) Figures (Continued)
2.4A ILOAD
2.4A
GATE GATE
ILOAD CTIM
PGOOD CTIM/Ch3 PGOOD
FIGURE TURN INTO NOMINAL LOAD
FIGURE TURN INTO OVERCURRENT
2.4A ILOAD
GATE
CTIM
FIGURE RESPONSE DURING OPERATION
TB457.0 April 2006
Technical Brief ISL6116 (-48V)
Figure show ISL6116 -48V Side Switch Application. eval board uses HIP5600 bias ISL6116 higher than -48V. Note intentionally left empty. Tests were done -36V keep power dissipated load low. Results would essentially same -48V. Figure notice soft-start ramp GATE upon LOGIN being driven low. Keep mind that PGOOD disabled side applications. Upon turn GATE begins soft-start, then attempts regulate, then shut down (see Figure 14). Note CTIM's behavior eval board setup DNP). Figure load switched from open controller immediately pulls GATE down, CTIM load isolated. When LOGIN forced high, controller shuts down (see Figure 16).
ISL6116 (-48V) Figures
+VBUS LOAD -VBUS -48V EMPTY
ISL6116
3.3V
LOGIN
0-5V
FIGURE ISL6116 EVAL BOARD SCHEMATIC
FIGURE ISL6116 EVAL BOARD PICTURE
2.4A
2.4A
GATE LOGIN
LOGIN GATE CTIM ILOAD
ILOAD CTIM
FIGURE TURN LOGIN
FIGURE TURN INTO
TB457.0 April 2006
Technical Brief ISL6116 (-48V) Figures (Continued)
2.4A LOGIN
2.4A
GATE CTIM ILOAD
GATE ILOAD CTIM
FIGURE RESPONSE DURING OPERATION
FIGURE TURN LOGIN
ISL6115 (+12V)
Figures show ISL6115 +12V high side switch application. Refer Figures After PWRON asserted, notice soft-start ramp GATE assure inrush current limited. Observe PGOOD delay well.
Both Figures show event; Figure shows turning into short, Figure shows short occurring during normal operation. event occurs when current through sense resistor exceeds user programmed threshold (see data sheet). controller enters mode capacitor CTIM begins charging. nominal time-out period CTIM 93k.
ISL6115 (+12V) Figures
LOAD
+12V VBIAS ISL6115 3.3V PWRON
FIGURE ISL6115 EVAL BOARD SCHEMATIC
FIGURE ISL6115 EVAL BOARD PICTURE
TB457.0 April 2006
Technical Brief ISL6115 (+12V) Figures (Continued)
1.5A PGOOD
1.5A
GATE PWRON
ILOAD
FIGURE TURN PWRON INTO NOMINAL LOAD
FIGURE TURN PWRON
1.5A CTIM
1.5A PGOOD
GATE
ILOAD GATE PGOOD CTIM ILOAD
FIGURE TURN INTO
FIGURE RESPONSE DURING OPERATION
TB457.0 April 2006
Technical Brief HIP1012A (+5V +3.3V)
Figures show HIP1012A dual Swap controller. configure +3.3V +5V, remove JP1, apply function generator pin2 (PWRON2)'. Figures show HIP1012A dual Swap controller load card.
TABLE SWAP CONTROLLER LOAD CARD 3.3V LOAD (3.3A) (1.8A) (4.7A) LOAD 10.1 (0.5A) (0.7A) (1.2A)
Figures both show same event. Figure shows Figure shows I3.3V. Controller shutdown forcing PWRON2 high. Figures show turning into condition. Figure shows 3/12VG PWRON2, while Figure shows PGOOD. event occurs when current through sense resistor exceeds user programmed threshold (see data sheet). controller enters mode capacitor CTIM begins charging. nominal time-out period CTIM 200k. Both Figures show event. Figure shows 700mA 1.2A load step into range during normal operation, while Figure shows short occurring during normal operation. Notice that "short condition", Figure pulled instantly GND, then slowly ramped event occurs line. Notice that 3.3V line continues operating normally until CTIM times device latches (see Figure 35).
Both Figures show same event. Figure shows Figure shows I3.3V. After PWRON2 asserted (forced low), notice soft-start ramp 3/12VG assure inrush current limited. Observe PGOOD delay well.
HIP1012A (+5V +3.3V) Figures
CEC1 /12VIN 0.1µF 5VIN 0.1µF 3/12VS 3/12VG HIP1012A 3/12ISEN RILIM CPUMP CTIM PGOOD 5VISEN 5VOUT 0.047µF 0.01µF CEC2 12VOUT
MODE/ PWRON1 PWRON2
R101 0.01µF 100m LED1
Note: Test point number equals HIP1012A number. FIGURE HIP1012A EVAL BOARD SCHEMATIC
TB457.0 April 2006
Technical Brief HIP1012A (+5V +3.3V) Figures (Continued)
FIGURE HIP1012A EVAL BOARD PICTURE
1,2,3 R102 LED2 4,5,6, 7,8,10 SW11 9,11, R103 LED3 SW12 SW13 SW14
FIGURE LOAD CIRCUIT SCHEMATIC
FIGURE LOAD CIRCUIT EVAL BOARD PICTURE
5VICR 3.3VICR
3/12VG PGOOD
5VICR 3.3VICR
PGOOD I3.3V
(PWRON2)'
(PWRON2)'
FIGURE TURN SHOWING BOTH CHANNELS
FIGURE TURN SHOWING +3.3V DETAILS
TB457.0 April 2006
Technical Brief HIP1012A (+5V +3.3V) Figures (Continued)
5VICR 3.3VICR (PWRON2)' 5VICR 3.3VICR (PWRON2)'
PGOOD
PGOOD
3/12VG
I3.3V 3/12VG
FIGURE TURN SHOWING BOTH CHANNELS
FIGURE TURN SHOWING +3.3V DETAILS
5VICR 3.3VICR
3/12VG
5VICR 3.3VICR
(PWRON2)'
CTIM
CTIM PGOOD
FIGURE TURN INTO SHOWING BOTH CHANNELS
FIGURE TURN INTO SHOWING DETAILS
5VICR 3.3VICR
5VICR 3.3VICR
CTIM PGOOD
CTIM PGOOD
FIGURE RESPONSE SHORT DURING OPERATION
FIGURE RESPONSE DURING OPERATION1
TB457.0 April 2006
Technical Brief HIP1012A (+5V +3.3V) Figures (Continued)
3V/12VG 5VICR 3.3VICR
PGOOD
CTIM
FIGURE RESPONSE SHOWING BOTH CHANNELS
HIP1012A (+5V 12V)
HIP1012A eval board also configured +12V Swap control. this, jumpers must removed.
HIP1012A (+5V 12V) Figures
CEC1 /12VIN 0.1µF 5VIN 0.1µF 3/12VS 3/12VG HIP1012A 3/12ISEN RILIM CPUMP CTIM PGOOD 5VISEN 5VOUT 0.047µF 0.01µF CEC2 12VOUT
MODE/ PWRON1 PWRON2
R101 0.01µF 100m LED1
Note: Test point number equals HIP1012A number. FIGURE SCHEMATIC +12V OPERATION
TB457.0 April 2006
Technical Brief HIP1012A (+5V 12V) Figures (Continued)
FIGURE +12V EVAL BOARD PICTURE
ISL6173 (+3.3V +2.5V)
Figure shows ISL6173 dual voltage Swap controller. This targets applications between +2.1V +3.6V +Vin1, with second channel controlling applications from +0.7V +Vin1. ISL6173 biased +Vin1. following measurements, channel will control +3.3V, channel +2.5V. Both Figures show device turning enable lines being asserted (forced low). Figure shows each output soft-start ramp after being enabled, while Figure shows more detail regarding only channel (+3.3V this case) during soft-start. Figures show condition occurring during operation channel (+3.3V). device enters mode until times out, which point switch channel latches off. Figure note that (PG1)' triggered upon dipping, while (FLT1)' stays high until times out. nominal time-out this device (CTIM*1.178)/10µA.
Both Figures show condition occurring during operation channel (+3.3V). Figure shows gate signal output voltage channel staying high while channel shuts down. Figure shows Power Good Fault signals each channel, again note that (PG1)' (FLT1)' tripped, while (PG2)' (FLT2)' remain unaffected. Figures show condition occurring during operation channel (+3.3V). device enters mode load recovers before chance time out. Notice that (PG1)' triggered with VO1, then recovers, while (FLT1)' stays high never timing out. nominal time-out this device (CTIM*1.178)/10µA. Figure ISL6173 reset mode, which means device will attempt bring channel again after discharging times. This process will repeat infinitely. case high di/dt shorts, condition exists (see Figure 65). controller will immediately pull before attempting enter mode. Note that load released before timeout occurs here. Both channels disabled bringing their respective enable lines high (see Figure 66).
TB457.0 April 2006
ISL6173 (+3.3V +2.5V) Figures
IRF7821 Vi_1 Vi_1 3.3V 220µF 0.01
1.1K 1000pF 0.01µF STUFF 3.57K 10µF
47µF
CON2 0.1µF
MBR130P
TP11
OPEN Disable CLOSE Enable
2.2µF
CPQ-
ISL6173
0.033µF OCREF GND1 14.7K
0.022µF
CPQ+
FLT1
GND_IN
OPEN Latch CLOSE Retry 0.47µF
CPVDD
TP17 TP18
1.1K
SNS2
TP14
PGND
FLT2 0.033µF
0.15µF TP10
0.15µF
FLT2 LED55B/TO TP15
LED55B/TO
1000pF TP16 STUFF
2.55K
CON2
Vi_2 Vi_2
220µF
CON2 0.01
47µF
2.5V
FIGURE EVAL BOARD SCHEMATIC
FLT1 LED55B/TO
0.1µF
TP12
0.01µF
RTR/LTCH BIAS
SNS1
LED55B/TO
GND_OUT TP13
Technical Brief
IRF7821
MBR130P
TB457.0 April 2006
TP27 TP28
TP31 IRF7821 49.9
TP30
TP29
IRF7821
TP33
TP34
TP35
TP36
TP26
TP25
OUTA IN2_ OUTB EL7202/SO
Technical Brief
TP19
TP24
TP32 IRF7821 49.9
TP20
TP23 IRF7821
TP22
TP21 OUTA IN2_ OUTB
EL7202/SO
TB457.0 April 2006
FIGURE EVAL BOARD SCHEMATIC (CONTINUED)
Technical Brief ISL6173 (+3.3V +2.5V) Figures
FIGURE ISL6173 EVAL BOARD PICTURE
BOTH CHANNELS 2.2A BOTH CHANNELS IWOC 6.6A
BOTH CHANNELS 2.2A BOTH CHANNELS IWOC 6.6A
(EN1)' (EN2)' (PG1)'
FIGURE TURN (EN)' SHOWING BOTH CHANNELS
FIGURE TURN SHOWING CHANNEL DETAILS
TB457.0 April 2006
Technical Brief ISL6173 (+3.3V +2.5V) Figures (Continued)
BOTH CHANNELS 2.2A BOTH CHANNELS IWOC 6.6A (FLT1)' BOTH CHANNELS 2.2A BOTH CHANNELS IWOC 6.6A
(PG1)'
ILOAD3.3V
ILOAD3.3V
FIGURE RESPONSE LATCH MODE (CT)
FIGURE RESPONSE LATCH MODE ((PG)')
BOTH CHANNELS 2.2A BOTH CHANNELS IWOC 6.6A
BOTH CHANNELS 2.2A BOTH CHANNELS IWOC 6.6A
(PG2)' (PG1)' (PG2)' (FTL1)'
FIGURE CHANNEL COMPARISON
FIGURE CHANNEL COMPARISON ((FLT)' (PG)')
BOTH CHANNELS 2.2A BOTH CHANNELS IWOC 6.6A
BOTH CHANNELS 2.2A BOTH CHANNELS IWOC 6.6A (FTL1)'
(PG1)' ILOAD3.3V ILOAD3.3V
FIGURE WITH RECOVERY BEFORE TIMEOUT (CT)
FIGURE WITH RECOVERY BEFORE TIMEOUT ((PG)')
TB457.0 April 2006
Technical Brief ISL6173 (+3.3V +2.5V) Figures (Continued)
BOTH CHANNELS 2.2A BOTH CHANNELS IWOC 6.6A BOTH CHANNELS 2.2A BOTH CHANNELS IWOC 6.6A
ILOAD3.3V ILOAD3.3V
FIGURE RESET MODE
FIGURE RESPONSE
BOTH CHANNELS 2.2A BOTH CHANNELS IWOC 6.6A
(EN2)' (EN1)'
FIGURE TURN (EN)'
ISL6111 (+12V, -12V, +3.3V, +5V)
Figures show ISL6111 Plug power switch controller. This provides power control four legacy supplies (+12V, -12V, 3.3V, PCI-X slot. +12V -12V switches integrated, while higher power 3.3V lines require external N-channel FETs. Refer Figures Though different time scales, both figures show same event; Figure shows four output voltages ramping Figure gives detailed information pertaining single rail (+3.3V) startup. There resistive load +3.3V output.
Refer Figures Though different time scales, both figures show same event; Figure shows four output approaching GND, Figure gives detailed information pertaining single rail (+3.3V) shutdown There resistive load +3.3V output. Both Figures show same event, each with different details. Note that PGOOD goes soon 3.3VS drops, FLTLN waits until mode expired. nominal time-out period this device CTIM 150k. Turning into direct short, +3.3V section controller goes immediately into mode until CRTIM times out. nominal time-out period this device CTIM 150k (see Figure 46).
TB457.0 April 2006
Technical Brief ISL6111 (+12V, -12V, +3.3V, +5V) Figures
FIGURE EVAL BOARD SCHEMATIC
FIGURE EVAL BOARD PICTURE
TB457.0 April 2006
Technical Brief ISL6111 (+12V, -12V, +3.3V, +5V) Figures (Continued)
+5VICR +12VOUT +3.3VICR +12VICR 650mA -12VICR 140mA +5VOUT +3.3VOUT ILOAD3.3V +5VICR +3.3VICR +12VICR 650mA -12VICR 140mA -12VOUT +3.3VOUT
FIGURE TURN SHOWING OUTPUTS
FIGURE TURN SHOWING +3.3V DETAILS
+5VICR +12VOUT +3.3VICR +12VICR 650mA -12VICR 140mA +5VOUT +3.3VOUT ILOAD3.3V -12VOUT +3.3VOUT
+5VICR +3.3VICR +12VICR 650mA -12VICR 140mA
FIGURE TURN SHOWING OUTPUTS
FIGURE TURN SHOWING +3.3V DETAILS
+5VICR +3.3VICR +12VICR 650mA -12VICR 140mA ILOAD3.3V FTLN +3.3VOUT
+5VICR +3.3VICR +12VICR 650mA -12VICR 140mA ILOAD3.3V
PGOOD
CRTIM
FIGURE RESPONSE +3.3V CHANNEL
FIGURE RESPONSE +3.3V CHANNEL
TB457.0 April 2006
Technical Brief ISL6111 (+12V, -12V, +3.3V, +5V) Figures (Continued)
ILOAD3.3V
+5VICR +3.3VICR +12VICR 650mA -12VICR 140mA CRTIM
+3.3VOUT
FIGURE TURN INTO SHORT +3.3V
ISL6118 (+5V
Figures show ISL6118 dual power supply controller. This provides fully independent fault protection +2.5V +5.5V environment, with integrated MOSFETs. ease testing, were tied together this board. Refer Figures After asserted, notice soft-start ramp both outputs VIN, this case +5V. Also
notice that FAULT2 only indicator timeout, thus indicator under voltage conditions. Figure shows condition occurring through channel Note that channel stays regardless condition channel Figure shows turning into condition channel Again, channel unaffected.
ISL6118 (+5V Figures
(VIN) FAULT_OUT1 OUT1 FAULT_OUT2 TP10
ISL6118
OUT2
FIGURE EVAL BOARD SCHEMATIC
FIGURE EVAL BOARD PICTURE
TB457.0 April 2006
Technical Brief ISL6118 (+5V Figures (Continued)
BOTH CHANNELS 600mA
BOTH CHANNELS 600mA
EN_1&2
OUT_1/CH2 OUT_2
FAULT2 EN_1&2 OUT_1/CH2 OUT_2
FAULT2
FIGURE TURN
FIGURE TURN
BOTH CHANNELS 600mA
BOTH CHANNELS 600mA
OUT_1/CH3 EN_1&2 FAULT2 OUT_2
EN_1&2
OUT_1 FAULT2 OUT_2
FIGURE RESPONSE CONDITION
FIGURE TURN INTO SHORT
TB457.0 April 2006
Technical Brief Setting Overcurrent Trip Point
Setting Plug Over Current Trip Points
general, Intersil plug devices sense load current through sense resistor, then compare voltage generated across this sense resistor voltage programmed "set" resistor Steps Trip Point: (Steps vary slightly part) Select desired trip point level Determine RISET selecting sense threshold voltage design Calculate RISENSE based level selected step
SUPPLY ICR) +3.3 +5.0 NOMINAL CURRENT REGULATION LEVEL (10%) EACH SUPPLY ((100µA RCRSET)/8.54)/RRSENSE ((100µA RCRSET)/12)/RRSENSE (100µA RCRSET)/0.7 (100µA RCRSET)/3.3
ISL6173 (+3.3V +2.5V)
ISL6173 level, equation:
HIP1012A, ISL6115, ISL6116 Devices
HIP1012A, ISL6115, ISL6116 levels, equation:
ISENSE
Where:
OCREF OCREF typically 80µA
ISL6118
ISL6118 current sense limiting circuitry sets current limit nominal 600mA.
HIP1012A ISET 10µA
-40°C IOUT (mA)
With:
RISET RESISTOR 4.99k 2.5k
NOMINAL (mV)
25°C
ISL6115, ISL6116 ISET 20µA RILIM RESISTOR 4.99 NOMINAL (mV)
85°C 1.25 1.50 1.75 2.00 2.25 VOUT 2.50 2.75 3.00
FIGURE CURRENT REGULATION VOUT (VIN 3.3V)
-40°C
Applications:
IOUT (mA)
25°C
RCRSET 4.22k, which provides nominal current trip level 110%-130% higher than maximum specified range Non-PCI Applications: RCRSET (thermal considerations) select RCRSET 3.0k avoid noise faults
85°C
VOUT
FIGURE CURRENT REGULATION VOUT (VIN
TB457.0 April 2006
Technical Brief Summary Overcurrent Response
HIP1012A programmed setpoint exceeded, gate modulated regulate current current regulation level until programmed timeout occurs. timeout occurs, both gates latch off. load current exceeds 300% programmed setpoint, affected gate immediately pulled ground, then modulated regulate current current regulation level until timeout occurs. HIP1013 setpoint exceeded, both gates will latch ~2µs after event HIP1011, programmed setpoint exceeded, outputs latch off. ISL6115, ISL6116, ISL6117, ISL6120 programmed setpoint exceeded, gate modulated regulate current current regulation level until programmed timeout occurs. timeout occurs, gate latches off. overcurrent voltage threshold exceeded more than 150mV, affected gate immediately pulled ground, then modulated regulate current current regulation level until timeout occurs. ISL6118, ISL619, ISL6121 setpoint exceeded, current regulated then gate latches ~12ms after event. ISL6111 programmed setpoint exceeded, gate modulated regulate current current regulation level until programmed timeout occurs. timeout occurs, four gates latch off. HIP1020 This device does provide current monitoring. ISL6140, ISL6150 programmed setpoint exceeded more than 2µs, gate will latch off. ISL6173 levels overcurrent detection present, mode (Way Overcurrent) mode. load current reaches setpoint, gate modulated regulate current current regulation level until current drops below programmed timeout occurs. timeout occurs, output will either latch indefinitely retry depending condition RTR/LTCH pin. mode reached upon very high di/dt spike >300% Gate pulled immediately, then device enters mode. ISL6141/51 programmed setpoint exceeded, gate modulated regulate current current regulation level until 500µs timeout occurs. overcurrent voltage threshold exceeded more than 150mV, affected gate immediately pulled ground, then modulated regulate current current regulation level until 500µs timeout occurs. timeout occurs, gate latches off. ISL6142/52 programmed setpoint exceeded, gate modulated regulate current current regulation level until programmed timeout occurs. overcurrent voltage threshold exceeded more than 150mV, affected gate immediately pulled ground, then modulated regulate current current regulation level until programmed timeout occurs. timeout occurs, gate latches off. ISL6161 programmed setpoint exceeded, gate modulated regulate current current regulation level until programmed timeout occurs. timeout occurs, both gates latch off. load current exceeds 300% programmed setpoint, affected gate immediately pulled ground, then modulated regulate current current regulation level until timeout occurs.
TB457.0 April 2006
Technical Brief Plug/Hot Swap Target Applications
SWAP/HOT PLUG INTERSIL PART NUMBER HIP1011 HIP1011A HIP1011B HIP1011D HIP1011E HIP1012A HIP1013 HIP1020 ISL6111 ISL6115 ISL6116 ISL6117 ISL6118 ISL6119 ISL6120 ISL6121 ISL6140/50 ISL6141/51 ISL6142/52 ISL6160 ISL6161 ISL6173 BIAS VOLTAGE +2.5 +5.5 +2.5 +5.5 +2.5 +5.5 +2.1 +3.6 CONTROLLED VOLTAGE(S) +12, -12, +3.3 +12, -12, +3.3 +12, -12, +3.3 +12, -12, +3.3, +12, -12, +3.3, +12/+5 +5/+3.3 +12/+5 +5/+3.3 +12/+5/+3.3 +5/+3.3 +12, -12, +3.3 +3.3 +2.5 +12/+5 +12/+3.3 +2.17 +3.6, +0.7 VBIAS COMPACT TARGET APPLICATIONS STORAGE SYSTEMS -48V TELECOM GENERAL PURPOSE
INFINIBAND
TB457.0 April 2006
Technical Brief List Figures
Page ISL6116 (+5V) Figures EVAL BOARD SCHEMATIC EVAL BOARD PICTURE TURN PWRON INTO NOMINAL LOAD. TURN PWRON INTO SHORT RESPONSE DURING OPERATION RESPONSE FALSE FAULT EVENT ISL6116 (-12V) Figures ISL6116EVAL1 NEGATIVE VOLTAGE SIDE CONTROLLER ISL6116 EVAL BOARD PICTURE. TURN INTO NOMINAL LOAD TURN INTO OVERCURRENT RESPONSE DURING OPERATION ISL6116 (-48V) Figures ISL6116 EVAL BOARD SCHEMATIC ISL6116 EVAL BOARD PICTURE. TURN LOGIN TURN INTO RESPONSE DURING OPERATION TURN LOGIN ISL6115 (+12V) Figures ISL6115 EVAL BOARD SCHEMATIC ISL6115 EVAL BOARD PICTURE. TURN PWRON INTO NOMINAL LOAD. TURN PWRON. TURN INTO RESPONSE DURING OPERATION HIP1012A (+5V +3.3V) Figures HIP1012A EVAL BOARD SCHEMATIC HIP1012A EVAL BOARD PICTURE LOAD CIRCUIT SCHEMATIC LOAD CIRCUIT EVAL BOARD PICTURE. TURN SHOWING BOTH CHANNELS TURN SHOWING +3.3V DETAILS TURN SHOWING BOTH CHANNELS TURN SHOWING +3.3V DETAILS. TURN INTO SHOWING BOTH CHANNELS TURN INTO SHOWING DETAILS RESPONSE SHORT DURING OPERATION RESPONSE DURING OPERATION1 RESPONSE SHOWING BOTH CHANNELS HIP1012A (+5V 12V) Figures SCHEMATIC +12V OPERATION +12V EVAL BOARD PICTURE
TB457.0 April 2006
Technical Brief
ISL6173 (+3.3V +2.5V) Figures EVAL BOARD SCHEMATIC EVAL BOARD SCHEMATIC (CONTINUED) ISL6173 EVAL BOARD PICTURE. TURN (EN)' SHOWING BOTH CHANNELS TURN SHOWING CHANNEL DETAILS. RESPONSE LATCH MODE (CT) RESPONSE LATCH MODE ((PG)') CHANNEL COMPARISON GT). CHANNEL COMPARISON ((FLT)' (PG)') WITH RECOVERY BEFORE TIMEOUT (CT). WITH RECOVERY BEFORE TIMEOUT ((PG)') RESET MODE RESPONSE WOC. TURN (EN)' ISL6111 (+12V, -12V, +3.3V, +5V) Figures EVAL BOARD SCHEMATIC EVAL BOARD PICTURE TURN SHOWING OUTPUTS TURN SHOWING +3.3V DETAILS TURN SHOWING OUTPUTS TURN SHOWING +3.3V DETAILS RESPONSE +3.3V CHANNEL RESPONSE +3.3V CHANNEL TURN INTO SHORT +3.3V ISL6118 (+5V Figures EVAL BOARD SCHEMATIC EVAL BOARD PICTURE TURN TURN RESPONSE CONDITION TURN INTO SHORT ISL6118 CURRENT REGULATION VOUT (VIN 3.3V). CURRENT REGULATION VOUT (VIN
Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that Application Note Technical Brief current before proceeding.
information regarding Intersil Corporation products, www.intersil.com
TB457.0 April 2006
Other recent searches
PK008 - PK008 PK008 Datasheet
PQ100 - PQ100 PQ100 Datasheet
HQ100 - HQ100 HQ100 Datasheet
HWS451 - HWS451 HWS451 Datasheet
CSD-10H-1 - CSD-10H-1 CSD-10H-1 Datasheet
AN1156 - AN1156 AN1156 Datasheet
1N4148W - 1N4148W 1N4148W Datasheet
1N3595UR-1 - 1N3595UR-1 1N3595UR-1 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
