ISL6443 August 2006 FN9044.2 300kHz Dual, 180° Out-of-Phase,

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ISL6443 August 2006 FN9044.2 300kHz Dual, 180° Out-of-Phase,

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L6443A Data Sheet
ISL6443
August 2006 FN9044.2
300kHz Dual, 180° Out-of-Phase, StepDown Single Linear Controller
ISL6443 high-performance, triple-output controller optimized converting wall adapter, battery network intermediate input supplies into system supply voltages required wide variety applications. Each output adjustable down 0.8V. PWMs synchronized 180° phase reducing input current ripple voltage. ISL6443 incorporates several protection features. adjustable overcurrent protection circuit monitors output current sensing voltage drop across lower MOSFET. Hiccup mode overcurrent operation protects DC/DC components from damage during output overload/short circuit conditions. Each independent logic-level shutdown input (SD1 SD2). single PGOOD signal issued when soft-start complete both controllers their outputs within point linear regulator output greater than setpoint. Thermal shutdown circuitry turns device junction temperature exceeds +150°C.
Features
Wide Input Supply Voltage Range Variable 5.6V Fixed 4.5V 5.6V Three Independently Programmable Output Voltages Switching Frequency 300kHz Phase Controller Operation Reduces Required Input Capacitance Power Supply Induced Loads External Current Sense Resistor Uses Lower MOSFET's rDS(ON) Bidirectional Frequency Synchronization Synchronizing Multiple ISL6443s Programmable Soft-Start Extensive circuit protection functions PGOOD UVLO Overcurrent Over-temperature Independent Shutdown Both PWMs Excellent Dynamic Response Voltage Feed-Forward with Current Mode Control Packages: Compliant JEDEC PUB95 MO-220 Quad Flat Leads Package Outline Near Chip Scale Package footprint, which improves efficiency thinner profile Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER ISL6443IR PART TEMP. MARKING RANGE (°C) ISL6443IR PACKAGE PKG. DWG.
L28.5x5 L28.5x5 (Pb-free)
ISL6443IRZ ISL6443IRZ (See Note)
"-T" "-TK" suffix tape reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
Applications
Power Supplies with Multiple Outputs xDSL Modems/Routers DSP, ASIC, FPGA Power Supplies Set-Top Boxes Dual Output Supplies DSP, Memory, Logic, Core Telecom Systems
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. Rights Reserved other trademarks mentioned property their respective owners.
ISL6443 Pinouts
ISL6443 (QFN) VIEW
PHASE1 ISEN1 PGND SGND OCSET1 SGND SYNC GATE3 SGND UGATE2 UGATE1 LGATE2 LGATE1 BOOT2 BOOT1
PHASE2 ISEN2 PGOOD VCC_5V OCSET2
FN9044.2 August 2006
Block Diagram
BOOT1 UGATE1 PHASE1 VCC_5V LGATE1 PGND ADAPTIVE DEAD-TIME DIODE EMULATION SAMPLE TIMING ADAPTIVE DEAD-TIME DIODE EMULATION SAMPLE TIMING PGOOD SGND BOOT2 UGATE2 PHASE2 LGATE2
PGND ENABLE 0.8V REFERENCE BIAS SUPPLIES REFERENCE FAULT LATCH SOFT-START PGOOD PGOOD
GATE3
gm*VE
ISL6443
1400k 180k
18.5pF
18.5pF
1400k
PWM2
180k
VSEN2
0.8V ERROR
PWM1
ERROR
SOFT2
DUTY CYCLE RAMP GENERATOR CHANNEL PHASE CONTROL
0.8V ISEN2
ISEN1
CURRENT SAMPLE
CURRENT SAMPLE CURRENT SAMPLE
CURRENT SAMPLE
OCSET1
OCSET2
0.8V REFERENCE
0.8V REFERENCE
SAME STATE CLOCK CYCLES REQUIRED LATCH OVERCURRENT FAULT
SYNC
SAME STATE CLOCK CYCLES REQUIRED LATCH OVERCURRENT FAULT
FN9044.2 August 2006
ISL6443 Typical Application Schematic
+12V 4.7µF 0.1µF 0.1µF BOOT1 VCC_5V 0.1µF BOOT2 0.1µF BAT54HT1 56µF
BAT54HT1
UGATE1 PHASE1
ISL6443 (See Note)
UGATE2 PHASE2 ISEN2 1.4K
VOUT1 +1.2V, 330µF
6.4µH
1.4K
ISEN1
6.4µH 330µF 31.6K
VOUT2 +3.3V,
LGATE1
FDS6990
LGATE2 SGND SGND FDS6990
4.99k
PGND
OCSET1
0.1µF IRF7404 VOUT3 +2.5V, 500mA 21.5K 10µF
GATE3 OCSET2 120K PGOOD VCC_5V VOUT2 +3.3V
120K PGOOD SGND SYNC
FN9044.2 August 2006
ISL6443
Absolute Maximum Ratings
Supply Voltage (VCC_5V Pin) -0.3V Input Voltage (VIN Pin). .+27V BOOT1, UGATE1, +35V PHASE1, ISEN1, +27V BOOT1, with Respect PHASE1, +6.5V UGATE1, (PHASE1, 0.3V) (BOOT1, +0.3V)
Thermal Information
Thermal Resistance (Typical) (°C/W) (°C/W) Lead (Note Maximum Junction Temperature (Plastic Package) -55°C 150°C Maximum Storage Temperature Range -65°C 150°C Temperature Range -40°C 85°C
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured free with component mounted high effective thermal conductivity test board with "direct attach" features. "case temp" location center exposed metal underside package. Tech Brief TB379.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer Block Diagram Typical Application Schematic. 5.6V 24V, VCC_5V ±10%, -40°C 85°C (Note Typical values 25°C TEST CONDITIONS UNIT
PARAMETER SUPPLY Input Voltage Range VCC_5V SUPPLY (Note Input Voltage Output Voltage Maximum Output Current SUPPLY CURRENT Shutdown Current (Note Operating Current (Note REFERENCE SECTION Nominal Reference Voltage Reference Voltage Tolerance POWER-ON RESET Rising VCC_5V Threshold Falling VCC_5V Threshold OSCILLATOR Total Frequency Variation Peak-to-Peak Sawtooth Amplitude (Note
5.6V, 20mA
-1.0
4.25 3.95
4.45
4.16 0.6V
0.667
10.0 5.44
Ramp Offset (Note SYNC Input Rise/Fall Time (Note SYNC Frequency Range SYNC Input HIGH Level SYNC Input Level SYNC Input Minimum Pulse Width (Note SYNC Output HIGH Level SHUTDOWN1/SHUTDOWN2 HIGH Level (Converter Enabled) Level (Converter Disabled) Internal Pull-up (3A)
FN9044.2 August 2006
ISL6443
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer Block Diagram Typical Application Schematic. 5.6V 24V, VCC_5V ±10%, -40°C 85°C (Note Typical values 25°C (Continued) TEST CONDITIONS UNIT
PARAMETER CONVERTERS Output Voltage Bias Current Maximum Duty Cycle Minimum Duty Cycle CONTROLLER ERROR AMPLIFIERS Gain (Note Gain-Bandwidth Product (Note Slew Rate (Note Maximum Output Voltage (Note Minimum Output Voltage (Note CONTROLLER GATE DRIVERS (Note Sink/Source Current Upper Drive Pull-Up Resistance Upper Drive Pull-Down Resistance Lower Drive Pull-Up Resistance Lower Drive Pull-Down Resistance Rise Time Fall Time LINEAR CONTROLLER Drive Sink Current Feedback Threshold Undervoltage Threshold Input Leakage Current (Note Amplifier Transconductance POWER GOOD CONTROL FUNCTIONS PGOOD Level Voltage PGOOD Leakage Current PGOOD Upper Threshold, PGOOD Lower Threshold, PGOOD Linear Controller ISEN CURRENT LIMIT Full Scale Input Current (Note Overcurrent Threshold (Note OCSET (Current Limit) Voltage SOFT-START Soft-Start Current
COUT 1000pF, 25°C
VCC_5V 4.5V VCC_5V 4.5V VCC_5V 4.5V VCC_5V 4.5V COUT 1000pF COUT 1000pF
21mA 0.8V, 21mA
Pull-up 100k
±1.0
Fraction point Fraction point
ROCSET 110k
1.75
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ISL6443
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer Block Diagram Typical Application Schematic. 5.6V 24V, VCC_5V ±10%, -40°C 85°C (Note Typical values 25°C (Continued) TEST CONDITIONS UNIT
PARAMETER PROTECTION Thermal Shutdown Rising
Hysteresis NOTES: Specifications -40°C 85°C guaranteed design, production tested.
normal operation, where device supplied with voltage pin, VCC_5V provides output capable 60mA (min). When VCC_5V used supply input, internal regulator disabled input must connected VCC_5V pin. (Refer Descriptions section more details.) This total shutdown current with VCC_5V PVCC Operating current supply current consumed when device active switching. does include gate drive current. peak-to-peak sawtooth amplitude production tested only; this parameter guaranteed design. Guaranteed design; production tested. production tested; guaranteed characterization only. Guaranteed design. full scale current 32µA recommended optimum current sample hold operation. Feedback Loop Compensation Section below.
FN9044.2 August 2006
ISL6443 Typical Performance Curves
(Oscilloscope Plots Taken Using ISL6443EVAL Evaluation Board, Unless Otherwise Noted.)
PWM1 OUTPUT VOLTAGE PWM2 OUTPUT VOLTAGE 3.39 3.38 3.37 3.36 3.35 3.34 3.33 3.32 3.31 LOAD CURRENT 3.39 3.38 3.37 3.36 3.35 3.34 3.33 3.32 3.31 LOAD CURRENT
FIGURE PWM1 LOAD REGULATION
FIGURE PWM2 LOAD REGULATION
PGOOD 5V/DIV 0.85 0.84 REFERENCE VOLTAGE 0.83 0.82 0.81 0.79 0.78 0.77 0.76 0.75 TEMPERATURE (°C) VOUT1 2V/DIV VOUT2 2V/DIV VOUT3 2V/DIV
FIGURE REFERENCE VOLTAGE VARIATION OVER TEMPERATURE
FIGURE SOFT-START WAVEFORMS WITH PGOOD
VOUT1 20mV/DIV, COUPLED
VOUT2 20mV/DIV, COUPLED
0.5A/DIV, COUPLED
0.5A/DIV, COUPLED
PHASE1 10V/DIV
PHASE2 10V/DIV
FIGURE PWM1 WAVEFORM
FIGURE PWM2 WAVEFORM
FN9044.2 August 2006
ISL6443 Typical Performance Curves
(Continued)
(Oscilloscope Plots Taken Using ISL6443EVAL Evaluation Board, Unless Otherwise Noted.)
VOUT1 200mV/DIV COUPLED
VOUT2 200mV/DIV COUPLED
IOUT1 1A/DIV
IOUT2 1A/DIV
FIGURE LOAD TRANSIENT RESPONSE VOUT1 (3.3V)
FIGURE LOAD TRANSIENT RESPONSE VOUT2 (3.3V)
VCC_5V 1V/DIV
VOUT1 2V/DIV
2A/DIV
2V/DIV VOUT1 1V/DIV
FIGURE SOFT-START WAVEFORM
FIGURE OVERCURRENT HICCUP MODE OPERATION
PWM1 EFFICIENCY
PWM2 EFFICIENCY
LOAD CURRENT
LOAD CURRENT
FIGURE PWM1 EFFICIENCY LOAD (3.3V),
FIGURE PWM2 EFFICIENCY LOAD (3.3V),
FN9044.2 August 2006
ISL6443 Descriptions
BOOT2, BOOT1 These pins power upper MOSFET drivers each converter. Connect this junction bootstrap capacitor cathode bootstrap diode. anode bootstrap diode connected VCC_5V pin. UGATE2, UGATE1 These pins provide gate drive upper MOSFETs. PHASE2, PHASE1 These pins connected junction upper MOSFETs source, output filter inductor lower MOSFETs drain. LGATE2, LGATE1 These pins provide gate drive lower MOSFETs. PGND This provides power ground connection lower gate drivers both PWM1 PWM2. This should connected sources lower MOSFETs terminals external input capacitors. FB3, FB2, These pins connected feedback resistor divider provide voltage feedback signals respective controller. They output voltage converter. addition, PGOOD circuit uses these inputs monitor output voltage status. ISEN2, ISEN1 These pins used monitor voltage drop across lower MOSFET current loop feedback overcurrent protection. PGOOD This open drain logic output used indicate status output voltages. This pulled when either outputs within respective nominal voltage, linear controller output less than it's nominal value. Table shows detailed status PGOOD which classified into cases under different combinations inputs. first case when both HIGH. PGOOD will HIGH pins from REQUIRED outputs within regulation soft-starts (SS1 SS2) complete. other cases when either which means system wants shut down outputs still wants keep another output working. PGOOD will HIGH pins from
TABLE LDO>75%? 90%<FB1<110%? 90%<FB2<110%? COMPLETED? COMPLETED? PGOOD
REQUIRED outputs within regulation soft-start (SS1/SS2) complete. last case when both LOW. PGOOD will low. SGND (Pin TSSOP; QFN) This small-signal ground, common controllers, must routed separately from high current ground (PGND). voltage levels measured with respect this pin. Connect additional SGND pins this pin. using supply, connect this VCC_5V. small ceramic capacitor should connected right next this noise decoupling. this power device with external supply voltage with range 5.6V 24V. ±10% operation, connect this VCC_5V. VCC_5V This output internal linear regulator. This output supplies bias side gate drivers, external boot circuitry high side gate drivers. powered directly from single (±10%) supply this pin. When used supply input, this must externally connected VIN. VCC_5V must always decoupled power ground with minimum 4.7F ceramic capacitor, placed very close pin. SYNC This used synchronize more ISL6443 controllers. This requires resistor ground used; connect directly VCC_5V used. SS1, These pins provide soft-start function their respective controllers. When chip enabled, regulated pull-up current source charges capacitor connected from this ground. error amplifier reference voltage ramps from 0.8V while voltage soft-start ramps from 0.8V. SD1, These pins provide enable/disable function their respective output. output enabled when this floating pulled HIGH, disabled when pulled LOW. GATE3 This open drain output linear regulator controller. OCSET2, OCSET1 resistor from this ground sets overcurrent threshold respective PWM.
means "don't care".
FN9044.2 August 2006
ISL6443 Functional Description
General Description
ISL6443 integrates control circuits synchronous buck converters linear controller. synchronous bucks operate phase substantially reduce input ripple thus reduce input filter requirements. chip four control lines (SS1, SD1, SS2, SD2), which provide independent control each synchronous buck outputs. buck controllers employ free-running frequency 300kHz. current mode control scheme with input voltage feed-forward ramp input modulator provides excellent rejection input voltage variations provides simplified loop compensations. linear controller drive either PFET provide ultra low-dropout regulation with programmable voltages. main outputs start-up. soft-start time obtained from following equation:
SOFT 0.8V
VCC_5V 1V/DIV
VOUT1 1V/DIV
1V/DIV
Internal Linear Regulator (VCC_5V)
ISL6443 functions internally powered from onchip, dropout regulator. maximum regulator input voltage 24V. Bypass regulator's output (VCC_5V) with 4.7µF capacitor ground. dropout voltage this typically 600mV, when VCC_5V greater than 5.6V, VCC_5V typically ISL6443 also employs undervoltage lockout circuit that disables both regulators when VCC_5V falls below 4.4V. internal source over 60mA supply power side gate drivers, charge external boot capacitor supply small external loads. When driving large FETs especially 300kHz frequency, little regulator current available external loads. example, single large with 15nC total gate charge requires 15nC 300kHz 4.5mA. Also, higher input voltages with larger FETs, power dissipation across internal will increase. Excessive dissipation across this regulator must avoided prevent junction temperature rise. Larger FETs used with ±10% input applications. thermal overload protection circuit will triggered, VCC_5V output short circuited. Connect VCC_5V ±10% input applications.
FIGURE SOFT-START OPERATION
soft-start capacitors chosen provide startup tracking outputs. This achieved choosing soft-start capacitors such that soft-start capacitor ration equals respective output voltage ratio. example, PWM1 1.2V PWM2 3.3V then soft-start capacitor ratio should CSS1/CSS1 1.2/3.3 0.364. Figure shows that soft-start waveform with CSS1 0.01µF CSS2 0.027µF.
VOUT1 1V/DIV
VOUT2 1V/DIV
Soft-Start Operation
When soft-start initiated, voltage enabled channels starts ramp gradually, current sourced into external capacitor. output voltage follows soft-start voltage. When voltage reaches 0.8V, output voltage enabled channel reaches regulation point, soft-start voltage continues rise. this point PGOOD fault circuitry enabled. This completes soft-start sequence. further rise voltage does affect output voltage. varying values soft-start capacitors, possible provide sequencing
FIGURE PWM1 PWM2 OUTPUT TRACKING DURING STARTUP
Output Voltage Programming
resistive divider from output ground sets output voltage either channel. center point divider shall connected pin. output voltage value determined following equation.
OUTx 0.8V
where resistor feedback divider network resistor connected from ground.
FN9044.2 August 2006
ISL6443
Out-of-Phase Operation
controllers ISL6443 operate out-ofphase reduce input ripple current. This reduces input capacitor ripple current requirements, reduces power supplyinduced noise, improves EMI. This effectively helps lower component cost, save board space reduce EMI. Dual PWMs typically operate in-phase turn both upper FETs same time. input capacitor must then support instantaneous current requirements both controllers simultaneously, resulting increased ripple voltage current. higher ripple current lowers efficiency power loss associated with input capacitor. This typically requires more low-ESR capacitors parallel minimize input voltage ripple ESR-related losses, meet required ripple current rating. With dual synchronized out-of-phase operation, high-side MOSFETs ISL6443 turn 180o out-of-phase. instantaneous input current peaks both regulators longer overlap, resulting reduced ripple current input voltage ripple. This reduces required input capacitor ripple current rating, allowing fewer less expensive capacitors, reducing shielding requirements EMI. typical operating curves show synchronized 180° out-of-phase operation. 180o Shoot-through control logic provides 20ns deadtime ensure that both upper lower MOSFETs will turn simultaneously cause shoot-through condition.
Gate Drivers
low-side gate driver supplied from VCC_5V provides peak sink/source current 400mA. high-side gate driver also capable 400mA current. Gate-drive voltages upper N-Channel MOSFET generated flying capacitor boot circuit. boot capacitor connected from BOOT PHASE node provides power high side MOSFET driver. limit peak current external resistor placed between UGATE gate external MOSFET. This small series resistor also damps oscillations caused resonant tank parasitic inductances traces board FET's input capacitance.
VCC_5V
BOOT UGATE PHASE
Input Voltage Range
ISL6443 designed operate from input supplies ranging from 4.5V 24V. However, input voltage range effectively limited available maximum duty cycle (DMAX 93%).
0.93
ISL6443
FIGURE
where, parasitic voltage drops inductor discharge path, including lower FET, inductor board. voltage drops charging path, including upper FET, inductor board resistances. maximum input voltage minimum output voltage limited minimum on-time (tON(min)).
300kHz
start-up low-side MOSFET turns forces PHASE ground order charge BOOT capacitor After low-side MOSFET turns off, high-side MOSFET turned closing internal switch between BOOT UGATE. This provides necessary gate-tosource voltage turn upper MOSFET, action that boosts gate drive signal above VIN. current required drive upper MOSFET drawn from internal regulator.
Protection Circuits
converter output monitored protected against overload, short circuit undervoltage conditions. sustained overload output sets PGOOD initiates hiccup mode.
where, tON(min) 30ns
Gate Control Logic
gate control logic translates generated signals into gate drive signals providing amplification, level shifting shoot-through protection. gate drivers have some circuitry that helps optimize performance over wide range operational conditions. MOSFET switching times vary dramatically from type type with input voltage, gate control logic provides adaptive dead time monitoring real gate waveforms both upper lower MOSFETs.
Overcurrent Protection
Both controllers lower MOSFET's onresistance, rDS(ON) monitor current converter. sensed voltage drop compared with threshold resistor connected from OCSETx ground.
OCSET
FN9044.2 August 2006
ISL6443
where, desired overcurrent protection threshold, value current sense resistor connected ISENx pin. overcurrent detected consecutive clock cycles then enters hiccup mode turning gate drivers entering into soft-start. will cycle times through soft-start before trying restart. will continue cycle through soft-start until overcurrent condition removed. Hiccup mode active during soft-start care must taken ensure that peak inductor current does exceed overcurrent threshold during soft-start. Because nature this current sensing technique, accommodate wide range rDS(ON) variations, value overcurrent threshold should represent overload current about 150% 180% maximum operating current. more accurate current protection desired place current sense resistor series with lower MOSFET source.
Feedback Loop Compensation
reduce number external components simplify process determining compensation components, both controllers have internally compensated error amplifiers. make internal compensation possible several design measures were taken. First, ramp signal applied comparator proportional input voltage provided pin. This keeps modulator gain constant with variation input voltage. Second, load current proportional signal derived from voltage drop across lower MOSFET during time interval subtracted from amplified error signal comparator input. This creates internal current control loop. resistor connected ISEN sets gain current feedback loop. following expression estimates required value current sense resistor depending maximum operating load current value MOSFET's rDS(ON).
-32A
Over-Temperature Protection
incorporates over-temperature protection circuit that shuts down when temperature 150°C reached. Normal operation resumes when temperatures drops below 130°C through initiation full soft-start cycle.
Choosing provide 32µA current current sample hold circuitry recommended values down 100µA used. current loop feedback, modulator single pole response with -20dB slope frequency determined load.
Implementing Synchronization
SYNC used synchronize more controllers. When SYNC pins controllers connected together, controller becomes master other controller synchronizes master. pull-down resistor required must sized provide enough time constant pass SYNC pulse. Connect this VCC_5V used. Figure shows SYNC waveform operating times switching frequency.
where load resistance load capacitance. this type modulator, Type compensation circuit usually sufficient. Figure shows Type amplifier response along with responses current mode modulator converter. Type amplifier, addition pole origin, zero-pole pair that causes flat gain region frequencies between zero pole.
6kHz 600kHz
FIGURE SYNC WAVEFORM
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ISL6443
feedback resistor drains excess charge. However, charge build output capacitor making VLDO rise above point. Care must taken insure that feedback resistor's current exceeds pass transistors leakage current over entire temperature range. linear regulator output supplied output PWMs. When using PFET, output linear will track supply after output rises voltage greater than threshold PFET pass device. voltage differential between linear output will load current times rDS(ON). Figure shows linear regulator (2.5V) startup waveform (3.3V) startup waveform.
CONVERTER TYPE 17.5dB
MODULATOR
18dB
FIGURE FEEDBACK LOOP COMPENSATION
zero frequency, amplifier high-frequency gain, modulator gain chosen satisfy most typical applications. crossover frequency will appear point where modulator attenuation equals amplifier high frequency gain. only task that system designer complete specify output filter capacitors position load main pole somewhere within decade lower than amplifier zero frequency. With this type compensation plenty phase margin easily achieved zero-pole pair phase `boost'. Conditional stability occur only when main load pole positioned much left side frequency axis excessive output filter capacitance. this case, zero placed within 1.2kHz 30kHz range gives some additional phase `boost'. Some phase boost also achieved connecting capacitor parallel with upper resistor divider that sets output voltage value. Please refer output inductor capacitor selection sections further details.
VOUT2 1V/DIV
VOUT3 1V/DIV
FIGURE LINEAR REGULATOR STARTUP WAVEFORM
0.79
Linear Regulator
linear regulator controller transconductance amplifier with nominal gain 2A/V. N-channel MOSFET output device sink minimum 50mA. reference voltage 0.8V. With zero volts differential it's input, controller sinks 21mA current. external transistor PFET pass element used. dominant pole loop placed base gate PFET), capacitor from emitter base (source gate PFET). Better load transient response achieved however, dominant pole placed output, with capacitor ground output regulator. Under no-load conditions, leakage currents from pass transistors supply output capacitors, even when transistor off. Generally this problem since
ERROR AMPLIFIER SINK CURRENT (mA)
0.82 0.83 0.81 FEEDBACK VOLTAGE
0.84
0.85
FIGURE LINEAR CONTROLLER GAIN
Base-Drive Noise Reduction
high-impedance base driver susceptible system noise, especially when linear regulator lightly loaded. Capacitively coupled switching noise inductively coupled
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ISL6443
onto base drive causes fluctuations base current, which appear noise linear regulator's output. Keep base drive traces away from step-down converter, short possible, minimize noise coupling. resistor series with gate drivers reduces switching noise generated PWM. Additionally, bypass capacitor placed across base-to-emitter resistor. This bypass capacitor, addition transistor's input capacitor, could bring second pole that will destabilize linear regulator. Therefore, stability requirements determine maximum base-to-emitter capacitance. Place controller close lower FET. LGATE connection should short wide. best placed over quiet ground area. Avoid switching ground loop current this area. Place VCC_5V bypass capacitor very close VCC_5V connect ground PGND plane. Place gate drive components BOOT diode BOOT capacitors together near controller output capacitors should placed close load possible. short wide copper regions connect output capacitors load avoid inductance resistances. copper filled polygons wide short trace connect junction upper FET. Lower output inductor. Also keep PHASE node connection short. unnecessary oversize copper islands PHASE node. Since phase nodes subjected very high dv/dt voltages, stray capacitor formed between these islands surrounding circuitry will tend couple switching noise. Route high speed switching nodes away from control circuitry. Create separate small analog ground plane near Connect SGND this plane. small signal grounding paths including feedback resistors, current limit setting resistors, SYNC/SDx pull down resistors should connected this SGND plane. Ensure feedback connection output capacitor short direct.
Layout Guidelines
Careful attention layout requirements necessary successful implementation ISL6443 based DC/DC converter. ISL6443 switches very high frequency therefore switching times very short. these switching frequencies, even shortest trace significant impedance. Also peak gate drive current rises significantly extremely short time. Transition speed current from device another causes voltage spikes across interconnecting impedances parasitic circuit elements. These voltage spikes degrade efficiency, generate EMI, increase device overvoltage stress ringing. Careful component selection proper board layout minimizes magnitude these voltage spikes. There sets critical components DC/DC converter using ISL6443. switching power components small signal components. switching power components most critical from layout point view because they switch large amount energy they tend generate large amount noise. critical small signal components those connected sensitive nodes those supplying critical bias currents. multi-layer printed circuit board recommended.
Component Selection Guidelines
MOSFET Considerations
logic level MOSFETs chosen optimum efficiency given potentially wide input voltage range output power requirements. N-Channel MOSFETs used each synchronous-rectified buck converters PWM1 PWM2 outputs. These MOSFETs should selected based upon rDS(ON), gate supply requirements, thermal management considerations. power dissipation includes loss components; conduction loss switching loss. These losses distributed between upper lower MOSFETs according duty cycle (see following equations). conduction losses main component power dissipation lower MOSFETs. Only upper MOSFET significant switching losses, since lower device turns into near zero voltage. equations assume linear voltage-current transitions model power loss reverse-recovery lower MOSFET's body diode.
UPPER
Layout Considerations
Input capacitors, Upper FET, Lower FET, Inductor Output capacitor should placed first. Isolate these power components topside board with their ground terminals adjacent another. Place input high frequency decoupling ceramic capacitor very close MOSFETs. separate ground planes power ground small signal ground. Connect SGND PGND together close connect them together anywhere else. loop formed Input capacitor, bottom must kept small possible. Insure current paths from input capacitor MOSFET; output inductor output capacitor short possible with maximum allowable trace widths.
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ISL6443
LOWER
large gate-charge increases switching time, tSW, which increases upper MOSFET switching losses. Ensure that both MOSFETs within their maximum junction temperature high ambient temperature calculating temperature rise according package thermal-resistance specifications.
High frequency decoupling capacitors should placed close power pins load physically possible. careful inductance circuit board wiring that could cancel usefulness these inductance components. Consult with manufacturer load circuitry specific decoupling requirements. only specialized low-ESR capacitors intended switching-regulator applications 300kHz bulk capacitors. most cases, multiple small-case electrolytic capacitors perform better than single large-case capacitor. stability requirement selection output capacitor that `ESR zero', between 1.2kHz 30kHz. This range internal, single compensation zero 6kHz. zero factor five either side internal zero still contribute increased phase margin control loop. Therefore,
Output Capacitor Selection
output capacitors each output have unique requirements. general, output capacitors should selected meet dynamic regulation requirements including ripple voltage load transients. Selection output capacitors also dependent output inductor, some inductor analysis required select output capacitors. parameters limiting converter's response load transient time required inductor current slew it's level. ISL6443 will provide either duty cycle response load transient. response time time interval required slew inductor current from initial current value load current level. During this interval difference between inductor current transient current level must supplied output capacitor(s). Minimizing response time minimize output capacitance required. Also, load transient rise time slower than inductor response time, hard drive drive, reduces requirement output capacitor. maximum capacitor value required provide full, rising step, transient load current during response time inductor
TRAN
conclusion, output capacitors must meet three criteria: They must have sufficient bulk capacitance sustain output voltage during load transient while output inductor current slewing value load transient, must sufficiently meet desired output voltage ripple output inductor current, zero should placed, rather large range, provide additional phase margin. recommended output capacitor value ISL6443 between 150F 680F, meet stability criteria with external compensation. aluminum electrolytic, POSCAP, tantalum type capacitors recommended. ceramic capacitors possible would take more rigorous loop analysis ensure stability.
Output Inductor Selection
converters require output inductors. output inductor selected meet output voltage ripple requirements. inductor value determines converter's ripple current ripple voltage function ripple current output capacitor(s) ESR. ripple voltage expression given capacitor selection section ripple current approximated following equation:
where, COUT output capacitor(s) required, output inductor, ITRAN transient load current step, input voltage, output voltage, DVOUT drop output voltage allowed during load transient. High frequency capacitors initially supply transient current slow load rate-of-change seen bulk capacitors. bulk filter capacitor values generally determined (Equivalent Series Resistance) voltage rating requirements well actual capacitance requirements. output voltage ripple inductor ripple current output capacitors defined
RIPPLE
ISL6443, Inductor values between 6.4H recommended when using Typical Application Schematic. Other values used thorough stability study should done.
where, calculated Inductor Selection section.
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ISL6443
Input Capacitor Selection
important parameters bulk input capacitor(s) voltage rating current rating. reliable operation, select bulk input capacitors with voltage current ratings above maximum input voltage largest current required circuit. capacitor voltage rating should least 1.25 times greater than maximum input voltage times conservative guideline. Input current varies with load. total current supplied input capacitance
RMS1 RMS2
INPUT CURRENT 3.3V LOAD CURRENT 3.3V PHASE PHASE
where,
RMSx
FIGURE INPUT CURRENT LOAD
duty cycle respective PWM. Depending specifics input power impedance, most all) this current supplied input capacitor(s). Figure shows advantage having converters operating phase. converters were operating phase, combined current would algebraic sum, which much larger value shown. combined out-of-phase current square root square individual reflected currents significantly less than combined in-phase current.
input bypass capacitors control voltage ripple across MOSFETs. ceramic capacitors high frequency decoupling bulk capacitors supply current. Small ceramic capacitors placed very close upper MOSFET suppress voltage induced parasitic circuit impedances. board designs that allow through-hole components, Sanyo OS-CON® series offer good temperature performance. surface mount designs, solid tantalum capacitors used, caution must exercised with regard capacitor surge current rating. These capacitors must capable handling surgecurrent power-up. series available from surge current tested.
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FN9044.2 August 2006
ISL6443 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
D1/2 INDEX AREA E1/2 0.15 0.15 VIEW 0.10 0.08 SIDE VIEW (DATUM (DATUM INDEX AREA (Nd-1)Xe REF. BOTTOM VIEW E2/2 (Ne-1)Xe REF. 0.10 0.15 0.15
L28.5x5
LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT JEDEC MO-220VHHD-1 ISSUE MILLIMETERS SYMBOL 0.20 0.50 2.95 2.95 0.18 0.80 NOMINAL 0.90 0.02 0.65 0.20 0.25 5.00 4.75 3.10 5.00 4.75 3.10 0.50 0.60 0.60 0.75 3.25 3.25 0.30 1.00 0.05 1.00 NOTES Rev. 11/04 NOTES: Dimensioning tolerancing conform ASME Y14.5-1994. number terminals. refer number terminals each dimensions millimeters. Angles degrees. Dimension applies metallized terminal measured between 0.15mm 0.30mm from terminal tip. configuration identifier optional, must located within zone indicated. identifier either mold mark feature. Dimensions exposed pads which provide improved electrical thermal performance. Nominal dimensions provided assist with Land Pattern Design efforts, Intersil Technical Brief TB389.
SEATING PLANE
CORNER OPTION
SECTION "C-C"
Features dimensions present when Anvil singulation method used present singulation.
TERMINAL TERMINAL/SIDE EVEN TERMINAL/SIDE
FN9044.2 August 2006

ISL6443 August 2006 FN9044.2 300kHz Dual, 180° Out-of-Phase,

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