Data Sheet August 2005 FN817.6 15MHz, BiMOS Operational Amplifier

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Data Sheet August 2005 FN817.6 15MHz, BiMOS Operational Amplifier

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CA3130, CA3130A
Data Sheet August 2005 FN817.6
15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output
CA3130A CA3130 amps that combine advantage both CMOS bipolar transistors. Gate-protected P-Channel MOSFET (PMOS) transistors used input circuit provide very-high-input impedance, very-low-input current, exceptional speed performance. PMOS transistors input stage results common-mode input-voltage capability down 0.5V below negative-supply terminal, important attribute single-supply applications. CMOS transistor-pair, capable swinging output voltage within 10mV either supply-voltage terminal very high values load impedance), employed output circuit. CA3130 Series circuits operate supply voltages ranging from 16V, (±2.5V ±8V). They phase compensated with single external capacitor, have terminals adjustment offset voltage applications requiring offset-null capability. Terminal provisions also made permit strobing output stage. CA3130A offers superior input characteristics over those CA3130.
Features
MOSFET Input Stage Provides: Very High (1.5 1012) (Typ) Very (Typ) Operation (Typ) Operation Ideal Single-Supply Applications Common-Mode Input-Voltage Range Includes Negative Supply Rail; Input Terminals Swung 0.5V Below Negative Supply Rail CMOS Output Stage Permits Signal Swing Either both) Supply Rails Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Ground-Referenced Single Supply Amplifiers Fast Sample-Hold Amplifiers Long-Duration Timers/Monostables High-Input-Impedance Comparators (Ideal Interface with Digital CMOS) High-Input-Impedance Wideband Amplifiers Voltage Followers (e.g. Follower Single-Supply Converter) Voltage Regulators (Permits Control Output Voltage Down Peak Detectors Single-Supply Full-Wave Precision Rectifiers Photo-Diode Sensor Amplifiers
Ordering Information
PART (BRAND)
CA3130AE CA3130AM
TEMP. RANGE (oC) PACKAGE PDIP SOIC SOIC Tape Reel SOIC (Pb-free) SOIC Tape Reel (Pb-free) PDIP PDIP* (Pb-free) SOIC
PKG. DWG. E8.3 M8.15 M8.15 M8.15 M8.15 E8.3 E8.3 M8.15
(3130A)
CA3130AM96
(3130A)
CA3130AMZ
Pinout
CA3130, CA3130A (PDIP, SOIC) VIEW
(3130AZ) (Note)
CA3130AMZ96
(3130AZ) (Note)
CA3130E CA3130EZ (Note) CA3130M
(3130)
CA3130M96
(3130)
CA3130MZ
(3130MZ) (Note)
CA3130MZ96
(3130MZ)
SOIC M8.15 Tape Reel SOIC M8.15 (Pb-free) SOIC M8.15 Tape Reel (Pb-free)
OFFSET NULL INV. INPUT NON-INV. INPUT
STROBE OUTPUT OFFSET NULL
*Pb-free PDIPs used through hole wave solder processing only. They intended Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2005. Rights Reserved other trademarks mentioned property their respective owners.
CA3130, CA3130A
Absolute Maximum Ratings Supply Voltage (Between Terminals) .16V Differential Input Voltage Input Voltage +8V) -0.5V) Input-Terminal Current Output Short-Circuit Duration (Note Indefinite Operating Conditions Temperature Range -50oC 125oC
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) PDIP Package*. SOIC Package Maximum Junction Temperature (Plastic Package) .150oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) .300oC (SOIC Lead Tips Only) *Pb-free PDIPs used through hole wave solder processing only. They intended Reflow solder processing applications.
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: Short circuit applied ground either supply. measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Input Offset Voltage Input Offset Voltage Temperature Drift Input Offset Current Input Current Large-Signal Voltage Gain
25oC, 15V, Unless Otherwise Specified TEST CONDITIONS ±7.5V CA3130 ±7.5V ±7.5V 10VP-P ±7.5V 14.99 -0.5 13.3 0.002 0.01 0.01 14.99 CA3130A -0.5 13.3 0.002 0.01 0.01 UNITS µV/oC kV/V µV/V
SYMBOL |VIO| VIO/T |IIO|
Common-Mode Rejection Ratio Common-Mode Input Voltage Range Power-Supply Rejection Ratio Maximum Output Voltage
CMRR VICR VIO/VS VOM+ VOMVOM+ VOM-
Maximum Output Current
IOM+ (Source) IOM- (Sink)
Supply Current
7.5V,
CA3130, CA3130A
Electrical Specifications
Typical Values Intended Only Design Guidance, VSUPPLY ±7.5V, 25oC Unless Otherwise Specified SYMBOL TEST CONDITIONS Across Terminals 1MHz 0.2MHz, (Note 47pF CA3130, CA3130A UNITS
PARAMETER Input Offset Voltage Adjustment Range Input Resistance Input Capacitance Equivalent Input Noise Voltage Open Loop Unity Gain Crossover Frequency (For Unity Gain Stability 47pF Required.) Slew Rate: Open Loop Closed Loop Transient Response: Rise Time Overshoot Settling Time <0.1%, 4VP-P) NOTE:
56pF 56pF, 25pF, (Voltage Follower)
V/µs V/µs
0.09
Although source used this test, equivalent input noise remains constant values 10M.
Electrical Specifications
PARAMETER Input Offset Voltage Input Offset Current Input Current Common-Mode Rejection Ratio Large-Signal Voltage Gain
Typical Values Intended Only Design Guidance, 25oC Unless Otherwise Specified (Note SYMBOL CMRR 4VP-P, TEST CONDITIONS CA3130 CA3130A UNITS kV/V µV/V
Common-Mode Input Voltage Range Supply Current
VICR 2.5V,
Power Supply Rejection Ratio NOTE:
VIO/V+
Operation recommended temperatures below 25oC.
CA3130, CA3130A Schematic Diagram
BIAS CIRCUIT CURRENT SOURCE 8.3V INPUT STAGE NON-INV. INPUT INV.-INPUT (NOTE OUTPUT STAGE SECOND STAGE "CURRENT SOURCE LOAD"
OUTPUT
OFFSET NULL
COMPENSATION
STROBING
NOTE: Diodes through provide gate-oxide protection MOSFET input stage.
Application Information
Circuit Description
Figure block diagram CA3130 Series CMOS Operational Amplifiers. input terminals operated down 0.5V below negative supply rail, output swung very close either supply rail many applications. Consequently, CA3130 Series circuits ideal single-supply operation. Three Class amplifier stages, having individual gain capability current consumption shown Figure provide total gain CA3130. biasing circuit provides potentials common first second stages. Terminal used both phase compensation strobe output stage into quiescence. When Terminal tied negative supply rail (Terminal mechanical electrical means, output potential Terminal essentially rises positive supply-rail potential Terminal This condition essentially zero current drain output stage under strobed "OFF" condition only achieved when ohmic load resistance presented amplifier very high (e.g.,when amplifier output used drive CMOS digital circuits Comparator applications).
Input Stage
circuit CA3130 shown schematic diagram. consists differential-input stage using PMOS field-effect transistors (Q6, working into mirror-pair bipolar transistors (Q9, Q10) functioning load resistors together with resistors through mirror-pair transistors also function differential-tosingle-ended converter provide base drive secondstage bipolar transistor (Q11). Offset nulling, when desired, effected connecting 100,000 potentiometer across Terminals potentiometer slider Terminal
CA3130, CA3130A
CA3130 200µA 1.35mA 200µA (NOTE (NOTE BIAS CKT.
sources both first second amplifier stages, respectively. total supply voltages somewhat less than 8.3V, zener diode becomes nonconductive potential, developed across series-connected D1-D4, varies directly with variations supply voltage. Consequently, gate bias varies accordance with supply-voltage variations. This variation results deterioration power-supply-rejection ratio (PSRR) total supply voltages below 8.3V. Operation total supply voltages below about 4.5V results seriously degraded performance.
INPUT 6000X OUTPUT COMPENSATION (WHEN REQUIRED) STROBE
Output Stage
output stage consists drain-loaded inverting amplifier using CMOS transistors operating Class mode. When operating into very high resistance loads, output swung within millivolts either supply rail. Because output stage drain-loaded amplifier, gain dependent upon load impedance. transfer characteristics output stage load returned negative supply rail shown Figure Typical loads readily driven output stage. Because largesignal excursions non-linear, requiring feedback good waveform reproduction, transient delays encountered. voltage follower, amplifier achieve 0.01% accuracy levels, including negative supply rail.
NOTE: general information characteristics CMOS transistor-pairs linear-circuit applications, File Number 619, data sheet CA3600E "CMOS Transistor Array".
OUTPUT VOLTAGE (TERMINALS 17.5 12.5 12.5 17.5 22.5 GATE VOLTAGE (TERMINALS SUPPLY VOLTAGE: 25oC LOAD RESISTANCE
OFFSET NULL
NOTES: Total supply voltage (for indicated voltage gains) with input terminals biased that Terminal potential +7.5V above Terminal Total supply voltage (for indicated voltage gains) with output terminal driven either supply rail. FIGURE BLOCK DIAGRAM CA3130 SERIES
Cascade-connected PMOS transistors constant-current source input stage. biasing circuit constant-current source subsequently described. small diodes through provide gate-oxide protection against high-voltage transients, including static electricity during handling
Second-Stage
Most voltage gain CA3130 provided second amplifier stage, consisting bipolar transistor cascade-connected load resistance provided PMOS transistors source bias potentials these PMOS transistors subsequently described. Miller Effect compensation (roll-off) accomplished simply connecting small capacitor between Terminals 47pF capacitor provides sufficient compensation stable unity-gain operation most applications.
Bias-Source Circuit
total supply voltages, somewhat above 8.3V, resistor zener diode serve establish voltage 8.3V across series-connected circuit, consisting resistor diodes through PMOS transistor junction resistor diode provides gate-bias potential about 4.5V PMOS transistors with respect Terminal potential about 2.2V developed across diode-connected PMOS transistor with respect Terminal provide gate bias PMOS transistors should noted that "mirror-connected (see Note both Since transistors designed identical, approximately 200µA current establishes similar current constant current
FIGURE VOLTAGE TRANSFER CHARACTERISTICS CMOS OUTPUT STAGE
CA3130, CA3130A
Input Current Variation with Common Mode Input Voltage
shown Table Electrical Specifications, input current CA3130 Series Amps typically 25oC when Terminals common-mode potential +7.5V with respect negative supply Terminal Figure contains data showing variation input current function common-mode input voltage 25oC. These data show that circuit designers advantageously exploit these characteristics design circuits which typically require input current less than 1pA, provided common-mode input voltage does exceed previously noted, input current essentially result leakage current through gate-protection diodes input circuit and, therefore, function applied voltage. Although finite resistance glass terminal-to-case insulator metal package also contributes increment leakage current, there useful compensating factors. Because gate-protection network functions connected Terminal potential, Metal case CA3130 also internally tied Terminal input Terminal essentially "guarded" from spurious leakage currents.
25oC
typical variation input bias current function temperature CA3130.
4000 1000 INPUT CURRENT (pA) ±7.5V
TEMPERATURE (oC)
FIGURE INPUT CURRENT TEMPERATURE
applications requiring lowest practical input current incremental increases current because "warm-up" effects, suggested that appropriate heat sink used with CA3130. addition, when "sinking" "sourcing" significant output current chip temperature increases, causing increase input current. such cases, heatsinking also very markedly reduce stabilize input current variations.
INPUT VOLTAGE
Input Offset Voltage (VIO) Variation with Bias Device Operating Life
well known that characteristics MOSFET device change slightly when gate-source bias potential applied device extended time periods. magnitude change increased high temperatures. Users CA3130 should alert possible impacts this effect application device involves extended operation high temperatures with significant differential bias voltage applied across Terminals Figure shows typical data pertinent shifts offset voltage encountered with CA3130 devices (metal package) during life testing. lower temperatures (metal plastic), example 85oC, this change voltage considerably less. typical linear applications where differential voltage small symmetrical, these incremental changes about same magnitude those encountered operational amplifier employing bipolar transistor input stage. 2VDC differential voltage example represents conditions when amplifier output stage "toggled", e.g., comparator applications.
-10V INPUT CURRENT (pA) CA3130
FIGURE INPUT CURRENT COMMON-MODE VOLTAGE
Offset Nulling
Offset-voltage nulling usually accomplished with 100,000 potentiometer connected across Terminals with potentiometer slider connected Terminal fine offset-null adjustment usually effected with slider positioned mid-point potentiometer's total range.
Input-Current Variation with Temperature
input current CA3130 Series circuits typically 25oC. major portion this input current leakage current through gate-protective diodes input circuit. with semiconductor-junction device, including amps with junction-FET input stage, leakage current approximately doubles every 10oC increase temperature. Figure provides data
CA3130, CA3130A
125oC TO-5 PACKAGES OFFSET VOLTAGE SHIFT (mV) 1000 1500 2000 2500 TIME (HOURS) 3000 3500 4000 DIFFERENTIAL VOLTAGE (ACROSS TERMINALS OUTPUT VOLTAGE DIFFERENTIAL VOLTAGE (ACROSS TERMINALS OUTPUT STAGE TOGGLED
increased current flow through (from positive supply) decreases correspondingly. When gate terminals driven increasingly negative with respect ground, current flow through increased current flow through decreased accordingly. Single-supply Operation: Initially, assumed that value very high disconnected), that inputterminal bias (Terminals such that output terminal (No. voltage V+/2, i.e., voltage drops across equal magnitude. Figure shows typical quiescent supply-current supply-voltage CA3130 operated under these conditions. Since output stage operating Class amplifier, supply-current will remain constant under dynamic operating conditions long transistors operated linear portion their voltage-transfer characteristics (see Figure either swung their linear regions toward cut-off non-linear region), there will corresponding reduction supply-current. extreme case, e.g., with Terminal swung down ground potential tied ground), NMOS transistor completely supply-current series-connected transistors goes essentially zero. preceding stages CA3130, however, continue draw modest supply-current (see lower curve Figure even though output stage strobed off. Figure shows dual-supply arrangement output stage that also strobed off, assuming pulling potential Terminal down that Terminal assumed that load-resistance nominal value (e.g., connected between Terminal ground circuit Figure assumed again that input-terminal bias (Terminals such that output terminal (No. voltage V+/2. Since PMOS transistor must supply quiescent current both transistor Q12, should apparent that under these conditions supply-current must increase inverse function magnitude. Figure shows voltagedrop across PMOS transistor function load current several supply voltages. Figure shows voltage-transfer characteristics output stage several values load resistance.
FIGURE TYPICAL INCREMENTAL OFFSET-VOLTAGE SHIFT OPERATING LIFE
CA3130
FIGURE DUAL POWER SUPPLY OPERATION
CA3130
FIGURE SINGLE POWER SUPPLY OPERATION FIGURE CA3130 OUTPUT STAGE DUAL SINGLE POWER SUPPLY OPERATION
Wideband Noise Power-Supply Considerations
Because CA3130 very useful single-supply applications, pertinent review some considerations relating power-supply current consumption under both single-and dual-supply service. Figures show CA3130 connected both dual-and single-supply operation. Dual-supply Operation: When output voltage Terminal currents supplied power supplies equal. When gate terminals driven increasingly positive with respect ground, current flow through (from negative supply) load From standpoint low-noise performance considerations, CA3130 most advantageous applications where source resistance input signal order more. this case, total input-referred noise voltage typically only 23µV when test-circuit amplifier Figure operated total supply voltage 15V. This value total input-referred noise remains essentially constant, even though value source resistance raised order magnitude. This characteristic fact that reactance input capacitance becomes significant factor shunting source resistance. should noted, however, that
CA3130, CA3130A
values source resistance very much greater than total noise voltage generated dominated thermal noise contributions both feedback source resistors.
+7.5V
with CMOS input logic, e.g., logic levels used circuit Figure circuit uses R/2R voltage-ladder network, with output potential obtained directly terminating ladder arms either positive negative power-supply terminal. Each CD4007A contains three "inverters", each "inverter" functioning single-pole double-throw switch terminate R/2R network either positive negative power-supply terminal. resistor ladder assembly tolerance metal-oxide film resistors. five arms requiring highest accuracy assembled with series parallel combinations 806,000 resistors from same manufacturing lot. single supply provides positive CA3130 follower amplifier feeds CA3085 voltage regulator. "scale-adjust" function provided regulator output control, nominal level this system. linevoltage regulation (approximately 0.2%) permits 9-bit accuracy maintained with variations several volts supply. flexibility afforded CMOS building blocks simplifies design systems tailored particular needs.
0.01µF NOISE VOLTAGE OUTPUT
0.01
30.1k
47pF -7.5V (-3dB) 200kHz TOTAL NOISE VOLTAGE (REFERRED INPUT) 23µV (TYP)
FIGURE TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USED WIDEBAND NOISE MEASUREMENTS
Typical Applications
Voltage Followers
Operational amplifiers with very high input resistances, like CA3130, particularly suited service voltage followers. Figure shows circuit classical voltage follower, together with pertinent waveforms using CA3130 split-supply configuration. voltage follower, operated from single supply, shown Figure together with related waveforms. This follower circuit linear over wide dynamic range, illustrated reproduction output waveform Figure with input-signal ramping. waveforms Figure show that follower does lose input-to-output phase-sense, even though input being swung 7.5V below ground potential. This unique characteristic important attribute both operational amplifier comparator applications. Figure also shows manner which CMOS output stage permits output signal swing down negative supply-rail potential (i.e., ground case shown). digital-to-analog converter (DAC) circuit, described later, illustrates practical CA3130 single-supply voltage-follower application.
Single-Supply, Absolute-Value, Ideal Full-Wave Rectifier
absolute-value circuit using CA3130 shown Figure During positive excursions, input signal through feedback network directly output. Simultaneously, positive excursion input signal also drives output terminal (No. inverting amplifier negative-going excursion such that 1N914 diode effectively disconnects amplifier from signal path. During negative-going excursion input signal, CA3130 functions normal inverting amplifier with gain equal -R2/R1. When equality equations shown Figure satisfied, full-wave output symmetrical.
Peak Detectors
Peak-detector circuits easily implemented with CA3130, illustrated Figure both peak-positive peak-negative circuit. should noted that with large-signal inputs, bandwidth peak-negative circuit much less than that peak-positive circuit. second stage CA3130 limits bandwidth this case. Negative-going output-signal excursion requires positive-going signal excursion collector transistor Q11, which loaded intrinsic capacitance associated circuitry this mode. other hand, during negative-going signal excursion collector Q11, transistor functions active "pull-down" mode that intrinsic capacitance discharged more expeditiously.
9-Bit CMOS
typical circuit 9-bit Digital-to-Analog Converter (DAC) shown Figure This system combines concepts multiple-switch CMOS lCs, low-cost ladder network discrete metal-oxide-film resistors, CA3130 connected follower, inexpensive monolithic regulator simple single power-supply arrangement. additional feature that readily interfaced
CA3130, CA3130A
+7.5V 0.01µF +15V
0.01µF
-7.5V 56pF 0.01µF 25pF
100k OFFSET ADJUST
56pF
(-3dB) 4MHz 10V/µs
0.1µF
0.1µF
Trace: Output Center Trace: Input FIGURE SMALL-SIGNAL RESPONSE (50mV/DIV., 200ns/DIV.)
FIGURE OUTPUT WAVEFORM WITH INPUT SIGNAL RAMPING (2V/DIV., 500µs/DIV.)
Trace: Output Signal; 2V/Div., 5µs/Div. Center Trace: Difference Signal; 5mV/Div., 5µs/Div. Bottom Trace: Input Signal; 2V/Div., 5µs/Div. FIGURE INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING SETTLING TIME (MEASUREMENT MADE WITH TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER) FIGURE SPLIT SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS
Trace: Output; 5V/Div., 200µs/Div. Bottom Trace: Input Signal; 5V/Div., 200µs/Div. FIGURE OUTPUT WAVEFORM WITH GROUND REFERENCE SINE-WAVE INPUT FIGURE SINGLE SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS. (E.G., SINGLE-SUPPLY CONVERTER; FIGURE AN6080)
CA3130, CA3130A
LOGIC INPUTS +10.010V CD4007A "SWITCHES" 806K 402K 200K 100K 806K 806K 806K 750K 806K 806K 806K 806K CD4007A "SWITCHES" CD4007A "SWITCHES" REQUIRED RATIO-MATCH STANDARD ±0.1% ±0.2% ±0.4% ±0.8%
NOTE: resistances ohms.
806K VOLTAGE REGULATOR CA3085 0.001µF 3.83k 22.1k +10.010V
PARALLELED RESISTORS +15V
+15V
OUTPUT LOAD REGULATED VOLTAGE
CA3130 VOLTAGE FOLLOWER
100K OFFSET NULL
56pF
0.1µF
FIGURE 9-BIT USING CMOS DIGITAL SWITCHES CA3130
+15V 0.01
CA3130
1N914 5.1k 100k OFFSET ADJUST
20pF
PEAK ADJUST
Gain 0.75 20VP-P Input: BW(-3dB) 230kHz, Output (Avg) 3.2V
0.5:
Trace: Output Signal; 2V/Div. Bottom Trace: Input Signal; 10V/Div. Time base both traces: 0.2ms/Div.
1VP-P Input: BW(-3dB) 130kHz, Output (Avg) 160mV
FIGURE SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
CA3130, CA3130A
6VP-P INPUT; (-3dB) 1.3MHz 0.3VP-P INPUT; (-3dB) 240kHz CA3130
6VP-P INPUT; +7.5V 0.01µF OUTPUT 1N914 0.01µF -7.5V (-3dB) 360kHz 0.3VP-P INPUT; (-3dB) 320kHz CA3130
+7.5V 0.01µF OUTPUT 1N914 0.01µF -7.5V
FIGURE 12A. PEAK POSITIVE DETECTOR CIRCUIT
FIGURE 12B. PEAK NEGATIVE DETECTOR CIRCUIT
FIGURE PEAK-DETECTOR CIRCUITS
CURRENT LIMIT
CA3086
56pF 25µF ERROR AMPLIFIER 100k VOLTAGE ADJUST OUTPUT 40mA
0.01µF
2.2k
+20V INPUT CA3086
CA3130
REGULATION LOAD FULL LOAD): <0.01% INPUT REGULATION: 0.02%/V NOISE OUTPUT: <25µV 100kHz
0.01
FIGURE VOLTAGE REGULATOR CIRCUIT 40mA)
CA3130, CA3130A
2N3055 2N2102 4.3k 3.3k
CURRENT LIMIT ADJUST
2N5294 1000pF 2.2k CA3086 ERROR AMPLIFIER 100µF
+55V INPUT
100µF
2N2102 CA3130
OUTPUT:
8.2k
VOLTAGE ADJUST
REGULATION LOAD FULL LOAD): <0.005% INPUT REGULATION: 0.01%/V NOISE OUTPUT: <250µVRMS 100kHz
FIGURE VOLTAGE REGULATOR CIRCUIT (0.1V
Error-Amplifier Regulated-Power Supplies
CA3130 ideal choice error-amplifier service regulated power supplies since function erroramplifier when regulated output voltage required approach zero. Figure shows schematic diagram 40mA power supply capable providing regulated output voltage continuous adjustment over range from 13V. CA3086 transistor-array function zeners provide supply-voltage CA3130 comparator (IC1). configured impedance, temperature-compensated source adjustable reference voltage error amplifier. Transistors (another CA3086 transistor-array connected parallel seriespass element. Transistor functions currentlimiting device diverting base drive from series-pass transistors, accordance with adjustment resistor Figure contains schematic diagram regulated power-supply capable providing regulated output voltage continuous adjustment over range from 0.1V currents error amplifier (lC1) circuitry associated with function previously described, although output boosted discrete transistor (Q4) provide adequate base drive Darlington-
connected series-pass transistors Transistor functions previously described current-limiting circuit.
Multivibrators
exceptionally high input resistance presented CA3130 attractive feature multivibrator circuit design because permits timing circuits with high ratios. circuit diagram pulse generator (astable multivibrator), with provisions independent control "on" "off" periods, shown Figure Resistors used bias CA3130 mid-point supply-voltage feedback resistor. pulse repetition rate selected positioning desired position rate remains essentially constant when resistors which determine "on-period" "off-period" adjusted.
Function Generator
Figure contains schematic diagram function generator using CA3130 integrator threshold detector functions. This circuit generates triangular square-wave output that swept over 1,000,000:1 range (0.1Hz 100kHz) means single control, voltage-control input also available remote sweepcontrol.
CA3130, CA3130A
heart frequency-determining system (OTA) (see Note 10), lC1, operated voltage-controlled current-source. output, current applied directly integrating capacitor, feedback loop integrator lC2, using CA3130, provide triangular-wave output. Potentiometer used adjust circuit slope symmetry positive-going negative-going signal excursions. Another CA3130, IC3, used controlled switch excursion limits triangular output from integrator circuit. Capacitor "peaking adjustment" optimize high-frequency square-wave performance circuit. Potentiometer adjustable perfect "amplitude symmetry" square-wave output signals. Output from threshold detector back resistor input toggle current source from plus minus generating linear triangular wave. amplifier circuit Figure employs feedback establish closed-loop gain 48dB. typical large-signal bandwidth (-3dB) 50kHz.
NOTE: file number technical information.
+15V
0.01µF 100k ON-PERIOD ADJUST 100k 100k 0.1µF 0.01µF 0.001µF CA3130 OUTPUT OFF-PERIOD ADJUST
Operation with Output-Stage Power-Booster
current-sourcing and-sinking capability CA3130 output stage easily supplemented provide power-boost capability. circuit Figure three CMOS transistorpairs single CA3600E (see Note array shown parallel connected with output stage CA3130. Class mode CA3600E shown, typical device consumes 20mA supply current operation. This arrangement boosts current-handling capability CA3130 output stage about 2.5X.
FREQUENCY RANGE: POSITION 0.001µF 0.01µF 0.1µF PULSE PERIOD 40µs 10ms 0.4ms 100ms
FIGURE PULSE GENERATOR (ASTABLE MULTIVIBRATOR) WITH PROVISIONS INDEPENDENT CONTROL "ON" "OFF" PERIODS
270k VOLTAGE-CONTROLLED CURRENT SOURCE +7.5V +7.5V 100k CA3080A (NOTE -7.5V +7.5V SLOPE SYMMETRY ADJUST VOLTAGE CONTROLLED INPUT 56pF FREQUENCY ADJUST (100kHz MAX) -7.5V -7.5V 100k AMPLITUDE SYMMETRY ADJUST -7.5V INTEGRATOR 100pF +7.5V HIGH FREQ. ADJUST 30pF
THRESHOLD DETECTOR 150k +7.5V CA3130
CA3130
-7.5V
NOTE: file number AN6668 technical information. FIGURE FUNCTION GENERATOR (FREQUENCY VARIED 1,000,000/1 WITH SINGLE CONTROL)
CA3130, CA3130A
+15V
0.01µF CA3600E (NOTE INPUT CA3130
750k
500µF
150mW 10%)
AV(CL) 48dB LARGE SIGNAL 50kHz
510k
NOTES: Transistors QP1, QP2, QN1, QN2, parallel connected with Q12, respectively, CA3130. file number 619. FIGURE CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED POWER BOOSTER OUTPUT STAGE CA3130
Typical Performance Curves
LOAD RESISTANCE OPEN LOOP VOLTAGE GAIN (dB) -100 OPEN LOOP VOLTAGE GAIN (dB) OPEN LOOP PHASE (DEGREES) SUPPLY VOLTAGE: 15V; 25oC -200 -300 -100
FREQUENCY (Hz)
TEMPERATURE (oC)
9pF, 0pF, 30pF, 15pF, 30pF, 47pF, 30pF, 150pF,
FIGURE OPEN LOOP GAIN TEMPERATURE
FIGURE OPEN-LOOP RESPONSE
CA3130, CA3130A Typical Performance Curves
17.5 QUIESCENT SUPPLY CURRENT (mA)
(Continued)
QUIESCENT SUPPLY CURRENT (mA) OUTPUT VOLTAGE V+/2 -55oC 25oC 125oC
12.5
LOAD RESISTANCE 25oC OUTPUT VOLTAGE BALANCED V+/2
OUTPUT VOLTAGE HIGH V2.5
TOTAL SUPPLY VOLTAGE
TOTAL SUPPLY VOLTAGE
FIGURE QUIESCENT SUPPLY CURRENT SUPPLY VOLTAGE
VOLTAGE DROP ACROSS PMOS OUTPUT STAGE TRANSISTOR NEGATIVE SUPPLY VOLTAGE 25oC POSITIVE SUPPLY VOLTAGE
FIGURE QUIESCENT SUPPLY CURRENT SUPPLY VOLTAGE
VOLTAGE DROP ACROSS NMOS OUTPUT STAGE TRANSISTOR NEGATIVE SUPPLY VOLTAGE 25oC POSITIVE SUPPLY VOLTAGE
0.01
0.01
0.001 0.001
0.01
0.001 0.001
0.01
MAGNITUDE LOAD CURRENT (mA)
MAGNITUDE LOAD CURRENT (mA)
FIGURE VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR (Q8) LOAD CURRENT
FIGURE VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR (Q12) LOAD CURRENT
CA3130, CA3130A Dual-In-Line Plastic Packages (PDIP)
INDEX AREA
E8.3 (JEDEC MS-001-BA ISSUE
LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES Rev. 12/93
0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
BASE PLANE SEATING PLANE 0.010 (0.25)
NOTES: Controlling Dimensions: INCH. case conflict between English Metric dimensions, inch dimensions control. Dimensioning tolerancing ANSI Y14.5M-1982. Symbols defined Series Symbol List" Section Publication Dimensions measured with package seated JEDEC seating plane gauge GS-3. dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010 inch (0.25mm). measured with leads constrained perpendicular datum measured lead tips with leads unconstrained. must zero greater. maximum dimensions include dambar protrusions. Dambar protrusions shall exceed 0.010 inch (0.25mm). maximum number terminal positions. Corner leads E8.3, E16.3, E18.3, E28.3, E42.6 will have dimension 0.030 0.045 inch (0.76 1.14mm).
0.100 0.300 0.115 0.430 0.150
2.54 7.62 10.92 3.81
2.93
CA3130, CA3130A Small Outline Plastic Packages (SOIC)
INDEX AREA SEATING PLANE 0.25(0.010)
M8.15 (JEDEC MS-012-AA ISSUE
LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 1.35 0.10 0.33 0.19 4.80 3.80 1.75 0.25 0.51 0.25 5.00 4.00 NOTES Rev. 6/05
0.0532 0.0040 0.013 0.0075 0.1890 0.1497
0.0688 0.0098 0.020 0.0098 0.1968 0.1574
0.10(0.004)
0.050 0.2284 0.0099 0.016 0.2440 0.0196 0.050
1.27 5.80 0.25 0.40 6.20 0.50 1.27
0.25(0.010)
NOTES: Symbols defined Series Symbol List" Section Publication Number Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.25mm (0.010 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. lead width "B", measured 0.36mm (0.014 inch) greater above seating plane, shall exceed maximum value 0.61mm (0.024 inch). Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact.
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Data Sheet August 2005 FN817.6 15MHz, BiMOS Operational Amplifier

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