Data Sheet February 2008 FN7510.0 Multiformat Video Crosspoint wi

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Data Sheet February 2008 FN7510.0 Multiformat Video Crosspoint wi

Datasheet Thumbnail

Top Searches for this datasheet

ISL59450
Data Sheet February 2008 FN7510.0
Multiformat Video Crosspoint with Integrated Sync Separator
ISL59450 video crosspoint switch supporting multiple video input formats (CVBS, S-Video, YPbPr, signals). Embedded anti-aliasing filters with programmable corner frequencies eliminate glitch noise from video DACs. large number inputs, wide range formats, integrated anti-aliasing filters, dual sync-separators make ISL59450 ideal choice video switching nearly display systems. ISL59450 available MQFP package specified operation over full -40°C +85°C temperature range.
Features
Composite, S-Video Component Video Sources Component Inputs Configured with Separate Sync Inputs Multi-format Video Filtering Compatible with Macrovision® Encoded Signals Programmable Gain Outputs have High Impedance Disable Mode Universal Sync Separators support Computer Signals Pb-free (RoHS compliant)
Ordering Information
PART NUMBER (Note) ISL59450IQZ PART MARKING ISL59450IQZ PACKAGE (Pb-free) MQFP PKG. DWG. MDP0055
Applications
Receivers LCD-TVs Switch Boxes Projectors HDTV Systems Multiple Video Input Systems
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate PLUS ANNEAL termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
Simplified Block Diagram
CVBSIN0 CVBSIN1 CVBSIN2 CVBSIN3 CVBSIN4 CVBSIN5 Restore CVBSOUTB CVBSOUTA
SvideoIN0 SvideoIN1 SvideoIN2 SvideoIN3
Restore
SvideoOUTA
SvideoOUTB
YPbPrIN0 YPbPrIN1 YPbPrIN2 YPbPrIN3
Restore
YPbPrOUTA
YPbPrOUTB
SOGs from Video Inputs HSYNCINA VSYNCINA HSYNCINB VSYNCINB Sync Processor Sync Processor HSYNCOUTA VSYNCOUTA HSYNCOUTB VSYNCOUTB
System Control
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. Rights Reserved. other trademarks mentioned property their respective owners.
ISL59450
Absolute Maximum Ratings
Voltage (referenced GNDA GNDD) 6.0V Voltage (referenced GNDA GNDD) 4.0V Voltage Analog Input -0.3V 0.3V Voltage Digital Input -0.3V 0.3V Current into Output ±20mA Classification Human Body Model 3000V Machine Model 125V
Thermal Information
Thermal Resistance (°C/W) MQFP Package 27.84 Maximum Biased Junction Temperature +150°C Storage Temperature .-65°C +150°C Pb-free Reflow Profile link below
Recommended Operating Conditions
Temperature (Commercial) .-40°C +85°C Supply Voltage. 5.0V, 3.3V
CAUTION: operate near maximum ratings listed extended periods time. Exposure such conditions adversely impact product reliability result failures covered warranty. IMPORTANT NOTE: parameters having Min/Max specifications guaranteed. Typical values information purposes only. Unless otherwise noted, tests specified temperature pulsed tests, therefore:
Electrical Specifications
5.0V, 3.3V, 0.7VP-P, +25°C, 150, VTIPINx 0.5V, VSLICEINx 0.6V, VLUMAx1INx VLUMAx2INx 0.8; VCHROMAx1INx VCHROMAx2INx 1.15V, frequency response measurements relative 100kHz, unless otherwise specified. CONDITIONS UNIT
PARAMETER
DESCRIPTION
YPbPr/RGB (Component) Video Inputs YPbPr-10MHz Passband Flatness, 10MHz Filter 6MHz, GAIN 6MHz, GAIN Cutoff Flatness, 10MHz Filter 10MHz, GAIN 10MHz, GAIN Stopband Rejection, 10MHz Filter 27MHz, GAIN 27MHz, GAIN 54MHz, GAIN 54MHZ, GAIN YPbPr-20MHz Passband Flatness, 20MHz Filter =12MHz, GAIN =12MHz, GAIN Cutoff Bandwidth, 20MHz Filter 20MHz, GAIN 20MHz, GAIN Stopband Rejection, 20MHz Filter 54MHz, GAIN 54MHz, GAIN YPbPr-36MHz Passband Flatness, 36MHz Filter 20MHz, GAIN 20MHz, GAIN Cutoff Bandwidth, 36MHz Filter 36MHz, GAIN 36MHz, GAIN Stopband Rejection, 36MHz Filter 108MHz, GAIN 108MHz, GAIN -1.5 -1.5 -3.6 -3.6 -1.6 -1.6 -4.7 -4.7 -1.6 -1.6 -4.2 -4.2 -1.1 -1.1 -2.7 -2.7 -0.9 -0.9 -2.3 -2.3 -2.7 -2.7 -0.4 -0.4 -1.3 -1.3 -0.4 -0.4 -1.5 -1.5 -0.4 -0.4 -1.5 -1.5
FN7510.0 February 2008
ISL59450
Electrical Specifications
5.0V, 3.3V, 0.7VP-P, +25°C, 150, VTIPINx 0.5V, VSLICEINx 0.6V, VLUMAx1INx VLUMAx2INx 0.8; VCHROMAx1INx VCHROMAx2INx 1.15V, frequency response measurements relative 100kHz, unless otherwise specified. (Continued) CONDITIONS 220MHz, GAIN 220MHz, GAIN Cutoff Bandwidth, Filter Bypassed GAIN GAIN Positive Slew Rate, Filter Bypassed VOUT 2VP-P, GAIN VOUT 2VP-P, GAIN Negative Slew Rate, Filter Bypassed VOUT 2VP-P, GAIN VOUT 2VP-P, GAIN S-Video VIDEO INPUTS SV-10MHz Passband Flatness, 10MHz Filter =7MHz, GAIN =7MHz, GAIN Cutoff Rejection, 10MHz Filter 11MHz, GAIN 11MHz, GAIN Stopband Rejection, 10MHz 27MHz, GAIN 27MHz, GAIN SV-Bypass Passband Flatness, Filter Bypassed Cutoff Rejection, Filter Bypassed CVBS (Composite) VIDEO INPUTS CVBS-7MHz Passband Flatness, 7MHz Filter 5MHz, GAIN 5MHz, GAIN Cutoff Rejection, 7MHz Filter 7MHz, GAIN 7MHz, GAIN Stopband Rejection, 7MHz Filter 27MHz, GAIN 27MHz, GAIN CVBS-Bypass Passband Flatness, Filter Bypassed Cutoff Rejection, Filter Bypassed Differential Gain 27MHz, GAIN 54MHz, GAIN 3.58MHz, GAIN 3.58MHz, GAIN Differential Phase 3.58MHz, GAIN 3.58MHz, GAIN VIDEO INPUTS INTER-XTALK Inter-Channel Crosstalk input Channel output Channel vice-versa, GAIN 10MHz -2.7 -2.7 -1.9 -7.2 -1.7 -1.7 -3.2 -3.2 -1.1 -3.8 0.45 0.65 -1.8 -1.8 -0.7 -2.7 27MHz, GAIN 54MHz, GAIN -2.3 -2.3 -5.5 -5.5 -2.3 -1.5 -1.5 -3.4 -3.4 -3.6 -0.8 -0.8 -0.8 -2.5 UNIT V/µs V/µs V/µs V/µs
PARAMETER YPbPr-Bypass
DESCRIPTION Passband Flatness, Filter Bypassed
FN7510.0 February 2008
ISL59450
Electrical Specifications 5.0V, 3.3V, +25°C, 150, VTIPINx 0.5V, VSLICEINx 0.6V,
VLUMAx1INx VLUMAx2INx 0.8; VCHROMAx1INx VCHROMAx2INx 1.15V, unless otherwise specified. PARAMETER DESCRIPTION Analog Supply Range Digital Supply Range Analog Supply Current output groups enabled Composite output enabled S-video output group enabled Component output group enabled IDISABLED Digital Supply Current Standby Supply Current Both sync separators enabled Disabled Analog Current, Disabled Digital Current, PSRR Power Supply Rejection GAIN output GAIN GAIN GAIN VOS-CLAMP Clamp Offset (Delta between external VREF reference input, GAIN reference voltage output during clamp) VREF reference input, GAIN IPULLDOWN ICLAMP VOUT (Useful DC-Coupling) Input Pulldown Current Clamp Pullup Current Clamp disabled, clamp enabled (sinking) S-Video, normal offset mode, clamp enabled (sourcing) Component/RGB, normal offset mode, clamp enabled (sourcing) S-Video, offset mode, clamp enabled (sourcing) Component/RGB, offset mode, clamp enabled (sourcing) Short Circuit Current 2.0V, Sourcing, Sinking, VOUT-LIN Output Linear Voltage Range 0.95 VREF 30mV VREF 30mV 0.45 CONDITIONS 1.05 VREF 30mV VREF 30mV UNIT
PSRRCLAMP_ON Rejection with Clamp Enabled Gain Frequency Gain
LOGIC INPUTS (SDA, SCL, Address, Reset, PowerDown, HSYNCINx, VSYNCINx, SDETx) Input High Voltage (HIGH) logic pins, except Reset Reset (Pin must >3.5V ensure part resetting) Input Voltage (LOW) Input High Current (VIN Logic Inputs, Sinking) pull-up pull-down Pins with 300k internal pull-downs: Address, Reset, Power-down pull-up pull-down Pins with 300k internal pull-up: SDETx
Input Current (VIN Logic Inputs, Sourcing)
FN7510.0 February 2008
ISL59450
Serial Interface (I2C) Specifications
SYMBOL PARAMETER Output Buffer Voltage Input Leakage Current Leakage Current 5.5V 5.5V CONDITIONS (Note (Note UNIT
TIMING CHARACTERISTICS fSCL tLOW tHIGH tSU:STA tHD:STA tHD:DAT Frequency Clock Time Clock HIGH Time START Condition Set-up Time START Condition Hold Time Input Data Hold Time Measured crossing. Measured crossing. rising edge falling edge. Both crossing From falling edge crossing falling edge crossing From falling edge crossing entering window. From rising edge crossing rising edge crossing From From Total on-chip off-chip
tSU:STO Cpin NOTE:
STOP Condition Set-up Time Rise Time Fall Time Capacitive Loading Capacitance
Parts 100% tested +25°C. Temperature limits established characterization production tested.
Timing
Diagram
tHIGH tLOW
tSU:STA tHD:STA (INPUT TIMING) tHD:DAT tSU:STO
(OUTPUT TIMING)
FN7510.0 February 2008
ISL59450 Functional Diagram
5.0V CVIN0 CVIN1 CVIN2 CVIN3 CVIN4 CVIN5 CVIN0 CVIN1 CVIN2 CVIN3 CVIN4 CVIN5 5.0V
Composite Channel
CVOUTA
Composite Channel
CVOUTB
SYNCCV 5.0V SYIN0 SCIN0 SYIN1 SCIN1 SYIN2 SCIN2 SYIN3 SCIN3 SYNCY-C 5.0V YIN0 PrIN0 PbIN0 YIN1 PrIN1 PbIN1 YIN2 PrIN2 PbIN2 YIN3 PrIN3 PbIN3 SYNCCOMP. 3.3V HSYNCINA VSYNCINA SYNC Separator HSYNCOUTA VSYNCOUTA GNDD DIGITAL CONTROL SIGNALS SYIN0 SCIN0 SYIN1 SCIN1 SYIN2 SCIN2 SYIN3 SCIN3
SYNCCV 5.0V
S-Video Channel
SYOUTA SCOUTA
S-Video Channel
SYOUTB SCOUTB
KEYED CLAMP TIMING (SLAVE MODE)
KEYED CLAMP TIMING (SLAVE MODE) YOUTA PrOUTA PbOUTA
SYNCY-C 5.0V YIN0 PrIN0 PbIN0 YIN1 PrIN1 PbIN1 YIN2 PrIN2 PbIN2 YIN3 PrIN3 PbIN3 SYNCCOMP. 3.3V CLAMPOUTA FIELDOUTA VSYNCINB SYNC Separator HSYNCINB
Component Channel
Component Channel
YOUTB PrOUTB PbOUTB
CLAMPOUTB FIELDOUTB HSYNCOUTB VSYNCOUTB GNDD
3.3V RESET ADDRESS GNDD Interface
FN7510.0 February 2008
ISL59450 Component Block Diagram
Component Control Register Bits SLICER VSLICE VTIP VLUMAx1 VLUMAx2 Clamp (from Sync Sep.) YIN0 YIN1 YIN2 YIN3 Component Control Register Bits Component Control Register Bits YOUT Component Control Register Sync Timing Sync Separator)
Component Control Register Bits
Clamp from Sync Separator
VCHROMAx1 VCHROMAx2 VLUMAx1 VLUMAx2
Component Control Register
PrIN0 PrIN1 PrIN2 PrIN3
Component Control Register Bits PrOUT
Component Control Register Bits
Component Control Register Bits
Clamp from Sync Separator
VCHROMAx1 VCHROMAx2 VLUMAx1 VLUMAx2
Component Control Register
PbIN0 PbIN1 PbIN2 PbIN3
Component Control Register Bits PbOUT
Component Control Register Bits
FN7510.0 February 2008
ISL59450 S-Video Block Diagram
S-Video Control Register Bits SLICER VSLICE VTIP VLUMAx1 VLUMAx2 Clamp (from Sync Sep.) SYIN0 SYIN1 SYIN2 SYIN3 S-Video Control Register S-Video Control Register Bits SYOUT S-Video Control Register Sync Timing Sync Separator)
S-Video Control Register
Clamp from Sync Separator
VCHROMAx1 VCHROMAx2
S-Video Control Register
SCIN0 SCIN1 SCIN2 SCIN3
S-Video Control Register S-Video Control Register Bits SCOUT
Composite Block Diagram
Composite Control Register Bits SLICER VSLICE VTIP VLUMAx1 VLUMAx2 Clamp (from Sync Sep.) CVIN0 CVIN1 CVIN2 CVIN3 CVIN4 CVIN5 Composite Control Register Composite Control Register Bits CVOUT Composite Control Register Sync Timing Sync Separator)
FN7510.0 February 2008
ISL59450 Sync Separator Block Diagram
Keyed Clamp Timing Signal Channels) other settings ClampOut Sync Separator Enable (bit Sync Separator control 1011 Sync Separator control bits HSYNCIN
Sync Separator control bits
FieldOut
SYNC from Composite SLICER
SYNC from S-Video SLICER
SYNC from Component SLICER
Sync Separator
Sync Separator control
VSYNCIN
HSYNCOUT VSYNCOUT
HSYNCIN
FN7510.0 February 2008
ISL59450 Typical Application Circuit
0.1µF 0.1µF 0.01µF 0.01µF +3.3V
COMPOSITE COMPOSITE COMPOSITE COMPOSITE COMPOSITE COMPOSITE 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF CVIN0 CVIN1 CVIN2 CVIN3 CVIN4 CVIN5
Powerdown
Address
Reset
CVOUTA CVOUTB
SYOUTA S-Video Luma S-Video Chroma S-Video Luma S-Video Chroma S-Video Luma S-Video Chroma S-Video Luma S-Video Chroma 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF SYIN0 SCIN0 SYIN1 SCIN1 SYIN2 SCIN2 SYIN3 SCIN3 YOUTA PrOUTA PbOUTA HSYNCOUTA VSYNCOUTA Component Luma Component Component Component Luma Component Component 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF YIN0 PbIN0 PrIN0 YIN1 PbIN1 PrIN1 YIN2 PbIN2 PrIN2 YOUTB PrOUTB PbOUTB HSYNC OUTB VSYNC OUTB VTIPINA VTIPINB VLUMAX1INA VLUMAX2INA HSYNC VSYNC Green Blue 0.1µF 0.1µF 0.1µF YIN3 PrIN3 HSYNC VSYNC VCHROMAX1INA VCHROMAX2INA VCHROMAX1INB CSETA 56nF 56nF CSETB VCHROMAX2INB 0.1µF VSLICE VSLICE 0.6V 0.1µF VLUMAX1INB VLUMAX2INB 0.1µF 0.5V SCOUTA SYOUTB SCOUTB S-Video S-Video
ISL59450
Green (SoG) Blue
HSYNC VSYNC
FN7510.0 February 2008
ISL59450 Pinout
ISL59450 (128 MQFP) VIEW
VCHROMAx2INA VCHROMAx1INA VLUMAx2INA VLUMAx1INA VSYNCINA ClampOUTA
VSLICEINA
HSYNCINA
VTIPINA
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GNDA
GNDA
CVIN0
GNDA
CVIN1
GNDD
CSETA
GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA
Field GNDA GNDA GNDA Address GNDD GNDD GNDA eset GNDD GNDA GNDA GNDA Field
CVIN4
CVIN5
GNDA
GNDA
GNDA
VCHROMAx2INB
VCHROMAx1INB
VLUMAx2INB
VLUMAx1INB
VSLICEINB
GNDD
GNDD
GNDD
GNDD
CSETB
HSYNCINB
GNDD
GNDD
ClampOUTB
GNDD
VTIPINB
VSYNCINB
GNDD
FN7510.0 February 2008
ISL59450 Descriptions
NUMBER NAME DESCRIPTION COMPOSITE (CV) VIDEO INPUTS (6x1) CVIN0 CVIN1 CVIN2 CVIN3 CVIN4 CVIN5 Composite Video Input Composite Video Input Composite Video Input Composite Video Input Composite Video Input Composite Video Input
COMPOSITE (CV) VIDEO OUTPUTS CVOUTA CVOUTB Composite Video Output with High-Z disable mode Composite Video Output with High-Z disable mode
S-VIDEO (SV) INPUTS (4x2) SYIN0 SCIN0 SYIN1 SCIN1 SYIN2 SCIN2 SYIN3 SCIN3 S-Video Luma Input S-Video Chroma Input S-Video Luma Input S-Video Chroma Input S-Video Luma Input S-Video Chroma Input S-Video Luma Input S-Video Chroma Input
S-VIDEO (SV) OUTPUTS SYOUTA SCOUTA SYOUTB SCOUTB S-Video Luma Output with High-Z disable mode S-Video Chroma Output with High-Z disable mode S-Video Luma Output with High-Z disable mode S-Video Chroma Output with High-Z disable mode
S-VIDEO CONNECTION DETECTION PINS SDET0 Digital Input with internal pull-up Detects S-Video connector switch S-Video connector, with other switch tied ground. cable attached, S-Video cable attached. 300k pull-up analog supply. Digital Input with internal pull-up Detects S-Video connector switch S-Video connector, with other switch tied ground. cable attached, S-Video cable attached. 300k pull-up analog supply. Digital Input with internal pull-up Detects S-Video connector switch S-Video connector, with other switch tied ground. cable attached, S-Video cable attached. 300k pull-up analog supply. Digital Input with internal pull-up Detects S-Video connector switch S-Video connector, with other switch tied ground. cable attached, S-Video cable attached. 300k pull-up analog supply.
SDET1
SDET2
SDET3
COMPONENT (YPbPr) VIDEO INPUTS (4x3) YIN0 PbIN0 PrIN0 YIN1 PbIN1 Luma component Green RGB) video input Chroma component Blue RGB) video input Chroma component RGB) video input Luma component Green RGB) video input Chroma component Blue RGB) video input
FN7510.0 February 2008
ISL59450 Descriptions (Continued)
NUMBER NAME PrIN1 YIN2 PbIN2 PrIN2 YIN3 PbIN3 PrIN3 DESCRIPTION Chroma component RGB) video input Luma component Green RGB) video input Chroma component Blue RGB) video input Chroma component RGB) video input Luma component Green RGB) video input Chroma component Blue RGB) video input Chroma component RGB) video input
COMPONENT VIDEO OUTPUTS YOUTA PbOUTA PrOUTA YOUTB PbOUTB PrOUTB Component Video Luma Output with High-Z disable mode Chroma component Blue Component) Video Output with High-Z disable Chroma component Component) Video Output with High-Z disable Component Video Luma Output with High-Z disable mode Chroma component Blue Component) Video Output with High-Z disable Chroma component Component) Video Output with High-Z disable
SYNC SEPARATOR INPUTS OUTPUTS HSYNCINA VSYNCINA CSETA HSYNCOUTA VSYNCOUTA FieldOUTA ClampOUTA Horizontal External Sync Source Sync Separator This signal pure HSYNC CSYNC. Vertical External Sync Source Sync Separator Sync Separator filter capacitor. Connect 0.056µF capacitor between this analog ground. Horizontal Sync Output Sync Separator Vertical Sync Output Sync Separator Field Flag Sync Separator field, high even field. External Clamp Timing Pulse Sync Separator (for timed back porch clamping)
SYNC SEPARATOR INPUTS OUTPUTS HSYNCINB VSYNCINB CSETB HSYNCOUTB VSYNCOUTB FieldOUTB ClampOUTB Horizontal External Sync Source Sync Separator This signal pure HSYNC CSYNC. Vertical External Sync Source Sync Separator Sync Separator filter capacitor. Connect 0.056µF capacitor between this analog ground. Horizontal Sync Output from Sync Separator Vertical Sync Output from Sync Separator Field Flag Sync Separator field, high even field. External Clamp Timing Pulse Sync Separator (for timed back porch clamping)
EXTERNAL REFERENCE LEVELS VCHROMAx2INA Analog Input. Chroma Reference Level DC-Restore when Channel This voltage sets midpoint voltage signal (S-Video) signals (Component video) Channel when gain When using YPbPr inputs YPbPr mode, this voltage sets clamp voltage Pr/R Pb/B signals Channel This input typically tied together with VCHROMAx2INB driven with same voltage. Analog Input. Chroma Reference Level DC-Restore when Channel This voltage sets midpoint voltage signal (S-Video) signals (Component video) Channel when gain When using YPbPr inputs YPbPr mode, this voltage sets clamp voltage Pr/R Pb/B signals Channel This input typically tied together with VCHROMAx1INB driven with same voltage.
VCHROMAx1INA
FN7510.0 February 2008
ISL59450 Descriptions (Continued)
NUMBER NAME VLUMAx2INA DESCRIPTION Analog Input. Luma Reference Level DC-Restore when Channel When using YPbPr inputs mode, this voltage sets clamp voltage Pr/R Pb/B signals Channel when gain When using YPbPr inputs YPbPr mode, this voltage sets clamp voltage Pr/R Pb/B signals Channel A.This input typically tied together with VLUMAx2INB driven with same voltage. signal clamped VTIPINA voltage master mode VLUMAx2INA slave mode. Analog Input. Luma Reference Level DC-Restore when Channel When using YPbPr inputs mode, this voltage sets clamp voltage signals Channel when gain This input typically tied together with VLUMAx1INB driven with same voltage. signal clamped VTIPINA voltage master mode VLUMAx1INA slave mode. Analog Input. Slicer comparator threshold extracting composite sync from video, Channel This voltage typically 0.07V above VTIPINA, creating sync slicing level 70mV. This input typically tied together with VSLICEINB driven with same voltage. Analog Input. Sync Reference Level DC-Restore, Channel This voltage sets level sync Channel output signal. This input typically tied together with VTIPINB driven with same voltage. mode (with Sync-on-Green), this sets black level channel. Analog Input. Chroma Reference Level DC-Restore when Channel This voltage sets midpoint voltage signal (S-Video) signals (Component video) Channel when gain When using YPbPr inputs YPbPr mode, this voltage sets clamp voltage Pr/R Pb/B signals Channel This input typically tied together with VCHROMAx2INA driven with same voltage. Analog Input. Chroma Reference Level DC-Restore when Channel This voltage sets midpoint voltage signal (S-Video) signals (Component video) Channel when gain When using YPbPr inputs YPbPr mode, this voltage sets clamp voltage Pr/R Pb/B signals Channel This input typically tied together with VCHROMAx1INA driven with same voltage. Analog Input. Luma Reference Level DC-Restore when Channel When using YPbPr inputs mode, this voltage sets clamp voltage signals Channel when gain This input typically tied together with VLUMAx2INA driven with same voltage. signal clamped VTIPINB voltage master mode VLUMAx2INB slave mode. Analog Input. Luma Reference Level DC-Restore when Channel When using YPbPr inputs mode, this voltage sets clamp voltage signals Channel when gain This input typically tied together with VLUMAx1INA driven with same voltage. signal clamped VTIPINB voltage master mode VLUMAx1INB slave mode. Analog Input. Slicer comparator threshold extracting composite sync from video, Channel This voltage typically 0.07V above VTIPINB, creating sync slicing level 70mV. This input typically tied together with VSLICEINA driven with same voltage. Analog Input. Sync Reference Level DC-Restore, Channel This voltage sets level sync Channel output signal. This input typically tied together with VTIPINA driven with same voltage. mode (with Sync-on-Green), this sets black level channel.
VLUMAx1INA
VSLICEINA
VTIPINA
VCHROMAx2INB
VCHROMAx1INB
VLUMAx2INB
VLUMAx1INB
VSLICEINB
VTIPINB
CONTROL Address Data Clock Digital Input with internal pull-down. Sets address: 0x84 tied low, 0x8C tied high. (300k pull-down)
RESET, ENABLE MISC. Reset PowerDown Digital Input, with 3.5V logic threshold 300k pull-down. normal operation. Taking Reset back initializes data registers 0x00. Digital Input with 300k pull-down. When this taken high, analog circuitry disabled minimize power consumption. PowerDown mode, outputs tri-stated while interface remains active register data retained.
POWER SUPPLIES Analog supply
FN7510.0 February 2008
ISL59450 Descriptions (Continued)
NUMBER NAME Analog supply output drivers DESCRIPTION
POWER SUPPLIES DIGITAL (3V) Digital Plus Supply Digital Supply Sync Separators
POWER SUPPLIES ANALOG GROUND (0V) GNDA 123, 124, Analog Ground
POWER SUPPLIES DIGITAL GROUND (0V) GNDD 105, 106, 107, 111, 112, 113, 115, UNUSED PINS Implemented. Connect these pins anything (leave floating). Digital Ground
Typical Performance Curves
SUPPLY CURRENT (mA) VOLTAGE INPUT LOAD OUTPUTS ENABLED
+5V, +3.3V, GND, +25°C, unless otherwise specified.
DIGITAL SUPPLY CURRENT (mA) INPUT LOAD BOTH SYNC SEPARATOR ENABLED VOLTAGE
FIGURE ANALOG SUPPLY CURRENT SUPPLY VOLTAGE
FIGURE DIGITAL SUPPLY CURRENT SUPPLY VOLTAGES
MAGNITUDE (dB) 700mVP-P 0.1M FILTER ENABLED MAGNITUDE (dB) 100M FILTER BYPASSED
FREQUENCY (Hz)
FILTER BYPASSED FILTER ENABLED 700mV 0.1M 100M FREQUENCY (Hz)
FIGURE COMPOSITE FREQUENCY RESPONSE (GAIN
FIGURE COMPOSITE FREQUENCY RESPONSE (GAIN
FN7510.0 February 2008
ISL59450 Typical Performance Curves
FILTER BYPASSED MAGNITUDE (dB)
+5V, +3.3V, GND, +25°C, unless otherwise specified. (Continued)
FILTER BYPASSED FILTER ENABLED 700mV 0.1M FREQUENCY (Hz)
MAGNITUDE (dB)
FILTER ENABLED
700mVP-P 0.1M
FREQUENCY (Hz)
100M
100M
FIGURE S-VIDEO FREQUENCY RESPONSE (GAIN
FIGURE S-VIDEO FREQUENCY RESPONSE (GAIN
COMPONENT 10MHz COMPONENT 20MHz COMPONENT 36MHz 700mVP-P 0.1M FREQUENCY (Hz)
COMPONENT BYPASS
100M
COMPONENT 10MHz COMPONENT 20MHz COMPONENT 36MHz 700mVP-P 0.1M FREQUENCY (Hz)
MAGNITUDE (dB)
MAGNITUDE (dB)
COMPONENT BYPASS
100M
FIGURE COMPONENT BANDWIDTH FREQUENCY RESPONSE (GAIN
FIGURE COMPONENT BANDWIDTH FREQUENCY RESPONSE (GAIN
-0.1 -0.2 -0.3 -0.4 -0.5 -0.6 40mVP-P 3.58MHz COMPOSITE OUTPUT FILTER ENABLED OUTPUT VOLTAGE GAIN GAIN
-0.1 -0.2 40mVP-P 3.58MHz COMPOSITE OUTPUT FILTER ENABLED OUTPUT LEVEL GAIN GAIN
FIGURE DIFFERENTIAL GAIN
FIGURE DIFFERENTIAL PHASE
FN7510.0 February 2008
ISL59450 Typical Performance Curves
+5V, +3.3V, GND, +25°C, unless otherwise specified. (Continued)
COMPOSITE INPUT TIMEBASE 100ns/DIV INPUT: 200mV/DIV OUTPUT: 500mV/DIV COMPOSITE INPUT
COMPOSITE OUTPUT GAIN FILTER ENABLED VTIP 0.5V TIMEBASE 10µs/div INPUT: 500mV/div OUTPUT: 1V/div GAIN FILTER ENABLED VTIP 0.5V COMPOSITE OUTPUT
FIGURE COLORBAR RESPONSE
FIGURE RESPONSE
TIMEBASE 500ns/DIV INPUT: 200mV/DIV OUTPUT: 500mV/DIV COMPOSITE INPUT
COMPONENT OUTPUT
GAIN FILTER ENABLED VTIP 0.5V
COMPOSITE OUTPUT 10MHz TIMEBASE 10ns/DIV VERTICLE SCALE: 500mV/DIV
FIGURE 12.5T RESPONSE
FIGURE COMPONENT LARGE SIGNAL PULSE RESPONSE GAIN
COMPONENT OUTPUT DELAY (ns) 10MHz TIMEBASE 10ns/DIV VERTICLE SCALE: 500mV/DIV 700mVP-P 0.1M FREQUENCY (Hz) 100M GAIN GAIN
FIGURE COMPONENT LARGE SIGNAL PULSE RESPONSE GAIN
FIGURE COMPOSITE GROUP DELAY
FN7510.0 February 2008
ISL59450 Typical Performance Curves
DELAY (ns) 700mVP-P 0.1M GAIN GAIN DELAY (ns)
+5V, +3.3V, GND, +25°C, unless otherwise specified. (Continued)
700mV 0.1M GAIN GAIN
FREQUENCY (Hz)
100M
FREQUENCY (Hz)
100M
FIGURE S-VIDEO GROUP DELAY
FIGURE COMPONENT 10MHz FILTER GROUP DELAY
GAIN DELAY (ns) DELAY (ns)
700mVP-P 0.1M GAIN GAIN
GAIN
700mVP-P 0.1M
FREQUENCY (Hz)
100M
FREQUENCY (Hz)
100M
FIGURE COMPONENT 20MHz FILTER GROUP DELAY
FIGURE COMPONENT 36MHz FILTER GROUP DELAY
DELAY (ns) 700mVP-P 0.1M GAIN CROSSTALK (dB) GAIN
FREQUENCY (Hz) 100M 0.1M FREQUENCY (Hz) 100M INPUT CHANNEL OUTPUT CHANNEL VICE-VERSA GAIN GAIN
FIGURE COMPONENT BYPASS GROUP DELAY
FIGURE INTER-CHANNEL CROSSTALK
FN7510.0 February 2008
ISL59450 Typical Performance Curves
CROSSTALK (dB) COMPOSITE INPUT COMPONENT OUTPUT FILTER ENABLED COMPOSITE INPUT S-VIDEO OUTPUT FILTER DISABLED COMPOSITE INPUT S-VIDEO OUTPUT FILTER ENABLED CROSSTALK (dB)
+5V, +3.3V, GND, +25°C, unless otherwise specified. (Continued)
S-VIDEO INPUT COMPOSITE OUTPUT FILTER ENABLED S-VIDEO INPUT COMPONENT OUTPUT FILTER DISABLED S-VIDEO INPUT COMPONENT OUTPUT FILTER ENABLED S-VIDEO INPUT COMPOSITE OUTPUT FILTER DISABLED
COMPOSITE INPUT COMPONENT OUTPUT FILTER DISABLED 0.1M FREQUENCY (Hz) 100M
0.1M
FREQUENCY (Hz)
100M
FIGURE INTRA-CHANNEL CROSSTALK: COMPOSITE COMPONENT/S-VIDEO
FIGURE INTRA-CHANNEL CROSSTALK: S-VIDEO COMPONENT/COMPOSITE
BYPASS MODE CROSSTALK (dB) CROSSTALK (dB) 0.1M 36MHz FILTER ENGAGED 20MHz FILTER ENGAGED 10MHz FILTER ENGAGED
BYPASS MODE FREQUENCY (Hz) 100M -100 0.1M FREQUENCY (Hz) 100M 10MHz FILTER ENGAGED 20MHz FILTER ENGAGED 36MHz FILTER ENGAGED
FIGURE INTRA-CHANNEL CROSSTALK: COMPONENT INPUT COMPOSITE OUTPUT
FIGURE INTRA-CHANNEL CROSSTALK: COMPONENT INPUT S-VIDEO OUTPUT
INPUT VIDEO SQUARE WAVE (BEFORE COUPLING CAPACITOR)
TIMEBASE 500µs/DIV INPUT: 500mV/DIV OUTPUT: 1V/DIV
INPUT VIDEO SQUARE WAVE (BEFORE COUPLING CAPACITOR)
TIMEBASE 500µs/DIV INPUT: 500mV/DIV OUTPUT: 1V/DIV
COMPOSITE S-VIDEO OUTPUT
COMPOSITE S-VIDEO OUTPUT
FILTER SETTING GAIN OFFSET
FILTER SETTING GAIN OFFSET
FIGURE COMPOSITE/S-VIDEO: CLAMP RESPONSE +250mV STEP INPUT (HIGH OFFSET MODE)
FIGURE COMPOSITE/S-VIDEO: CLAMP RESPONSE +250mV STEP INPUT (LOW OFFSET MODE)
FN7510.0 February 2008
ISL59450 Typical Performance Curves
INPUT VIDEO SQUARE WAVE (BEFORE COUPLING CAPACITOR)
+5V, +3.3V, GND, +25°C, unless otherwise specified. (Continued)
INPUT VIDEO SQUARE WAVE (BEFORE COUPLING CAPACITOR) TIMEBASE 500µs/DIV INPUT: 500mV/DIV OUTPUT: 1V/DIV
TIMEBASE 500µs/DIV INPUT: 500mV/DIV OUTPUT: 1V/DIV
YPrPb
YPrPb OUTPUT
FILTER SETTING GAIN OFFSET
FILTER SETTING GAIN OFFSET
FIGURE COMPONENT: CLAMP RESPONSE +250mV STEP INPUT (HIGH OFFSET MODE)
FIGURE COMPONENT: CLAMP RESPONSE +250mV STEP INPUT (LOW OFFSET MODE)
INPUT VIDEO SQUARE WAVE (BEFORE COUPLING CAPACITOR)
REJECTION (dB)
OUTPUT 200mVP-P
GAIN
OUTPUT
GAIN 100k FREQUENCY (Hz)
TIMEBASE 10Ms/DIV INPUT: 500mV/DIV OUTPUT: 1V/DIV
FILTER SETTING GAIN
FIGURE PULL-DOWN CURRENT RESPONSE
FIGURE PSRR FREQUENCY
POWER DISSIPATION AMBIENT TEMPERATURE (°C) MQFP +27.84°C/W
FIGURE PACKAGE POWER DISSIPATION
FN7510.0 February 2008
ISL59450 Functional Description
Signal Muxes
ISL59450 accepts composite, S-video component video sources. Each signal type routed into crosspoint with outputs. composite signals routed into mux, S-video inputs routed into double component video signals routed into triple mux. Each controlled through interface. Each signal type dedicated outputs, Signal types cannot routed different signal type outputs. example, S-video signal cannot routed composite outputs. luma CVBS) channels, DC-restore function either standard sync-tip clamp (Master Mode) slaved clamp signal generated from sync separator (Slave Mode). chroma Pr/Pb) channels, DC-restore function keyed clamp timed luma channel (Master Mode) timed clamp signal generated from sync separator (Slave Mode). clamping circuit restores AC-coupled video signal fixed level (VTIP, VLUMA). clamping circuit provides line-by-line restoration video sync level selected reference voltage during sync tip. mode) driven sync separator. clamps chroma channels (C/Pr/Pb) keyed clamps timed either luma (master mode) sync separator (slave mode). Clamp Disable clamp disabled each channel setting appropriate high Miscellaneous register (0x16). S-video component channels, additional action needs taken order completely disable clamps. S-video, setting Miscellaneous register disables pull-down pull-down current both luma chroma channel along with clamp pull-up current luma channel. However, does disable clamp pull-up current chroma channel unless sync separator that channel 0x25. component, setting Miscellaneous register disables pull-down pull-down current three channels, along with clamp pull-up current luma channel. However, does disable clamp pull-up current channels unless sync separator that channel 0x24. Offset Mode Setting Composite S-Video Channel registers increases maximum amount pull-up clamp current available from 130µA 270µA, which slightly reduces offset between reference output when clamp enabled. component channels, this setting enabled setting Miscellaneous register Channel Channel This mode increases maximum amount pull-up clamp current available from 270µA 500µA.
Clamp Modes
ISL59450 clamp modes: master slave. Each output group operate either mode. master mode, sync timing derived directly from video signal video levels clamped using this internal sync signal. slave mode, video sync derived from input groups corresponding sync separator external source connected corresponding sync separator. slave mode, sync timing come from HSYNCIN VSYNCIN derived from sync timing active video composite, S-video, component channels (see "Sync Separator Block Diagram" page slave mode, clamping occurs during sync selected video signal HSYNC signal (external HSYNC input).
References
Table shows references used clamping depending mode video input being used. VSLICE should usually 70mV 100mV above selected reference level luma.
TABLE CHANNEL REFERENCE LEVELS VIDEO OUTPUT Composite S-Video Luma S-Video Chroma Component: Luma/Green (YPrPb Mode) Component: Luma/Green (RGB Mode) MASTER MODE GAIN VTIP VTIP GAIN VTIP VTIP SLAVE MODE GAIN VLUMAx1 VLUMAx1 GAIN VLUMAx2 VLUMAx2
Filters
ISL59450 integrated anti-aliasing/smoothing filters video signals. Composite Video signals, user 7MHz pass filter bypass (40MHz bandwidth). S-video signals have 10MHz filter with bypass (43MHz). Component Video signals have user-selectable 36MHz, 20MHz, 10MHz filter, bypass (275MHz). filters selections made host interface.
VCHROMAx1 VCHROMAx2 VCHROMAx1 VCHROMAx2 VTIP VTIP VLUMAx1 VLUMAx2
VTIP
VTIP
VLUMAx1
VLUMAx2
Clamps
clamps luma composite channels sync clamps (master mode) timed keyed clamps (slave
FN7510.0 February 2008
ISL59450
TABLE CHANNEL REFERENCE LEVELS (Continued) VIDEO OUTPUT MASTER MODE GAIN GAIN SLAVE MODE GAIN GAIN
longer than vertical sync default delay time. horizontal output gives horizontal timing with pre/post equalizing pulses. sync separators allows user send independent sync information signals downstream devices. example would video decoders ADCs that used picture-in-picture application. Each sync separator dedicated respective channel, Sync Separator Channel Sync Separator Channel important note that syncs each channel cannot MUXed onto other channel. example, HSYNCINA VSYNCINA cannot MUXed HSYNCOUTB VSYNCOUTB. "Sync Separator Timing Diagrams" beginning page typical horizontal vertical sync output timing. VERTICAL SYNC low-going Vertical Sync pulse output during start vertical cycle incoming video signal. vertical cycle starts with pre-equalizing phase pulses with duty cycle about 93%, followed vertical serration phase that duty cycle about 15%. Vertical Sync clocked ISL59450 first rising edge during vertical serration phase. absence vertical serration pulses, vertical sync pulse will forced after vertical sync default delay time, approximately 60µs after last falling edge vertical equalizing phase. HORIZONTAL SYNC horizontal circuit senses composite sync edges produces true horizontal pulses nominal width standard definition NTSC signals. pulse width HSYNC output changes line frequency input signal changes. example, NTSC input generates HSYNCOUT with pulse width 5µs; while 720p video input generates HSYNCOUT with pulse width 1.9µs. leading edge triggered from leading edge input HSYNC with same propagation delay composite sync. half line pulses present input signal during vertical blanking removed with internal line eliminator circuit. This circuit that inhibits horizontal output pulses until line time reached, then horizontal output operation enabled again. signals present signal after true sync will ignored, thus horizontal output will effected MacroVision copy protection. When there loss sync, Horizontal Sync output held high. CSET Connect external capacitors from CSETA CSETB ground. CSET capacitor should grade better general capacitors leaky cause faulty operation. CSET capacitor should very close CSETA CSETB pins reduce possible board leakage. 56nF recommended. CSET capacitor rectifies pulse current creates voltage CSET.
FN7510.0 February 2008
VCHROMAx1 VCHROMAx2 VCHROMAx1 VCHROMAx2 Component: Pr/Pb (YPrPb Mode) Component: Pr/Pb (RGB Mode) VLUMAx1 VLUMAx2 VLUMAx1 VLUMAx2
Bypass each reference voltage with 0.01µF capacitor ground reduce noise injection.
TABLE SUGGESTED REFERENCE LEVELS REFERENCE VTIPINA VTIPINB VLUMAx1INA VLUMAx2INA VLUMAx1INB VLUMAx2INB VCHROMAx1INA VCHROMAx2INA VCHROMAx1INB VCHROMAx2INB VSLICEINA VSLICEINB VOLTAGE
Outputs/Levels
Each signal output selectable gain (GAIN (GAIN input sync separators video inputs, shown "Sync Separator Block Diagram" page HSYNC VSYNC inputs dedicated their respective sync separator (i.e. Sync Separator connect HSYNCINA VSYNCINA, HSYNCINB VSYNCINB).
Sync Separators
ISL59450 contains high performance video sync separators that automatically lock video signal. They will also extract sync timing information from non-standard video inputs presence Macrovision pulses. Composite sync, vertical sync horizontal sync outputs provided from each sync separator. Timing adjusted automatically various video standards. composite sync output follows video sync pulses vertical sync pulse output rising edge first vertical serration following vertical pre-equalizing string. non-standard vertical inputs, default vertical pulse output when vertical signal stays
ISL59450
CSET voltage converted bias current HSYNC VSYNC timing.
Layout Issues
Match channel-to-channel analog trace lengths layout symmetry. This will minimize propagation delay mismatches S-video component traces. signal lines should routed over continuous ground planes (i.e. split planes gaps under these lines). proper termination resistors close device possible. When testing, high quality connectors cables, matching cable types keep cable lengths minimum. Decouple well using minimum power supply decoupling capacitors (1000pF, 0.01µF), placed close devices possible. Vias between capacitor device unwanted inductance. Larger capacitors farther away.
Internal Control Registers
ISL59450 initialized controlled internal registers that define operating parameters entire device. Communication established between external controller ISL59450 through standard host port interface, described earlier. Register Listing table page describes these registers. Detailed programming information each register described "ISL59450 Serial Communications" page Note: write reserved registers. Reserved bits register should written with unless otherwise noted. INITIALIZATION recommended that registers initialized 0x00 toggling Reset after powering device. Once registers initialized, Miscellaneous Register engage global enable allow various channels powered
Power Dissipation
With high output drive capability ISL59450, possible exceed +125°C absolute maximum junction temperature under certain load current conditions. Therefore, important calculate maximum junction temperature application determine load conditions package types need modified assure operation amplifier safe operating area. maximum power dissipation allowed package determined according Equation
JMAX AMAX (EQ.
Logic Control Signals
Reset digital Input, with 3.5V logic threshold 300k pull-down. normal operation. Taking Reset back initializes data registers 0x00. Power-down digital input with 300k pull-down. When this taken high, analog circuitry disabled minimize power consumption. Power-down mode, outputs tri-stated while interface remains active register data retained.
Where: TJMAX Maximum junction temperature TAMAX Maximum ambient temperature
Thermal resistance package
Crosstalk Issues
input both channels references modes different. example, send CVIN0 both CVOUTA CVOUTB references Channel Channel different channel slave mode while other master mode. This could cause clamping conflicts compromise performance. lowest bandwidth setting suitable each application minimize noise, aliasing, crosstalk. "Typical Application Curves" page page
maximum power dissipation actually produced total quiescent supply current times total power supply voltage, plus power load, sourcing Equation
SMAX (EQ.
sinking Equation
SMAX LOAD (EQ.
Where: Supply voltage ISMAX Maximum quiescent supply current VOUT Maximum output voltage application RLOAD Load resistance tied ground ILOAD Load current
FN7510.0 February 2008
ISL59450 Register Listings
ISL59450 CONTROL ADDR. 0x00 FUNCTION Sync Separator Sync Output Polarity Sync Output Polarity Slave Mode Slave Mode Slave Mode Slave Mode Slave Mode Slave Mode Reserved Reserved Offset Mode Offset Mode Offset Mode Offset Mode Mode Mode DATA GREY READ ONLY, WHITE READ/WRITE Enable Reserved Reserved Output Amplifier Gain Output Amplifier Gain Output Amplifier Gain Output Amplifier Gain Output Amplifier Gain Output Amplifier Gain Sync Input Polarity Sync Input Polarity Filter Disable Filter Disable Filter Disable Filter Disable Filter Sync Type Input Select Input Select Input Select Input Select Input Select Input Select Input Select Input Select Input Select Input Select Input Select Input Select Input Select Input Select Input Select Input Select
0x01
Sync Separator
Enable
Sync Type
0x02
Composite Output
Enable
Input Select Input Select Reserved Reserved Filter
0x03
Composite Output
Enable
0x04
S-Video Output Group
Enable
0x05
S-Video Output Group
Enable
0x06
Component Video Output Group Component Video Output Group Reserved Ignore contents write these registers. Miscellaneous S-Video Connected. Field Invert Enable allows Field output signal inverted when "Sync Output Polarity" set. Global Enable: power standby mode with outputs highimpedance state, Powers internal reference Reserved Ignore contents write these registers. Miscellaneous
Enable
0x07
Enable
Filter
Filter
0x08 0x13 0x14
S-Video Connected
S-Video Connected
S-Video Connected
S-Video Connected
Reserved
Reserved
Field Invert Enable
Global Enable
0x15
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x16
Disable Component Component Clamp Offset Mode
Disable S-Video Clamp
Disable Component Disable Component Composite Clamp Offset Clamp Mode
Disable S-Video Clamp
Disable Composite Clamp
FN7510.0 February 2008
ISL59450 Register Descriptions
ADDRESS 0x00 REGISTER Sync Separator BIT(S) FUNCTION NAME Input Select DESCRIPTION Chooses sync source Sync Separator process. these bits conjunction with Sync Type directly below. Component (Channel S-Video (Channel Composite (Channel External CSYNC (Channel This must type incoming sync. CSYNC signals, this should set. HSYNC HSYNCA, VSYNC VSYNCA CSYNC HSYNCA This must depending polarity incoming sync. active external HSYNC/CSYNC. Active high external, HSYNC/CSYNC signal. This forces internal polarity HSYNC signal correct clamping. Please note setting this also inverts polarity HsyncA VsyncA outputs. "Typical Register Settings" page correct values. this Sync Separator disabled Sync Separator enabled this Polarity HsyncA VsyncA outputs Active Active High Note: Field Invert Enable (register 0x14b1) set, FieldA's output will also inverted when this set.
Sync Type
Sync Input Polarity
Reserved Enable Reserved Sync Output Polarity
FN7510.0 February 2008
ISL59450 Register Descriptions (Continued)
ADDRESS 0x01 REGISTER Sync Separator BIT(S) FUNCTION NAME Input Select DESCRIPTION Chooses sync source Sync Separator process. these bits conjunction with Sync Type directly below. Component (Channel S-Video (Channel Composite (Channel External CSYNC (Channel This must type incoming sync. CSYNC signals, this should set. HSYNC HSYNCB, VSYNC VSYNCB CSYNC HSYNCB This must depending polarity incoming sync. active external HSYNC/CSYNC. Active high external, HSYNC/CSYNC signal. This forces internal polarity HSYNC signal correct clamping. Please note setting this also inverts polarity HsyncB VsyncB outputs. "Typical Register Settings" page correct values. this Sync Separator disabled Sync Separator enabled this Polarity HsyncB VsyncB outputs Active Active High Note: Field Invert Enable (register 0x14b1) set, FieldB's output will also inverted when this set. CVBSIN0 CVBSIN1 CVBSIN2 CVBSIN3 CVBSIN4 CVBSIN5 7MHz Smoothing Filter Smoothing Filter bypassed (40MHz bandwidth)
Sync Type
Sync Input Polarity
Reserved Enable Reserved Sync Output Polarity
0x02
Composite Channel
Input Select
Filter Disable
Output Amplifier Gain Enable Offset Mode Disables (High-Z) Composite output Enables Composite output Normal Mode Offset Mode Slightly lowers offset from input output increasing maximum amount clamp restore current from 130µA 270µA. Sync DC-restore selected channel (master mode) DC-restore clamp timing slaved Sync Separator (slave mode)
Slave Mode
FN7510.0 February 2008
ISL59450 Register Descriptions (Continued)
ADDRESS 0x03 REGISTER Composite Channel BIT(S) FUNCTION NAME Input Select CVBSIN0 CVBSIN1 CVBSIN2 CVBSIN3 CVBSIN4 CVBSIN5 7MHz Smoothing Filter Smoothing Filter bypassed (40MHz bandwidth) DESCRIPTION
Filter Disable
Output Amplifier Gain Enable Offset Mode Disables (High-Z) Composite output Enables Composite output Normal Mode Offset Mode Slightly lowers offset from input output increasing maximum amount clamp restore current from 130µA 270µA. Sync DC-restore selected channel (master mode) DC-restore clamp timing slaved Sync Separator (slave mode) SvideoIN0 SvideoIN1 SvideoIN2 SvideoIN3 this 10MHz Smoothing Filter Smoothing Filter bypassed (40MHz bandwidth)
Slave Mode
0x04
S-Video Channel
Input Select
Reserved Filter Disable
Output Amplifier Gain Enable Offset Mode Disables (High-Z) S-Video outputs Enables S-Video outputs Normal Mode Offset Mode Slightly lowers offset output increasing maximum amount clamp restore current from 130µA 270µA. Sync DC-restore selected channel (master mode) DC-restore clamp timing slaved Sync Separator (slave mode)
Slave Mode
FN7510.0 February 2008
ISL59450 Register Descriptions (Continued)
ADDRESS 0x05 REGISTER S-Video Channel BIT(S) FUNCTION NAME Input Select SvideoIN0 SvideoIN1 SvideoIN2 SvideoIN3 this 10MHz Smoothing Filter Smoothing Filter bypassed (40MHz bandwidth) DESCRIPTION
Reserved Filter Disable
Output Amplifier Gain Enable Offset Mode Disables (High-Z) S-Video outputs Enables S-Video outputs Normal Mode Offset Mode Slightly lowers offset output increasing maximum amount clamp restore current from 130µA 270µA. Sync DC-restore selected channel (master mode) DC-restore clamp timing slaved Sync Separator (slave mode) YPbPrIN0 YPbPrIN1 YPbPrIN2 YPbPrIN3 10MHz Smoothing FIlter 20MHz Smoothing FIlter 36MHz Smoothing Filter Smoothing Filter Bypassed (250MHz bandwidth)
Slave Mode
0x06
Component Channel
Input Select
Filter Select
Output Amplifier Gain Enable Mode Disables (High-Z) Component outputs Enables Component outputs YPbPr Mode clamps VTIPINA (master mode) clamps VLUMAx1/2INA (slave mode) Pb/Pr clamps VCHROMAx1/2INA Mode clamps VTIPINA (master mode) clamps VLUMAx1/2INA (slave mode) Pb/Pr clamps VLUMAx1/2INA Sync DC-restore selected channel (master mode) DC-restore clamp timing slaved Sync Separator (slave mode)
Slave Mode
FN7510.0 February 2008
ISL59450 Register Descriptions (Continued)
ADDRESS 0x07 REGISTER Component Channel BIT(S) FUNCTION NAME Input Select YPbPrIN0 YPbPrIN1 YPbPrIN2 YPbPrIN3 10MHz Smoothing Filter 20MHz Smoothing Filter 36MHz Smoothing Filter Smoothing Filter Bypassed (250MHz bandwidth) DESCRIPTION
Filter Select
Output Amplifier Gain Enable Mode Disables (High-Z) Component outputs Enables Component outputs YPbPr Mode clamps VTIPINB (master mode) clamps VLUMAx1/2INB (slave mode) Pb/Pr clamps VCHROMAx1/2INB Mode clamps VTIPINB (master mode) clamps VLUMAx1/2INB (slave mode) Pb/Pr clamps VLUMAx1/2INB Sync DC-restore selected channel (master mode) DC-restore clamp timing slaved Sync Separator (slave mode) Reserved Write 0x00 these registers Reserved Write 0x00 these registers outputs disabled Outputs enabled their individual Enable settings Sync Output Polarity (Sync Separator) does affect Field polarity. Sync Output Polarity (Sync Separator) inverts Field output. this this Cable plugged S-Video Channel Nothing plugged S-Video Channel Cable plugged S-Video Channel Nothing plugged S-Video Channel Cable plugged S-Video Channel Nothing plugged S-Video Channel Cable plugged S-Video Channel Nothing plugged S-Video Channel Reserved
Slave Mode
0x08-0x0B 0x0C-0x0D 0x0E-0x11 0x12-0x13 0x14
Reserved (Read only) Reserved Reserved (Read only) Reserved Miscellaneous (Bits thru read-only)
Reserved Reserved Reserved Reserved Global Enable Field Invert Enable
0x15 Reserved
Reserved Reserved S-Video Connected S-Video Connected S-Video Connected S-Video Connected Reserved
FN7510.0 February 2008
ISL59450 Register Descriptions (Continued)
ADDRESS 0x16 REGISTER Miscellaneous BIT(S) FUNCTION NAME Disable Composite Clamp DESCRIPTION This disables DC-restore clamp composite Channel Composite clamp enabled Composite clamp disabled This disables DC-restore clamp luma S-Video Channel Disables pull-down currents both Does disable clamp chroma channel unless Slave mode Sync Separator. 0x25. S-Video clamp enabled S-Video clamp disabled Disable Component Clamp This disables DC-restore clamp component Channel Disables pull-down currents three channels. Does disable pull-up clamp Pr/R Pb/B unless Slave mode Sync Separator. 0x24. Component clamp enabled Component clamp disabled Component Offset Mode Normal operation DC-restore clamp lower offset. Slightly lowers offset component outputs increasing maximum amount clamp restore current from 250µA 500µA. This disables DC-restore clamp composite Channel Composite clamp enabled Composite clamp disabled This disables DC-restore clamp luma S-Video Channel Disables pull-down currents both Does disable clamp chroma channel unless Slave mode Sync Separator. 0x25. S-Video clamp enabled S-Video clamp disabled Disable Component Clamp This disables DC-restore clamp component Channel Disables pull-down currents three channels. Does disable clamps Pr/R Pb/B unless Slave mode Sync Separator. 0x24. Component clamp enabled Component clamp disabled Component Offset Mode Normal operation DC-restore clamp lower offset. Slightly lowers offset component outputs increasing maximum amount clamp restore current from 250µA 500µA.
Disable S-Video Clamp
Disable Composite Clamp
Disable S-Video Clamp
FN7510.0 February 2008
ISL59450 Typical Register Settings
REGISTER SETTINGS VIDEO TYPE CHANNEL REGISTER ADDRESS CHANNEL REGISTER ADDRESS CHANNEL REGISTER VALUE SYNC SEPARATOR REGISTER VALUE
settings, Miscellaneous Register (0x14) 0xX1 Miscellaneous (0x16) 0x00. Composite Composite Composite Composite Composite Composite S-Video S-Video S-Video S-Video Component Composite Composite Composite Composite Composite Composite S-Video S-Video S-Video S-Video Component Component Component Component Component Component Component RGB+HV 0x02 0x02 0x02 0x02 0x02 0x02 0x04 0x04 0x04 0x04 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x06 0x03 0x03 0x03 0x03 0x03 0x03 0x05 0x05 0x05 0x05 0x07 0x07 0x07 0x07 0x07 0x07 0x07 0x07 0x30 0x31 0x32 0x33 0x34 0x35 0x30 0x31 0x32 0x33 0x3C 0xFC 0x3D 0xFD 0x3E 0xFE 0x3F 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x23 (active sync 0xAB (active high sync 0x00 0x23 (active sync 0xAB (active high sync 0x00 0x23 (active sync 0xAB (active high sync 0x00 0x23 (active sync 0xAB (active high sync
FN7510.0 February 2008
ISL59450 Sync Separator NTSC Vertical Timing
SIGNAL COMPOSITE VIDEO INPUT, FIELD 1.5µs ±0.1µs TIME VERTICAL BLANKING INTERVAL
+63.5µs 1271µs -0µs
SYNC INTERVAL
START FIELD PREEQUALIZING PULSE INTERVAL
VERTICAL SYNC PULSE INTERVAL LINE VERTICAL INTERVAL
0.5H POSTEQUALIZING PULSE INTERVAL
SUBCARRIER PHASE, COLOR FIELD
SIGNAL VERTICAL SYNC OUTPUT
280µs SIGNAL HORIZONTAL SYNC OUTPUT
NOTES: composite sync output reproduces video input sync pulses, with propagation delay. Vertical sync leading edge coincident with first vertical serration pulse leading edge with propagation delay. Horizontal sync output produces true pulses nominal width 5µs. same delay composite sync.
Sync Separator NTSC Horizontal Timing
CONDITIONS: 3.3V, +25°C
COLOR BURST INPUT DYNAMIC RANGE 0.5V SYNC VSLICE VSYNC (SYNC VOLTAGE) SYNC LEVEL
WHITE LEVEL VIDEO
VBLANK (BLANKING LEVEL VOLTAGE)
SYNC
SYNC tdHOUT HOUT
tHOUT
FN7510.0 February 2008
ISL59450
PARAMETER tdHOUT tHOUT DESCRIPTION HOUT Timing Relative Input Horizontal Output Width CONDITIONS UNIT
Sync Separator HSYNC Timing 720p
CONDITIONS: 3.3V +25°C
SYNCIN
tdHOUT HOUT
tHOUT
PARAMETER tdHOUT tHOUT
DESCRIPTION HOUT Timing Relative Input Horizontal Output Width
CONDITIONS
3.3V 1.90
UNIT
ISL59450 Serial Communications
Overview
ISL59450 uses 2-wire serial communication with host. Serial Clock line, driven host, Serial Data line, which driven devices bus. open drain allow multiple devices share same simultaneously. Communication accomplished three steps: Host selects ISL59450 with which wishes communicate. Host writes initial ISL59450 Configuration Register address wishes write read from. Host writes reads from ISL59450's Configuration Register. ISL59450's internal address pointer auto increments, read registers 0x00 through 0x16, example, would write 0x00 step two, then repeat step four times, with each read returning next register value. ISL59450 7-bit address serial bus. upper 6-bits permanently 100010x, with determined state Address (Table This allows
ISL59450s independently controlled while sharing same bus. Address internal pull-down resistor pull terminal zero.
TABLE ADDRESS OPTIONS (MSB)
(Address) 0x85/0x84 0x87/0x86
nominally inactive, with high. Communication begins when host issues START command taking while high (Figure 34). ISL59450 continuously monitors lines start condition will respond command until this condition been met. host then transmits 7-bit serial address plus bit, indicating next transaction will Read (R/W Write (R/W address transmitted matches that device bus, that device must respond with ACKNOWLEDGE (Figure 35).
FN7510.0 February 2008
ISL59450
Once serial address been transmitted acknowledged, more bytes information written read from slave. Communication with selected device selected direction (read write) ended STOP command, where rises while high (Figure 34), second START command, which commonly used reverse data direction without relinquishing bus. Data serial must valid entire time high (Figure 36). achieve this, data being written ISL59450 latched delayed version rising edge SCL. delayed de-glitched inside ISL59450 three crystal clock periods (120ns 25MHz crystal) eliminate spurious clock pulses that could disrupt serial communication. When contents ISL59450 being read, line updated after falling edge SCL, delayed de-glitched same manner.
Configuration Register Write
Figure shows views steps necessary write more words Configuration Register.
Configuration Register Read
Figure shows views steps necessary read more words from Configuration Register.
START STOP
FIGURE VALID START STOP CONDITIONS
FROM HOST DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER
START
ACKNOWLEDGE
FIGURE ACKNOWLEDGE RESPONSE FROM RECEIVER
DATA STABLE DATA CHANGE DATA STABLE
FIGURE VALID DATA CHANGES
FN7510.0 February 2008
ISL59450
Signals beginning serial ISL59450 Device Select Address Write Addr first bits first byte select ISL59450 2-wire address Address pin. indicating next transaction will write. ISL59450 Register Address Write This address ISL59450's configuration register that following byte will written ISL59450 Register Data Write(s) This data written ISL59450's configuration register. Note: ISL59450's Configuration Register's address pointer auto increments after each data write. Repeat this step write multiple sequential bytes data Configuration Register. Signals ending serial
START Command ISL59450 Serial Address
(Repeat desired)
STOP Command Serial Address aaaaaaa0 Register Address AAAAAAAA Data Write* dddddddd
Signals from Host Signals from ISL59450
data write step repeated write ISL59450's Configuration Register sequentially, beginning Register Address written previous step.
FIGURE CONFIGURATION REGISTER WRITE
FN7510.0 February 2008
ISL59450
START Command ISL59450 Serial Address ISL59450 Device Select Address Write first bits first byte select ISL59450 2-wire address Address pin. indicating next transaction will write. ISL59450 Register Address Write This sets initial address ISL59450's configuration register subsequent reading. Ends previous transaction starts ISL59450 Serial Address Read This 7-bit address ISL59450 2-wire bus. address 0x85 low, 0x87 high. indicating next transaction(s) will read. ISL59450 Register Data Read(s) This data read from ISL59450's configuration register. Note: ISL59450's Configuration Register's address pointer auto increments after each data read. Repeat this step read multiple sequential bytes data from Configuration Register. Signals ending serial Serial Address aaaaaaa1 dddddddd Signals beginning serial
START Command ISL59450 Serial Address
(Repeat desired) STOP Command Serial Address aaaaaaa0
Signals from Host
Register Address AAAAAAAA
Data Read*
Signals from ISL59450
data read step repeated read from ISL59450's Configuration Register sequentially, beginning Register Address written previous steps.
FIGURE CONFIGURATION REGISTER READ
FN7510.0 February 2008
ISL59450 Metric Plastic Quad Flatpack Packages (MQFP)
MDP0055
14x20mm LEAD MQFP (WITH WITHOUT HEAT SPREADER) 3.2mm FOOTPRINT SYMBOL
20.000 ±0.100 (E1) 19.870 ±0.100 18.500
DIMENSIONS (MILLIMETERS) 3.40 0.250~0.500 2.750 ±0.250 0°~7° 0.220 ±0.050 0.200 ±0.030 17.200 ±0.250 14.000 ±0.100 23.200 ±0.250 20.000 ±0.100 0.500 Base 0.880 ±0.150 1.600 Ref. 0.170 ±0.060 0.152 ±0.040 0.100 0.100 Standoff
REMARKS Overall height Package thickness Foot angle Lead width Lead base metal width Lead Package length Lead Package width Lead pitch Foot length Lead length Frame thickness Frame base metal thickness Foot coplanarity Foot position Rev. 2/07
C0.600x0.350 (4X)
12.500 13.870 ±0.100 14.000 ±0.100 (D1) SECTION
AROUND
NOTES:
General tolerance: Distance ±0.100, Angle +2.5°.
Matte finish package body surface except ejection marking 0.8~2.0um).
DROP HEAT SPREADER STAND POINTS EXPOSED CONNECT ELECTRICALLY R0.25 AROUND 0.200 R0.13 0.13~0.30
molded body sharp corner RADII unless otherwise specified (Max RO.200). Package/Leadframe misalignment Max. 0.127 Top/Bottom misalignment Max. 0.127 Drawing does include plastic metal protrusion cutting burr.
Compliant JEDEC MS-022.
SEATING PLANE DETAIL
GAUGE PLANE 0.25 BASE
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
FN7510.0 February 2008

Data Sheet February 2008 FN7510.0 Multiformat Video Crosspoint wi

Top Searches for this datasheet

Other recent searches