Data Sheet July 2008 FN6651.1 FlexiHash+For Battery Authenticatio

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Data Sheet July 2008 FN6651.1 FlexiHash+For Battery Authenticatio

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ISL9206A
Data Sheet July 2008 FN6651.1
FlexiHash+For Battery Authentication
ISL9206A highly cost-effective fixed-secret hash engine based Intersil's second generation FlexiHashtechnology. device authentication achieved through challenge-response scheme customized low-cost applications, where cloning eavesdropping without knowledge device's secret code economically viable. When used intended applications, ISL9206A offers same level effectiveness other significantly more expensive high-maintenance hash algorithm authentication schemes. ISL9206A wide operating voltage range, suitable direct powering from 1-cell Li-ion/Li-Poly 3-cell series NiMH battery pack. ISL9206A also powered when pull-up voltage 3.3V higher. device connects directly cell terminals battery pack, includes on-chip voltage regulation circuit, POR, non-crystal based oscillator timing reference. Communication with host achieved through single wire interface light-weight subset Intersil's interface). compatible with serial ports offered 8250 compatible UART's single GPIO (General Purpose Input Output) microprocessor. clone prevention solution utilizing ISL9206A offers safety revenue protection lowest cost power, suitable protection against after-market replacement wide variety low-cost applications.
Features
Challenge-response based authentication scheme using 32-Bit challenge code 8-Bit authentication code. Fast flexible authentication process. Multi-pass authentication used achieve highest security level necessary. 16x8 stores three sets 32-Bit host-selectable secrets with additional programmable memory storage 48-Bits code and/or pack information. FlexiHash+engine uses sets 32-Bit secrets authentication code generation. Non-unique mapping secret 8-Bit authentication code maximizes hacking difficulty need exhaustive search (superior SHA-1). Supports 1-cell Li-ion/Li-Poly 3-cell series NiMH battery packs (2.6V 4.8V operation), powered bus. single-wire host interface communicates with 8250-compatible UART's single GPIO. Supports read data transfer bit-rate 23kbps. True "Zero Power" Sleep mode (automatically entered after inactivity time-out period) SOT-23 TDFN (2mmx3mm) packages -25°C +85°C operating temperature range Pb-free (RoHS compliant)
Ordering Information
PART NUMBER (Note) ISL9206ADHZ-T* PART TEMP. MARKING RANGE (°C) 206A PACKAGE (Pb-free) SOT-23 PKG. DWG. P5.064
Applications
Battery Pack Authentication Printer Cartridges Add-on Accessories Other Non-Monetary Authentication Applications
ISL9206ADRTZ-T*
TDFN L8.2x3A
*Please refer TB347 details reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, 100% matte plate plus anneal termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations). Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
Related Literature
Application Note AN1165 "ISL6296 Evaluation Kit" Application Note AN1167 "Implementing Host Using GPIO" Technical Brief TB363 "Guidelines Handling Processing Moisture Sensitive Surface Mount Devices (SMDs)"
Pinouts
ISL9206A TDFN) VIEW
ISL9206A SOT-23) VIEW
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL or1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. Rights Reserved. FlexiHash trademark Intersil Americas Inc. other trademarks mentioned property their respective owners.
ISL9206A
Absolute Maximum Ratings (Reference GND)
Supply Voltage (VDD) 5.5V Other Pins -0.5 0.5V Rating Human Body Model (Per MIL-STD-883 Method 3015.7) .4000V Machine Model (Per EIAJ ED-4701 Method C-111) .400V Charged Device Model .1000V
Thermal Information
Thermal Resistance (Typical) (°C/W) (°C/W) SOT-23 Package (Note TDFN Package (Notes 10.5 Maximum Junction Temperature (Plastic Package) +125°C Maximum Storage Temperature Range .-40°C +125°C Pb-free reflow profile .see link below
Recommended Operating Conditions
Ambient Temperature Range .-25°C +85°C
CAUTION: operate near maximum ratings listed extended periods time. Exposure such conditions adversely impact product reliability result failures covered warranty.
NOTES: measured with component mounted high effective thermal conductivity test board free air. Tech Brief TB379 details. measured free with component mounted high effective thermal conductivity test board with "direct attach" features. Tech Brief TB379. "case temp" location center exposed metal package underside.
Electrical Specifications
Unless otherwise noted, parameters established over operational supply voltage temperature range device follows: -25°C +85°C; 2.6V 4.8V; Parameters with and/or limits 100% tested +25°C, unless otherwise specified. Temperature limits established characterization production tested. SYMBOL TEST CONDITIONS UNITS
PARAMETER CHARACTERISTICS Supply Voltage
During normal operation During programming
Mode Supply Current (Exclude Current)
4.2V 4.8V 1.5V
Sleep Mode Supply Current Programming Mode Supply Current Internal Regulated Supply Voltage Internal Programming Voltage Release Threshold Assertion Threshold CHARACTERISTICS Input Voltage Input High Voltage Input Hysteresis Internal Pull-down Current
IDDS IDDP VPOR+ VPOR-
4.2V, floating 1.8ms duration write operation Observable only test mode Observable only test mode
0.15
VHYS 2.6V 4.2V 4.8V
-0.4
0.4V
Output Voltage Input Transition Time Output Fall Time Capacitance
CPIN
transition time 10%, CLOAD 12pF
FN6651.1 July 2008
ISL9206A
Electrical Specifications
Unless otherwise noted, parameters established over operational supply voltage temperature range device follows: -25°C +85°C; 2.6V 4.8V; Parameters with and/or limits 100% tested +25°C, unless otherwise specified. Temperature limits established characterization production tested. (Continued) SYMBOL TEST CONDITIONS UNITS
PARAMETER
TIMING CHARACTERISTICS (Refer Symbol Timing Definitions Tables beginning page Programming Rate Input De-glitch Time Device Wake-up Time Device Sleep Wait Time Auto-Sleep Time-out Period Write Time Hash Calculation Time tWDG tWKE tSLP tASLP tEEW tHASH Pulse width narrower than de-glitch time will cause device wake From falling-edge break command issued host falling-edge break command returned device From when `11' Opcode detected shut-off internal regulator From last transition detected device going into sleep mode From last write data frame when device ready accept next instruction From last Challenge Code Word from host Authentication Code being available read From last Soft-Reset instruction issued host falling-edge break command returned device 2.89 23.12
Soft-Reset Time
tSRST
Descriptions
SOT-23 NUMBER TDFN NUMBER NAME System ground. connection. Supply voltage. Production test pin. Used only during production testing. Must left floating during normal operation. Communication with weak internal pull-down VSS. This Schmitt-trigger input open-drain output. appropriate pull-up resistor required host side. DESCRIPTION
FN6651.1 July 2008
ISL9206A Typical Applications
PACK+ 5.1V PACKR2 PROTECTION 0.1µF
ISL9206A
FIGURE TYPICAL APPLICATION WITH ISL9206A POWERED BATTERY
PACK+ 5.1V PACK-
ISL9206A
0.1µF
PROTECTION
FIGURE TYPICAL APPLICATION WITH ISL9206A POWERED
Block Diagram
DIODE
POR/2.5V REGULATOR
OSCILLATOR ANALOG DIGITAL
COMM INTERFACE
DCFG BYTE) DTRM BYTE) SECRET BYTES) SECRET BYTES) SECRET BYTES) GENERAL PURPOSE BYTES) BYTES OTPROM CONTROL/STATUS/ TEST INTERFACE
AUTH SESL CHLG FLEXIHASH+ENGINE
DIODE
MSCR
STAT
FIGURE FUNCTIONAL BLOCK DIAGRAM
FN6651.1 July 2008
ISL9206A Theory Operation
ISL9206A contains circuitry required support battery pack authentication based challenge-response scheme. provides 16-Byte One-Time Programmable Read-Only Memory (OTPROM) space storage 96-Bit secret authentication other user information. 32-Bit hash engine (FlexiHash+TM) calculates authentication result immediately after receiving 32-Bit random challenge code. communication between ISL9206A host implemented through single-wire communication bus. Major functions within ISL9206A include following, shown Figure Power-on reset (POR) 2.5V regulator power internal logic circuits. 16x8-Bit (16-Byte) ROM, shown Table first part (two bytes) contains device default configuration (DCFG) information (such device address communication speed) default trimming (DTRM) information (such internal oscillator frequency trimming). second part contains groups (12-Byte) memory that independently locked storage three sets secret. last part provides additional bytes space general-purpose information. Control functions, including master control (MSCR) status (STAT) registers shown Table interrupt generation, test-related interface. FlexiHash+engine that includes 32-Bit highly non-linear proprietary hash engine, secret selection register, challenge code register, authentication result register. Table shows registers. communication Interface. device address communication speed configured DCFG address OTPROM, given Table Time Base Reference. following explains detail operation ISL9206A.
HOST BREAK DEVICE BREAK WAVEFORM 60µs 1.391
FIGURE WHEN HOST POWER-ON BREAK WIDER THAN 60µs
HOST BREAK
DEVICE BREAK WAVEFORM
FIGURE WHEN HOST POWER-ON NARROWER THAN 60µs FIGURE POWER-ON BREAK SIGNAL WAKE-UP ISL9206A FROM SLEEP MODE
Note that ISL9206A will initiate power-on sequence without waiting power-on `break' signal return high state. host sends initial `break' pulse wider than 60µs, device-ready `break' returned ISL9206A will likely merged with pulse sent host and, therefore, detectable. Figure illustrates waveforms during Power-on Reset. Figure represents case when power-on `break' rising edge occurs after device starts sending `break'. Figure represents case when power-on `break' finishes before device sends `break'. device break signal always 1.391 times device bit-time (BT, Interface section beginning page Either case Figure will wake-up device successfully device sleep mode. important keep mind that narrow `break' signal will taken normal signal cause errors, device sleep mode. this reason, narrow power-on `break' signal should used only user returned `break' signal.
Power-On Reset (POR)
ISL9206A powers Sleep mode. remains Sleep mode until power-on `break' command received from host through bus. initial power-on 'break' pulse width long wider than input deglitch time (20µs). Once `break' command received, internal regulator powered About 20µs after falling edge power-on `break', internal circuit releases reset digital block sequence started. During sequence, ISL9206A initializes itself loading default device configuration information from preassigned locations within memory. After initialization, `break' command returned host indicate that ISL9206A ready waiting transaction from host.
Auto-Sleep
While ISL9206A powered there activity more than about second, device will automatically return Sleep mode. Sleep mode entered independent whether held high low. While ISL9206A Sleep mode, recommended that held eliminate current drain through XSD-pin internal pull-down current. Auto-Sleep mode disabled clearing ASLP MSCR register. default, Auto-Sleep always enabled power-up after soft reset. Auto-sleep
FN6651.1 July 2008
ISL9206A
function permanently disabled clearing 0-00[2] (the ASLP DCFG) during programming. (STAT) registers. Functions that configured settings include: Device address (DAB[1:0]) speed (SPD[1:0]) Register default settings (eINT ASLP) read/write lock-out (SLO[1:0]) ISL9206A incorporates interrupt functions allow host quickly informed device status error conditions. Available interrupts summarized Table When interrupt enable set, 'break' command sent host whenever corresponding interrupt status set. After this, host should read STAT register immediately. following instruction frame from host does access STAT register, another `break' will sent immediately after receiving full instruction frame. This process repeated until host reads from STAT register. Upon reading STAT register, status bits will cleared. Refer Tables detailed explanations interrupt functions.
16-Byte memory based EEPROM technology incorporated into ISL9206A storage non-volatile information. contents (refer Table include, limited Device default settings (address 0-00) Factory programmed trim parameters (address 0-01) Device authentication secrets (address 0-02 0-0D) Pack information (address 0-0E 0-0F) memory written multiple times before lock-out bits (SLO[1:0] DCFG, Table set. SLO[1] (bit locks memory between 0-02 0-09 SLO[0] (bit locks memory between 0-0A 0-0D. These bits independently. Prior lock-out, memory written read directly through interface. After lock-out, writing addresses reading from secret code locations will permanently disabled after performing reset cycle. Writing EEPROM requires supply voltage maintained minimum 2.8V. Failure result unreliable programming total write failure. must written bytes time, 16-Bytes data read host single transaction. Only even addresses allowed read/write. 16-Byte read with allows entire content quickly verified simply checking byte. DTRM address stores default trimming parameters read-only address. DCFG DTRM (0-00 0-01 addresses) need written simultaneously data DRaddress ignored. writing process takes approximately 1.8ms two-bytes. While write process taking place, transaction allowed. Attempting access ISL9206A during on-going write process will result device ignoring access instruction issuing interrupt host. programming register based, performed pack manufacturer's facility.
FlexiHash+Engine
FlexiHash+engine contains 32-Bit highly non-linear proprietary hash engine three registers. Table lists three registers. 1-Byte secret selection (SESL) register selects sets secret (32-Bit each) from program hash engine. 4-Byte challenge code register (CHLG) receives challenge code from host through bus. Once challenge code received, hash engine generates 1-Byte authentication result code stores AUTH register host read. Figure shows data flow authentication process. following sections describe authentication process FlexiHash+encoding scheme detail. DEVICE AUTHENTICATION PROCESS start authentication process, host sends `break' command wake-up ISL9206A. Then host writes SESL register select sets secrets used authentication code generation. After that, host generates pseudo-random 4-Byte challenge code input into CHLG register initiate authentication process. Upon receiving fourth byte challenge code, ISL9206A immediately starts computing authentication code. Once computation completed, 8-Bit authentication code made available AUTH register host read out. host reads this code and, concurrently, calculates correct authentication code based challenge code generated same secrets chosen, finally compares result with authentication code read from device. codes match device fake device host shut
Device Control Status
ISL9206A control status register. control register read written host status register read only. Both registers contain device configuration information (see Table status register also contains device status information that lead interrupt signal host. Following host-initiated power-on `break' signal soft reset command, ISL9206A will configure default mode operation based information stored within DCFG address ROM. default configuration loaded into master control (MSCR) status
FN6651.1 July 2008
ISL9206A
itself down. flow chart Figure summarizes process that host needs execute.
32-BIT PSEUDO-RANDOM CHALLENGE WORD FROM HOST 64-BIT SECRET 32-BIT HASH FUNCTION 64-BIT HASH SEED START
WAKE ISL9206A USING REGULAR BREAK SIGNAL
SELECT HASH FUNCTION SEED WRITING SESL REGISTER FLEXIHASH+ENGINE
SEND 32-BIT RANDOM CHALLENGE CHLG REGISTER READ AUTHENTICATION RESULT FROM AUTH REGISTER, AFTER WAITING CALCULATE EXPECTED AUTHENTICATION RESULT BASED SAME SECRETS
8-BIT AUTHENTICATION CODE
FIGURE AUTHENTICATION PROCESS FLOW DIAGRAM
recommended that device authentication done once while maximize effectiveness. Before challenge code accepted device, SESL register must re-written again ensure that original seeds re-loaded from into hash engine prior performing next authentication code calculation. Failure follow sequence will result error, causing sBER flag STAT register. SET-UP DEVICE AUTHENTICATION SUPPORT configure host ISL9206A support device authentication function, pack manufacturer will need select least sets 32-Bit secret codes. greater security, third 32-Bit secret used. FlexiHash+engine requires sets 32-Bit secrets hash calculation: first define hash function, second initialize seed hash calculation. These sets selected from same secret location. chosen secret codes kept pack manufacturer maintained utmost confidentiality. After secrets have been determined, they written into device's ROM. After verifying that codes have been written correctly, relevant secrets' lock-out bits address location 0-00 should set. Once set, lock-out bits longer cleared. Thereafter, read/write access secret information will longer possible, secret codes made available only FlexiHash+engine generation authentication code based challenge code input from host. host side, same secret codes will need kept, same FlexiHash+engine will have implemented firmware. important that secret codes stored scrambled host's non-volatile memory that secret information cannot easily revealed monitoring signal transfer host PCB.
RESULTS MATCH?
SHUT DOWN SYSTEM
FIGURE FLOW CHART AUTHENTICATION PROCESS
HASH ENGINE hash engine consists cascade programmable highly non-linear proprietary encoders. Details proprietary encoder implementation will made available users under only.
FN6651.1 July 2008
ISL9206A
Host Interface
Communication with host achieved through XSD, light-weight subset Intersil's single-wire interface. programmable-rate pseudo-synchronous bidirectional host-initiated instruction-based serial communication interface that allows slave devices attached addressed separately. includes features enable quick reliable communication. communication protocol optimized efficient transfer data between device host. following list outlines features supported interface: Programmable bit-rate 23kbps devices connected host addressed separately 16-bit host instruction frame supports multi-byte register read write Built-in communication error detection generation capability Supports interrupt signaling Integrated inactivity detector automatic activation sleep mode PHYSICAL MODEL physical model shown Figure model shows single-wire connection between host device, including ground signal. input logic device side designed compatible with voltage between 1.8V 5.0V. host interface should contain open-drain open-collector output. pull-up resistor connected either host supply voltage VDDH device supply voltage VDDD. Typically, host supply voltage should used pull-up. DATA TRANSFER PROTOCOL initiate transaction, host first sends 16-bit instruction frame device, followed data byte frame(s) instruction write operation. instruction frame consists chip-select code, operation code, register bank address pointer, number data bytes information, shown Figure instruction read operation, device will return byte frames data back host. serial data transfer always takes place with first. following explains symbols transaction frames introduced later sections. SIGNALING SYMBOLS nominally held high. Various symbols commands generated active-low pulse width modulation. Following valid signaling symbols supported interface: break (issued host): used wake device from Sleep mode (Note: narrow `break' also used wake device from Sleep mode, described "Power-On Reset (POR)" page used reset device's counters time qualifiers used signal change communication channel (from slave device another) break (issued device): used `device-ready' indication host (after Soft-reset wake-up from Sleep mode) used interrupt indicator symbol: used instruction data coding symbol: used instruction data coding SYMBOL TIMING DEFINITIONS Symbol timings defined terms bit-time (BT), determined selected transfer bit-rate pre-programmed into device's location 0-00[5:4]. Selectable speeds are: 2.89kHz 0.5), 5.78kHz 11.56kHz 23.12kHz instruction data frame consists sequence and/or symbols. Figure illustrates timing definitions. symbol nominally wide while symbol nominally wide. symbol represented each period. detected pulse width less than 0.124 wide will interpreted glitch will result error. Table summarize timing definitions supported symbols signaling.
TABLE INTERRUPT EVENT SUMMARY CONDITION Write-inProgress Error Register Access Error INTERRUPT ENABLE eEEW (fixed) eINT eINT INTERRUPT STATUS FLAG sEEW sBER sACC INTERRUPT EVENT Accessing ISL9206A during on-going write process (used only during initial programming). error invalid instruction frame detected. Improper authentication sequence detected. Accessing protected registers.
FN6651.1 July 2008
ISL9206A
VDDH VDDD DEVICE HOST
OPEN-DRAIN Open-Drain PORT Port
Diode DIODE
Diode DIODE
1.5A
FIGURE CIRCUIT MODEL SERIAL
GLITCH glitch
BREAK Break
FIGURE SIGNAL TIMING DIAGRAM
TABLE HOST TIMING DEFINITIONS SYMBOLS SIGNALING PARAMETER Time De-glitch period pulse width pulse width `break' time SYMBOL 0.5, (Pulse Width) less than this will result frame error this range will interpreted code this range will interpreted code this range will interpreted `break' command 0.227 0.591 DESCRIPTION 173.6/x 0.124 0.453 0.824 UNIT
NOTE: Unless otherwise stated, pulse width (PW) referenced with respect active-low pulse. TABLE DEVICE TIMING DEFINITIONS SYMBOLS SIGNALING PARAMETER Time pulse width pulse width `break' time SYMBOL
BYTES BYTES ADDRESS ADDRESS BANK BANK
DESCRIPTION 0.5, code transmit pulse width code transmit pulse width this range will interpreted `break' command
164.2/x
172.8/x 0.304 0.696 1.391
181.4/x
UNIT
OPCODE OPCODE
FIGURE 16-BIT INSTRUCTION FRAME FIELD DEFINITION
FN6651.1 July 2008
ISL9206A
TABLE DEFINITION OPCODE FIELD OPCODE DESCRIPTION Write Operation Read Operation (normal) Write device register Read from device register ACTION
Read Operation (with CRC) Read from device register. Append 1-Byte last read frame. Sleep Mode Activation Immediately sets device Sleep mode. Note: After detecting `11' Opcode, device immediately enters sleep mode. more than bits sent, subsequent pulses wake device again.
Access Instruction Frame
access instruction frame shown Figure instruction frame consists bits digital signal with contents described following. FIELD field 1-bit Chip Address Selection. initial 1-bit Chip Address code pre-programmed into device's address location 0-00[7:6] time chip manufacture, re-programmed pack manufacturer needed. code instruction does match device's Chip Address code, instruction, subsequent frames that follow, will ignored until break command received. OPCODE FIELD OPCODE 2-bit field that defines operation transaction following instruction frame. operations described Table BANK FIELD memories ISL9206A divided into four banks. BANK field defined Table
TABLE BANK FIELD DEFINITION. BANK MEMORY/REGISTER BANK SELECTION Control Status Registers Device Authentication Registers Test Registers (Reserved)
ADDRESS FIELD address field indicates starting address memory register read write sequence. Keep mind that only starting addresses allowed access. BYTES FIELD bytes field indicates number data bytes read write, including byte. BYTES Field settings supported. Only settings marked with valid particular instruction, indicated Table Attempting read write with invalid BYTES setting yield unpredictable results. Writing occur only bytes time, reading from happen bytes time. Writing reading from other byte denomination will yield unpredictable results should therefore strictly prohibited.
Transaction Protocol
ISL9206A defines three types transactions. Figure shows transaction protocol. blue color represents signal sent host green color stands signal sent device. Before transaction starts, host should make sure that device sleep mode. method always send `break' signal before starting transaction, shown Figure device sleep mode, `break' signal mandatory. `break' pulse width appear wider than what host sends because reason explained Figure symbols Figure explained Table
TABLE DEFINITION BYTES FIELD BYTES FIELD DATA BYTES FOLLOW Invalid selection. Causes error. reading from only (prior lock-out). Invalid selection. Causes error. WRITE READ READ WRITE CHLG CODE WRITE COMMENTS Invalid selection. Causes error. Must 1-Byte read clearing STAT register.
FN6651.1 July 2008
ISL9206A
TABLE SYMBOLS TRANSACTION PROTOCOL SYMBOL IFGH IFGD DESCRIPTION Host inter-frame Device inter-frame Host turn-around time Device turn-around time 800ms 800ms
generation algorithm logically illustrated Figure Prior calculation, LFSR (linear feedback shift register) initialized zero. read data transmitted concurrently shifted into calculator. After actual data transmitted out, final content LFSR resulting value. This value transmitted after read data, with being transmitted first.
Passive Support
feature only supports read transaction ISL9206A. When OPCODE instruction `10', 8-Bit automatically calculated data bytes being transferred out. result then appended after last data byte read out. generated using polynomial shown Equation
Polynom
Analog Biasing Components Clock Generation
analog section ISL9206A mainly includes Time Base Generator internal regulator powering circuits ISL9206A. TIME BASE GENERATOR time base generator included on-chip provide timing reference serial data encoding decoding interface. This eliminates need external crystal. time base oscillator trimmed during manufacturing nominal frequency 532.5kHz. frequency tolerance better than over operating supply voltage temperature range.
IFGH IFGH DATA FRAME
(EQ.
BREAK break
WRITE INSTRUCTION FRAME
Write Instruction Frame
Data Frame
IFGH IFGH
DATA FRAME
Data Frame
FIGURE 10A. MULTI-BYTE WRITE INSTRUCTION
BREAK break
READ INSTRUCTIONFrame Read Instruction FRAME
Data Frame (OUPUT FROMslave) (output from SLAVE)
DATA FRAME
DATA FRAME
Data Frame
(OUPUT FROM SLAVE) (output from slave)
FIGURE 10B. MULTI-BYTE READ INSTRUCTION
BREAK break
READ INSTRUCTION FRAME
Read Instruction Frame
DATA FRAME Data Frame (OUPUT FROM slave) (output from SLAVE)
Next Instruction NEXT INSTRUCTION FRAME Frame
FIGURE 10C. BACK-TO-BACK TRANSACTION (READ FOLLOWED WRITE) FIGURE TRANSACTION PROTOCOL. `BREAK' SIGNAL OPTIONAL DEVICE AWAKE
Serial Serial SERIAL DATA Output Data
STAGE Stage
STAGE Stage
Stage STAGE
STAGE Stage
STAGE Stage
STAGE Stage
STAGE Stage
STAGE Stage
FIGURE CALCULATOR PASSIVE SUPPORT
FN6651.1 July 2008
ISL9206A
INTERNAL VOLTAGE REGULATOR ISL9206A incorporates internal voltage regulator that maintains nominal operating voltage 2.5V within device. regulator draws power directly from input. external component required regulate circuit voltage. regulator shut during Sleep mode. Power-on Reset occurs, soft reset issued. Table describes memory assignment. default factory setting address [0:00] given Table Bank contains Control Status registers. Only registers implemented. Table shows register Bank registers. Detailed descriptions register settings given Tables Bank contains Authentication registers. Only registers implemented. These registers used during battery pack authentication process. Table describes mapping Authentication registers. Bank reserved Intersil production testing only will accessible during normal operation. Accessing Test Trim Registers when test mode will result error.
Memory/Operational Register Description
ISL9206A memory register structure organized into banks addressable locations. However, addressable registers used implemented. Accessing unimplemented register will result access instruction being ignored. error indication flagged. Bank dedicated ROM. There memory locations implemented array. Writing immediate effect chip operation until
TABLE MEMORY (BANK ADDRESS 0-00 0-01 0-02 0-03 0-04 0-05 0-06 0-07 0-08 0-09 0-0A 0-0B 0-0C 0-0D 0-0E 0-0F NAME DCFG DTRM SE1A SE1B SE1C SE1D SE2A SE2B SE2C SE2D SE3A SE3B SE3C SE3D INF1 INF2 DESCRIPTION Default Configuration Default Trimming Auth Secret Auth Secret Auth Secret Auth Secret Auth Secret Auth Secret Auth Secret Auth Secret Auth Secret Auth Secret Auth Secret Auth Secret General Purpose General Purpose BIT3 eINT ASLP TOSC[3:0] S1A[7:0] S1B[7:0] S1C[7:0] S1D[7:0] S2A[7:0] S2B[7:0] S2C[7:0] S2D[7:0] S3A[7:0] S3B[7:0] S3C[7:0] S3D[7:0] General purpose non-volatile memory storage model date code, other cell information
DAB[1:0]
SPD[1:0] TIBB[2:0]
SLO[1:0]
NOTE: Information stored address 0-0E (INF1) 0-0F (INF2) host firmware only. Actual content depends host firmware customization preference. TABLE CONTROL STATUS REGISTERS (BANK ADDRESS 1-00 1-01 NAME MSCR STAT DESCRIPTION Master Control Device Status eEEW sEEW eINT sBER -sACC -BIT3 -DAB[1:0] -BIT ASLP SRST
SLO[1:0]
FN6651.1 July 2008
ISL9206A
TABLE AUTHENTICATION REGISTERS (BANK ADDRESS 2-00 2-01 2-05 NAME SESL CHLG AUTH DESCRIPTION Secrets Selection Challenge Code Register Authentication Code Register -BIT -BIT -BIT -CHLG[31:0] AUTH[7:0] BIT3
CSL[1:0]
SSL[1:0]
TABLE DEFAULT CONFIGURATION (DCFG) REGISTER SETTINGS NAME DAB[1:0] TYPE DEFAULT DESCRIPTION Device Address Setting: device responds only when field instruction frame is'0' device responds field value instruction frame device responds field value instruction frame device responds only when field instruction frame Speed Setting: Configures rate interface. 0.5x (2.89kbps) (5.78kbps) (11.56kbps) (23.12kbps) Power-on default setting eINT MSCR register. Power-on default setting ASLP MSCR register. Secrets Lock-out Bits: Read/Write lock-out address locations 0-02 0-09 (Secret Read/Write lock-out address locations 0-0A 0-0D (Secret NOTE: Once set, writing will permanently disabled (after reset cycle).
SPD[1:0]
eINT ASLP SLO[1:0]
TABLE DEFAULT TRIMMING (DTRM) REGISTER SETTINGS NAME TIBB[2:0] TOSC[3:0] TYPE DEFAULT -Unused Reference Current Trim Setting Oscillator Frequency Trim Setting DESCRIPTION
TABLE LEGEND TYPE COLUMN TYPE Read-only Write-only READ ACTION Data read Zeros read Data read Data read, then cleared Zeros read WRITE ACTION Data ignored Data written Data written Data ignored Data written, then cleared
ADDRESS 0-00: DEFAULT CONFIGURATION (DCFG) This address location stores default configuration when ISL9206A manufactured. Table describes each detail. legend TYPE column given Table ADDRESS 0-01: DEFAULT TRIM SETTING (DTRM) This address location writable only when device test mode. During normal operation, data written will ignored. Table describes DTRM address detail. ADDRESS 0-02/03/04/05: AUTHENTICATION SECRET (SE1A/B/C/D) These address locations store first secrets used hash calculation. Reading writing this register disabled setting SLO[1] location 0-00[1]. ADDRESS 0-06/07/08/09: AUTHENTICATION SECRET (SE2A/B/C/D) These address locations store second secrets used hash calculation. Reading writing this register disabled setting SLO[1] location 0-00[1].
Read/Write Clear after read Clear after write
Default setting loaded from designated locations Writing disabled after lock-out
FN6651.1 July 2008
ISL9206A
ADDRESS 0-0A/0B/0C/0D: AUTHENTICATION SECRET (SE3A/B/C/D) These address locations store optional third secrets used hash calculation. Reading writing this register disabled setting SLO[0] location 0-00[0]. Alternately, this memory space used store additional cell information which accessed host. this case, SLO[0] should set.
TABLE MASTER CONTROL REGISTER (MSCR) NAME eEEW TYPE DEFAULT <1/0> DESCRIPTION Write-in-Progress Interrupt Enable: When enabled, allows sEEW flag interrupt whenever sEEW interrupt event. eEEW fixed when none lock-out bits set. When both lock-out bits set, eEEW will become permanently after reset. Global Interrupt Enable: When enabled, allows sBER sACC flag interrupt host whenever respective interrupt events occur. (Default setting loaded from location 0-00[3]) Unused. Auto Sleep Mode Enable: When set, ISL9206A will automatically enter Sleep mode after about inactivity. When cleared, device only enter Sleep mode Opcode command. (Default setting loaded from location 0-00[2]) Soft Reset: When written, registers reset their default states, counters timers reset their start-up conditions, device configuration information reloaded from ROM. After reset sequence completed, `break' pulse sent host. TABLE DEVICE STATUS REGISTER (STAT) NAME sEEW sBER TYPE DEFAULT DESCRIPTION Write-in-Progress Flag: This when attempt made host read from write ISL9206A while still processing previous write instruction. Error Flag: This when more following occurs interface: invalid pulse width received activity detected before device completes power-up sequence invalid BYTES field instruction frame Improper authentication sequence detected Reading secret information after corresponding lock-out bits Register Access Error Flag: This whenever instruction frame attempts access protected register follows: Writing after ISL9206A been locked (any both lock-out bits set) Accessing ISL9206A's Test Trim Registers when device test mode Unused Device Address Setting: Loaded from location 0-00[7:6] during power-up. Secrets Lock-out Bits Setting: Loaded from location 0-00[1:0] during power-up.
eINT
-ASLP
SRST
sACC
-DAB[1:0] SLO[1:0]
<00> <00>
FN6651.1 July 2008
ISL9206A
TABLE SECRETS SELECTION REGISTER (SESL) NAME -CSL[1:0] TYPE DEFAULT 0000 Unused Coefficient Definition Secret Selection: Selects authentication secret code word stored used coefficient definition code FlexiHash+engine. invalid selection Authentication Secret Authentication Secret Authentication Secret Seed Secret Selection: Selects authentication secret code word stored used secret seed FlexiHash+engine. invalid selection Authentication Secret Authentication Secret Authentication Secret DESCRIPTION
SSL[1:0]
ADDRESS 0-0E/0F: GENERAL PURPOSE MEMORY (INF1/2) These address locations used store information like model date code, other cell information, which read host. ADDRESS 1-00: MASTER CONTROL REGISTER (MSCR) Master Control Register defined Table MSCR register both read written host through bus. ADDRESS 1-01: DEVICE STATUS REGISTER (STAT) STAT register defined Table status bits will cleared upon read this register. STAT read-only register. ADDRESS 2-00: SECRETS SELECTION REGISTER (SESL) This register must written re-load hash engine with secrets stored prior presenting challenge code word input. ADDRESS 2-01: CHALLENGE CODE INPUT REGISTER (CHLG) This register used input 32-Bit challenge code generated host device authentication. four bytes challenge code should written sequentially this register, starting with least-significant byte. After fourth challenge byte received, authentication code generation process will start. This CHLG write-only register. ADDRESS 2-05: AUTHENTICATION CODE OUTPUT REGISTER (AUTH) This register used output 8-Bit authentication code calculated from 32-Bit challenge code. register content read only once after each challenge code word written device. Subsequent read this register without challenge being input will result error condition.
Applications Information
Implementation
There ways implement host microprocessor. spare UART (Universal Asynchronous Receiver/Transmitter). GPIO (General Purpose Input/Output) used UART available communication. Refer application note AN1167 available from Intersil more information regarding implement within microprocessor.
Pull-up Resistor Selection
Since there internal pull-down current pin, shown Figure important choose pull-up resistor value that enough that small amount pull-down current through resistor does cause voltage droop below specification under condition. typical resistance used pull-up.
Powered
applications that device supply voltage lower than 2.6V (such application powered single-cell NiMH battery), device that power source all, ISL9206A powered bus. application circuit shown Figure condition such application circuit function properly that pull-up voltage 3.3V pull-up voltage will charge capacitor through internal diode, shown Figure diode 0.4V drop typically.
Rating
ISL9206A specification rated Human Body Model. When ISL9206A used handheld accessory, higher rating typically required. External components required enhance performance.
Additional Application Information
"Related Literature" page additional application information.
FN6651.1 July 2008
ISL9206A Small Outline Transistor Plastic Packages (SOT23-5)
P5.064
VIEW
LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS 0.90 0.00 0.90 0.30 0.30 0.08 0.08 2.80 2.60 1.50 1.45 0.15 1.30 0.50 0.45 0.22 0.20 3.00 3.00 1.70 NOTES SYMBOL 0.036 0.000 0.036 0.012 0.012 0.003 0.003 0.111 0.103 0.060 0.057 0.0059 0.051 0.020 0.018 0.009 0.008 0.118 0.118 0.067
0.20 (0.008)
SEATING PLANE
0.0374 0.0748 0.014 0.022 0.024 Ref. 0.010 Ref. 0.004 0.004 0.010
0.95 1.90 0.35 0.55 0.60 Ref. 0.25 Ref. 0.10 0.10 0.25
0.10 (0.004)
WITH PLATING
NOTES:
Rev. 9/03
BASE METAL
Dimensioning tolerance ASME Y14.5M-1994. Package conforms EIAJ SC-74 JEDEC MO178AA. Dimensions exclusive mold flash, protrusions, gate burrs.
GAUGE PLANE SEATING PLANE VIEW
Footlength measured reference gauge plane. number terminal positions. These Dimensions apply flat section lead between 0.08mm 0.15mm from lead tip. Controlling dimension: MILLIMETER. Converted inch dimensions reference only.
FN6651.1 July 2008
ISL9206A Thin Dual Flat No-Lead Plastic Package (TDFN)
0.15 0.15
L8.2x3A
LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL
0.70
NOMINAL 0.75 0.20
0.80 0.05
NOTES
INDEX AREA
0.20
0.25 2.00
0.32
VIEW
0.10
1.50
1.65 3.00
1.75
0.08
1.65
1.80 0.50
1.90
0.20 0.30
SEATING PLANE
SIDE VIEW
0.40
0.50
Rev. 6/04
(DATUM D2/2
NOTES:
INDEX AREA (DATUM
Dimensioning tolerancing conform ASME Y14.5-1994. number terminals. refers number terminals
E2/2
dimensions millimeters. Angles degrees. Dimension applies metallized terminal measured between 0.25mm 0.30mm from terminal tip. configuration identifier optional, must located within zone indicated. identifier either mold mark feature.
(Nd-1)Xe REF. BOTTOM VIEW (A1) SECTION "C-C" EVEN TERMINAL/SIDE TERMINAL 0.10
Dimensions exposed pads which provide improved electrical thermal performance. Nominal dimensions provided assist with Land Pattern Design efforts, Intersil Technical Brief TB389.
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
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FN6651.1 July 2008

Data Sheet July 2008 FN6651.1 FlexiHash+For Battery Authenticatio

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