Data Sheet 2008 FN2963.3 ARINC Interface Line Driver Circuit

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Data Sheet 2008 FN2963.3 ARINC Interface Line Driver Circuit

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HS-3182
Data Sheet 2008 FN2963.3
ARINC Interface Line Driver Circuit
HS-3182 monolithic dielectric ally isolated bipolar differential line driver designed meet specifications ARINC 429. This device intended used with companion chip, HS-3282 CMOS ARINC Interface Circuit, which provides data formatting processor interface function. logic inputs CMOS compatible. addition DATA DATA inputs, there also inputs CLOCK SYNC signals which AND'd with DATA inputs. This feature enhances system performance allows HS-3182 used with devices other than HS-3182. Three power supplies necessary operate HS-3182: +15V ±10%, -15V ±10%, ±5%. VREF used program differential output voltage swing such that VOUT (DIFF) ±2VREF. Typically, VREF ±5%, separate power supply used VREF which should exceed driver output impedance ±20% +25°C. Driver output rise fall times independently programmed through external capacitors connected inputs. Typical capacitor values 75pF high-speed operation (100kBPS), 300pF low-speed operation (12kBPS 14.5kBPS). outputs protected against overvoltage short circuit shown Block Diagram. HS-3182 designed operate over ambient temperature range -55°C +125°C, -40°C +85°C.
TABLE TRUTH TABLE SYNC DATA DATA AOUT BOUT COMMENTS Null Null
Features
RoHS/Pb-free Available SBDIP Package (100% Gold Termination Finish) CMOS Compatible Inputs Adjustable Rise Fall Times External Capacitors Programmable Output Differential Voltage VREF Input Operates Data Rates 100k Bits/s Output Short Circuit Proof Contains Overvoltage Protection Outputs Inhibited (0V) DATA DATA Inputs Both "Logic One" State DATA DATA Signals "AND'd" with Clock Sync Signals Full Military Temperature Range
Pinouts
HS-3182 SBDIP) VIEW
VREF SYNC DATA AOUT DATA BOUT
HS-3182 CLCC) VIEW
SYNC VREF DATA AOUT BOUT
Null High Null
DATA
-VREF +VREF +VREF -VREF
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 1997, 2007, 2008. Rights Reserved other trademarks mentioned property their respective owners.
HS-3182 Ordering Information
PART NUMBER HS1-3182-8 HS1-3182-9+ HS4-3182-8 ORDERING NUMBER 5962-8687901EA HS1-3182-9+ 5962-86879013A PART MARKING HS1-3182-8 HS1-3182-9+ HS4- 3182-8 TEMP. RANGE (°C) +125 +125 PACKAGE SBDIP, Solder Seal (Pb-free) SBDIP, Solder Seal (Pb-free) CLCC, Solder Seal PKG. DWG. D16.3 D16.3 J28.A
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations.
Block Diagram
OUTPUT DRIVER ROUT/2
DATA
LEVEL SHIFTER SLOPE CONTROL
AOUT
(14) CLOCK VREF SYNC (13) DATA LEVEL SHIFTER SLOPE CONTROL OUTPUT DRIVER ROUT/2 BOUT (11)
(16) CURRENT REGULATOR (12) OVER-VOLTAGE PROTECTION
Typical Application
NUMBERS INDICATED (16) (14) (12) AOUT HS-3182 ARINC DRIVER CIRCUIT 429D0 HS-3282 CMOS ARINC CIRCUIT 429D0 DATA (13) DATA LEAD BOUT (SEE NOTE) VREF CLOCK SYNC +15V
NUMBER -15V
NOTE: rise fall time outputs ARINC specified values Typical 75pF high speed 300pF speed operation. output levels ARINC specifications VREF.
FN2963.3 2008
HS-3182
Absolute Maximum Ratings
Voltage Between Terminals .40V VREF Logic Input Voltage -0.3V +0.3V Output Short Circuit Duration. (Note Output Overvoltage Protection. (Note
Thermal Information
Thermal Resistance (Typical) (°C/W) (°C/W) SBDIP Package CLCC Package Storage Temperature Range .-65°C +150°C Maximum Junction Temperature +175°C Pb-free reflow profile .see link below
Operating Conditions
Operating Voltage +15V ±10% -15V ±10% VREF (For ARINC 429) Operating Temperature Range HS-3182-9+ .-40°C +85°C HS-3182-8 .-55°C +125°C
Characteristics
Number Transistors Gates
CAUTION: operate near maximum ratings listed extended periods time. Exposure such conditions adversely impact product reliability result failures covered warranty.
NOTES: measured with component mounted effective thermal conductivity test board free air. Tech Brief TB379 details. "case temp" location center package underside. Heat sink required 100k bits/s +125°C output short circuit +125°C. fuses used output overvoltage protection blown fault each output greater than ±6.5V relative GND.
Electrical Specifications
Parameters with and/or limits 100% tested +25°C, unless otherwise specified. Temperature limits established characterization production tested.
PARAMETER Supply Current (Operating) Supply Current (Operating) Supply Current (Operating) Supply Current VREF (Operating) Logic Input Voltage Logic Input Voltage Output Voltage High (Output GND) Output Voltage (Output GND) Output Voltage Null Input Current (Input Low) Input Current (Input High) Output Short Circuit Current (Output High) Output Short Circuit Current (Output Low) Output Impedance NOTES:
SYMBOL ICCOP (+V) ICCOP (-V) ICCOP (V1) ICCOP (VREF) VNULL IOHSC IOLSC
CONDITIONS (Note Load 100k bits/s) Load 100k bits/s) Load 100k bits/s) Load 100k bits/s)
-1.0
VREF (+250mV) -VREF (+250mV) +250
UNITS
Load 100k bits/s) Load 100k bits/s) Load 100k bits/s)
VREF (-250mV) -VREF (-250mV) -250
Short Short +25°C
+15V ±10%, -15V ±10%, VREF ±5%, unless otherwise specified -40°C +85°C HS-3182-9+ -55°C +125°C HS-3182-8.
FN2963.3 2008
HS-3182
Electrical Specifications
PARAMETER Rise Time (AOUT, BOUT) SYMBOL CONDITIONS (Note 75pF, (Note -55°C Only) 300pF, (Note Fall Time (AOUT, BOUT) 75pF, (Note -55°C Only) 300pF, (Note Propagation Delay Input Output Propagation Delay Input Output NOTES: +15V, -15V, VREF unless otherwise specified -40°C +85°C HS-3182-9+ -55°C +125°C HS-3182-8. measured load. measured load. tPLH tPHL 75pF, Load 75pF, Load UNITS
Electrical Specifications
PARAMETER Input Capacitance Supply Current (Short Circuit) Supply Current (Short Circuit) NOTES: Limits established characterization production tested. SYMBOL (+V) (-V) +25°C Short GND, +25°C Short GND, +25°C CONDITIONS (NOTE -150 UNITS
Power Specifications
DATA RATE BITS/s) 12.5 NOTES: Load
Nominal Power +25°C, +15V, -15V, VREF Notes LOAD 11mA 24mA 46mA V-10mA -24mA -46mA 600µA 600µA 600µA CHIP POWER 325mW 660mW Watt POWER DISSIPATION LOAD 60mW 325mW
Full Load, Note Full Load, Note
Heat sink required 100k bits/s +125°C output short circuit +125°C. Thermal characteristics: T(CASE) T(Junction) (Junction Case) P(Dissipation). Where: T(Junction Max) +175°C (Junction Case) 10.9°C/W (6.1°C/W LCC) (Junction Ambient) 73.5°C/W (54.0°C/W LCC) Full Load ARINC 429: 30,000pF parallel between AOUT BOUT (See "Block Diagram" page Output Overvoltage Protection: fuses used output overvoltage protection blown fault each output greater than ±6.5V relative GND.
FN2963.3 2008
HS-3182 Driver Waveforms
ADJ.
DATA
DATA VREF AOUT
+4.75V +5.25V
ADJ. tPHL BOUT -VREF tPLH 2VREF
-VREF VREF
-4.75V -5.25V
+4.75V +5.25V
-4.75V -5.25V HIGH +9.5V +10.5V
DIFFERENTIAL OUTPUT
AOUT BOUT
NULL
-2VREF
NOTE: OUTPUTS UNLOADED -9.5V -10.5V
NOTES: measured measured -4.75V -5.25V 4.75V 5.25V
When Data input Logic state Data input Logic Zero state, AOUT equal VREF BOUT equal -VREF. This constitutes Output High state. Data Data both Logic Zero state causes both AOUT BOUT equal which designates output Null state. Data Logic Zero state Data Logic state causes AOUT equal -VREF BOUT equal VREF which Output state.
Burn-In Schematic
DATA HS-3182
DATA
NOTES: 0.03mF 500pF, +15.5V 0.5V -15.5V 0.5V +5.5V 0.5V 0.0mF decoupling capacitor required each three supply lines (+V, every Burn-In socket.
Ambient Temp. Max. +125°C. Package Lead Side Brazed DIP. Pulse Conditions 6.25kHz ±10%. delayed one-half cycle sync with 2.0V Min. 0.5V Max.
FN2963.3 2008
HS-3182 Ceramic Leadless Chip Carrier Packages (CLCC)
0.010
J28.A
MIL-STD-1835 CQCC1-N28 (C-4) CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL 0.060 0.050 0.022 0.006 0.442 0.100 0.088 0.028 0.022 0.460 MILLIMETERS 1.52 1.27 0.56 0.15 11.23 1.83 0.56 11.68 2.54 2.23 0.71 NOTES Rev. 5/18/94
0.072
0.300 0.150 0.442 0.460 0.460
7.62 3.81 11.68 11.68 7.62 3.81 0.38 1.02 0.51 1.14 1.14 1.90 0.08 1.40 1.40 2.41 0.038 11.68 1.27 11.23
0.010 PLANE PLANE
0.007
0.300 0.150 0.015 0.460 0.050 0.040 0.020 0.045 0.045 0.075 0.003 0.055 0.055 0.095 0.015
-FE1
NOTES: Metallized castellations shall connected plane terminals extend toward plane across least layers ceramic completely across ceramic layers make electrical connection with optional plane terminals.
Unless otherwise specified, minimum clearance 0.015 inch (0.38mm) shall maintained between metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) Symbol maximum number terminals. Symbols "ND" "NE" number terminals along sides length "E", respectively. required plane terminals optional plane terminals used) shall electrically connected. corner shape (square, notch, radius, etc.) vary manufacturer's option, from that shown drawing. Chip carriers shall constructed minimum ceramic layers. Dimension controls overall package thickness. maximum dimension package height before being solder dipped. Dimensioning tolerancing ANSI Y14.5M-1982. Controlling dimension: INCH.
FN2963.3 2008
HS-3182 Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
-A-DBASE METAL -Bbbb BASE PLANE SEATING PLANE SECTION LEAD FINISH
D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION
LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL eA/2 0.014 0.014 0.045 0.023 0.008 0.008 0.220 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS 0.36 0.36 1.14 0.58 0.20 0.20 5.59 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 2.54 7.62 3.81 3.18 0.38 0.13 0.13 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES Rev. 4/94
eA/2
0.100 0.300 0.150 0.125 0.015 0.005 0.005 0.200 0.060 105o 0.015 0.030 0.010 0.0015
NOTES: Index area: notch identification mark shall located adjacent shall located within shaded area shown. manufacturer's identification shall used identification mark. maximum limits lead dimensions shall measured centroid finished lead surfaces, when solder plate lead finish applied. Dimensions apply lead base metal only. Dimension applies lead plating finish thickness. Corner leads N/2, N/2+1) configured with partial lead paddle. this configuration dimension replaces dimension Dimension shall measured from seating plane base plane. Measure dimension four corners. Measure dimension from ceramic body nearest metallization lead. maximum number terminal positions. Braze fillets shall concave. Dimensioning tolerancing ANSI Y14.5M 1982. Controlling dimension: INCH.
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
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FN2963.3 2008

Data Sheet 2008 FN2963.3 ARINC Interface Line Driver Circuit

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