Data Sheet October 2008 FN2809.8 16-Bit Numerically Controlled Os
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HSP45106
Data Sheet October 2008 FN2809.8
16-Bit Numerically Controlled Oscillator
Intersil HSP45106 high performance 16-bit quadrature Numerically Controlled Oscillator (NCO16). NCO16 simplifies applications requiring frequency phase agility such frequency-hopped modems, modems, spread spectrum communications, precision signal generators. shown block diagram, HSP45106 divided into Phase Frequency Control Section (PFCS) Sine/Cosine Section. inputs Phase/Frequency Control Section consist microprocessor interface individual control lines. frequency resolution bits, which provides resolution better than 0.008Hz 33MHz. User programmable center frequency offset frequency registers give user capability perform phase coherent switching between sinusoids different frequencies. Further, programmable phase control register allows phase control better than 0.006°. applications requiring 8-level PSK, three discrete inputs provided simplify implementation. output PFCS 28-bit phase which input Sine/Cosine Section conversion into sinusoidal amplitude. outputs Sine/Cosine Section 16-bit quadrature signals. spurious free dynamic range this complex vector greater than 90dBc. added flexibility when using NCO16 conjunction with DACs, choice either parallel serial outputs with either two's complement offset binary encoding provided. addition, synchronization signal available which indicates serial word boundaries.
Features
25.6MHz, 33MHz Versions 32-Bit Center Offset Frequency Control 16-Bit Phase Control 8-Level Supported Through Three Interface Simultaneous 16-Bit Sine Cosine Outputs Output Two's Complement Offset Binary <0.008Hz Tuning Resolution 33MHz Serial Parallel Outputs Spurious Frequency Components <-90dBc 16-Bit Microprocessor Compatible Control Interface Pb-Free available (RoHS compliant)
Applications
Direct Digital Synthesis Quadrature Signal Generation Spread Spectrum Communications Modems Modulation FSK, (BPSK, QPSK, 8PSK) Frequency Hopping Communications Precision Signal Generation Related Products with Data Acquisition Parts HI5731 HI5741
Ordering Information
PART NUMBER HSP45106JC-25 HSP45106JC-25Z (Note) HSP45106JC-33 HSP45106JC-33Z (Note) PART MARKING HSP45106JC-25 HSP45106JC-25Z HSP45106JC-33 HSP45106JC-33Z TEMP. RANGE (°C) PACKAGE PLCC PLCC (Pb-free) PLCC PLCC (Pb-free PKG. DWG. N84.1.15 N84.1.15 N84.1.15 N84.1.15
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, 100% matte plate plus anneal termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations). Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2004, 2008. Rights Reserved other trademarks mentioned property their respective owners.
HSP45106 Block Diagram
MICROPROCESSOR INTERFACE CLOCK DISCRETE CONTROL SIGNALS SIN/COS ARGUMENT
PHASE/ FREQUENCY CONTROL SECTION
SINE/ COSINE SECTION
SINE
COSINE
Pinouts
HSP45106 PLCC) VIEW
TICO COS15 COS14 COS13 COS12 COS11 COS10 COS9 COS8 COS7 COS6 COS5 COS4 COS3 COS2 COS1 COS0 DACSTRB
PMSEL MOD0 MOD1 MOD2 TEST ENCFREG ENOFREG INHOFR ENTIREG INITTAC ENPOREG INPHAC PACI INITPAC BINFMT PAR/SER
Descriptions
NAME C(15:0) A(2:0) ENPOREG TYPE power supply pin. Ground. Control input loading phase, frequency, timer data into PFCS. LSB. Address pins selecting destination C(15:0) data (Table Chip select (active low). Enables data written into Control Registers Write enable (active low). Data clocked into register selected A(2:0) rising edge when low. Clock. registers, except Control Registers clocked with clocked (when enabled) rising edge CLK. Phase Offset Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENPOREG enables clocking data into Phase Offset Register. Allows address updated regardless ENPHAC. Offset Frequency Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENOFREG enables clocking data into Offset Frequency Register. Center Frequency Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENCFREG enables clocking data into Center Frequency Register. DESCRIPTION
ENOFREG ENCFREG
SIN15 SIN14 SIN13 SIN12 SIN11 SIN10 SIN9 SIN8 SIN7 SIN6 SIN5 SIN4 SIN3 SIN2 SIN1 SIN0
FN2809.8 October 2008
HSP45106 Descriptions
NAME ENPHAC ENTIREG INHOFR TYPE (Continued) DESCRIPTION Phase Accumulator Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENPHAC enables clocking data into Phase Accumulator Register. Timer Increment Register Enable (active low). Registered chip CLK. When active, after being clocked onto chip, ENTIREG enables clocking data into Timer Increment Register. Inhibit Offset Frequency Register Output (active low). Registered chip CLK. When active, after being clocked onto chip, INHOFR zeroes data path from Offset Frequency Register Frequency Adder. data still clocked into Offset Frequency Register. INHOFR does affect contents register. Initialize Phase Accumulator (active low). Registered chip CLK. Zeroes feedback path Phase Accumulator. Does clear Phase Accumulator Register. Modulation Control Inputs. When selected with PMSEL line, these bits offset 135, 180, 225, 270, degrees current phase (i.e., modulate output). lower bits phase control zero. These bits registered when Phase Offset Register enabled. Phase Modulation Select input. Registered on-chip CLK. This input determines source data clocked into Phase Offset Register. When high, Phase Input Register selected. When low, external modulation pins (MOD(2:1)) control three most significant bits Phase Offset Register least significant bits zero. Phase Accumulator Carry Input (active low). Registered on-chip CLK. Initialize Timer Accumulator (active low). This input registered chip CLK. When active, after being clocked onto chip, INITTAC enables clocking data into Timer increment Register, also zeroes feedback path Timer Accumulator. Test Select Input. Registered chip CLK. This input active high. When active, this input enables test busses outputs instead sine cosine data. Parallel/Serial Output Select. This input registered chip CLK. When low, sine cosine outputs serial mode. Output Shift Registers will load data after ENPHAC goes will start shifting data after ENPHAC goes high. When this input high, Output Registers loaded every clock shifting takes place. Format. This input registered chip CLK. When low, inverted form offset binary (unsigned) number. Three-state control bits SIN(15:0). Outputs enabled when low. Three-state control bits COS(15:0). Outputs enabled when low. Timer Accumulator Carry Output. Active low, registered. This output goes when carry generated Timer Accumulator. Strobe (active low). serial mode, this output will when first output word valid shift register output. This active only serial mode. Sine Output Data. When parallel mode enabled, data output SIN(15:0). When serial mode enabled, output data bits shifted SIN15 SIN0. stream SIN15 provided first while stream SIN0 provided first. Cosine Output Data. When parallel mode enabled, data output COS(15:0). When serial mode enabled, output data bits shifted COS15 COS0. stream COS15 provided first while stream COS0 provided first. Used align chip socket circuit board. Must left connect circuit. (CPGA Package only).
INITPAC MOD(2:0)
PMSEL
PACI INITTAC
TEST PAR/SER
BINFMT TICO DACSTRB SIN(15:0)
COS(15:0)
Index
FN2809.8 October 2008
HSP45106 Functional Description
16-bit Numerically Controlled Oscillator (NCO16) produces digital complex sinusoid waveform whose frequency phase controlled through standard microprocessor interface discrete inputs. NCO16 generates 16-bit sine cosine vectors maximum sample rate 33MHz. NCO16 preprogrammed produce constant (CW) sine cosine output Direct Digital Synthesis (DDS) applications. Alternatively, phase frequency inputs updated real time produce PSK, FSK, modulated waveform. simplify generation, interface provided support modulation levels. shown Figure HSP45106 Block Diagram, NCO16 comprised Phase Frequency Control Section (PFCS) Sine/ Cosine Section. PFCS stores phase frequency control inputs uses them calculate phase angle rotating complex vector. Sine/Cosine Section performs lookup this phase generates appropriate amplitude values sine cosine. These quadrature outputs configured serial parallel with either two's complement offset binary format.
Phase/Frequency Control Section
phase frequency quadrature outputs controlled PFCS (see Figure PFCS generates 32-bit word which represents instantaneous phase (Sin/Cos argument) sine cosine waves being generated. This phase incremented rising edge each preprogrammed amounts phase Frequency Control Registers. instantaneous phase steps from through full scale (232 phase quadrature outputs proceeds from around unit circle counter clockwise. PFCS comprised Phase Accumulator Section, Phase Offset adder, Input Section, Timer Accumulator Section. Phase Accumulator computes instantaneous phase angle from user programmed values Center Offset Frequency Registers. This angle then into Phase Offset adder where offset preprogrammed value Phase Offset Register. Input Section routes data from microprocessor compatible control discrete input signals into appropriate configuration registers. Timer Accumulator supplies pulse mark passage user programmed period time.
FN2809.8 October 2008
R.ENPHAC TEST PAR/SER BINFMT
INPUT SECTION (DISCRETE CONTROL INPUT SIGNALS PROCESSOR CONTROL INTERFACE)
ADDRESS DECODE SIN/COS FORMAT CONTROL OUTPUT CONTROL
SIN(15:0) COS(15:0) DACSTRB
SIN/COS ARGUMENT
C(15:0)
PHEN A(2:0) PHEN MSCFEN LSCFEN MSOFEN LSOFEN MSTIEN LSTIEN
ENCODER CENTER FREQUENCY INPUT (16) CENTER FREQUENCY INPUT (16)
MOD(2:1)
PHASE INPUT (16)
PHASE INPUT
R.PMSEL
LSCFEN
CENTER FREQUENCY
CENTER FREQUENCY REGISTER
PHASE OFFSET PHASE OFFSET ADDER REGISTER LSBs MSBs R.ENPOREG FREQUENCY ADDER
MSTIEN
ENOFREG INHOFR INITPAC PACI ENPHAC ENTIREG INITTAC
R.ENOFREG
R.INHOFR R.INITPAC R.PACI R.ENPHAC R.ENTIREG R.INITTAC
PMSEL ENCFREG ENPOREG R.PMSEL R.ENCFREG R.ENPOREG
OFFSET FREQUENCY INPUT (16) OFFSET FREQUENCY INPUT (16)
R.ENCFREG
LSOFEN
TIMER INCREMENT INPUT (16) TIMER INCREMENT INPUT (16)
OFFSET FREQUENCY REGISTER OFFSET FREQUENCY R.ENOFREG R.INHOFR
HSP45106
PHASE ACCUMULATOR REGISTER PHASE ACCUMULATOR SECTION
R.INITPAC R.PACI R.ENPHAC
LSTIEN
TIMER INCREMENT TIMER INCREMENT REGISTER R.ENTIREG R.INITTAC
R.INITTAC
TIMER ACCUMULATOR SECTION
TICO
FN2809.8 October 2008
FIGURE BLOCK DIAGRAM HSP45106
HSP45106
Input Section
Input Section loads data C(15:0) into seven input registers, Center Frequency Input Registers, Offset Frequency Registers, Timer Input Registers, Phase Input Register. destination depends state A(2:0) when (Table
TABLE ADDRESS DECODE MAPPING MOD(2:0) DECODING FUNCTION Load least significant bits Center Frequency input. Load most significant bits Center Frequency input. Load least significant bits Offset Frequency input. Load most significant bits Offset Frequency input. Load least significant bits Timing Interval input. Load most significant bits Timing Interval input. Load Phase Register Reserved Input Disabled
frequency quadrature outputs based number clock cycles required step from full scale. number steps required this transition depends phase increment calculated frequency adder. example, Center Offset Frequency Registers programmed such that output Frequency Adder 4000 0000 hex, Phase Accumulator will step phase from 360° every clock cycles. Thus, 30MHz CLK, quadrature outputs will have frequency 30/4 7.5MHz. general, frequency quadrature output determined Equations
(EQ.
(EQ.
where bits frequency control word that programmed. integer computation. example, control word 20000000 hexadecimal clock frequency 30MHz, then output frequency would fCLK/8, 3.75MHz. Frequency Adder sums contents both Center Offset Frequency Registers produce phase increment. enabling INHOFR, output Offset Frequency Register disabled that output frequency determined from Center Frequency Register alone. BFSK modems, INHOFR asserted/ de-asserted toggle quadrature outputs between programmed frequencies. NOTE: Enabling/disabling INHOFR preserves contents Offset Frequency Register. Block Diagram shown Figure illustrates method reading phase accumulator NCO16 from microprocessor. setup shown very similar that used when part used generating complex sinusoid, except that internal SIN/COS lookup bypassed setting TEST logic 1(high). While TEST high, phase accumulator continues drive inputs SIN/COS Generator while most significant bits phase accumulator multiplexed onto output pins. Because this, part operated modes, where SIN/COS Generator permanently bypassed, where phase accumulator output brought outputs check. Figure illustrates circuit reading phase accumulator time. this case, microprocessor loads frequency phase registers NCO16. This fairly straightforward, except Start Logic Block, which needs synchronous oscillator clock microprocessor interface. This been left undefined function, since dependent implementation. Also note that outputs (COS(15:0)) connected, although only COS(15:4) valid this application. microprocessor reads sine cosine data busses
Once Input Registers have been loaded, control inputs ENCFREG, ENOFREG, ENTIREG, ENCTIREG, ENPOREG will allow Input Registers downloaded PFCS Control Registers with input CLK. control inputs latched rising edge Control Registers updated rising edge following CLK. example, load Center Frequency Register, data loaded into Center Frequency Input Register, ENCFREG zero; next rising edge will pass registered version ENCFREG, R.ENCFREG, clock enable Center Frequency Register; this register then gets loaded following rising edge CLK. contents Input Registers downloaded Control Registers every clock, control inputs enabled.
Phase Accumulator Section
Phase Accumulator adds 32-bit output Frequency Adder with contents 32-bit Phase Accumulator Register every clock cycle. When causes adder overflow, accumulation continues with least significant bits result. Initializing Phase Accumulator Register done putting INITPAC ENPHAC lines. This zeroes feedback path accumulator, that register loaded with current value Frequency Adder next clock.
FN2809.8 October 2008
HSP45106
they were RAMs, using decoded address select other. timing loading Center Frequency Register (MSB LSB) data being output COS(15:0) SIN(15:0) shown Figure This timing independent whether output data represents phase accumulator data SIN/COS Generator output. When desired output NCO16 switched back forth between sine/cosine phase accumulator, circuit such shown Figure could used. this case, sinusoidal output cannot interrupted, phase accumulator must read between samples. This possible fact that TEST signal simply control line multiplexer output SIN/COS Generator, carries with limitation maximum possible clock rate. Since TEST synchronous input, output NCO16 must either driven SIN/COS Generator phase accumulator entire clock cycle. Therefore, part must driven twice desired speed times there clock cycle available TEST, when necessary. Note that processor must driven from same clock that generates clock order maintain synchronous operation.
MICROPROCESSOR DATA ADDRESS HSP45106 MOD0(2:0) (15:0) SIN0-15 PMSEL C(15:0) COS(15:0) A(2:0) ENPOREG ENCFREG ENOFREG ENPHAC ENTIGEG INHOFR INITPAC PACI INITTAC TEST PAR/SER BINFMT DATA ADDRESS WRITE WRITE INPUT INPUT REGISTER REGISTER
A0-2
C0-15 TRANSFER DATA CENTER OFFSET FREQUENCY REGISTER FREQUENCY DATA
ENCFREG, ENOFREG
COS0-15, SIN0-15
FIGURE NCO16 PIPELINE DELAY
MICROPROCESSOR HSP45106 MOD0-2 PMSEL SIN0-15 C0-15 COS0-15 A0-2 ENPOREG ENCFREG ENOFREG ENPHAC ENTIGEG INHOFR INITPAC PACI INITTAC TEST PAR/SER BINFMT
REGISTER
DECODE
DECODE
START LOGIC
START LOGIC
OSCILLATOR OSCILLATOR
FIGURE CIRCUIT READING PHASE ACCUMULATOR NCO16
FIGURE CIRCUIT READING PHASE ACCUMULATOR NCO16 WHILE GENERATING SINUSOID
FN2809.8 October 2008
HSP45106
Phase Offset Adder
output Phase Accumulator goes Phase Offset Adder, which adds 16-bit contents Phase Offset Register MSBs phase. Twenty-eight (28) bits resulting 32-bit number forms instantaneous phase which Sine/Cosine Section. user option loading Phase Offset Registers with contents Phase Input Register with MOD(2:0) inputs depending state PMSEL. When PMSEL high, contents Phase Input Register loaded. PMSEL low, MOD(2:0) encode upper bits Phase Offset Register while lower bits cleared. MOD(2:0) inputs simplify modulation providing input interface phase modulate carrier shown Table control input ENPOREG acts clock enable must enable clocking data into Phase Offset Register.
TABLE MODULATION CONTROL MOD(2:0) DECODING MOD2 MOD1 MOD0 PHASE SHIFT (DEGREES)
outputs. takes most significant bits PFCS output passes them through Sine/Cosine look form 16-bit quadrature outputs. sine cosine values computed reduce amount needed. magnitude error computed value complex vector less than -90.2dB. error sine cosine alone approximately better. 20-bit phase word maps into radians that angular resolution (2p)/220. address zero corresponds radians address FFFFF corresponds 2-((2)/220) radians. outputs Sine Cosine Section two's complement sine cosine values. contents have been scaled (216-1)/(216+1) symmetry about zero. simplify interfacing with converters, format Sine/cosine outputs changed offset binary enabling BINFMT. When BINFMT enabled, Sine Cosine outputs (SIN15 COS15 when outputs parallel mode) inverted. Depending upon state BINFMT, output centered around midscale ranges from 8001H 7FFFH (two's complement mode) 0001H FFFFH (offset binary mode). Serial output mode chosen enabling PAR/SER. this mode user loads Output Shift Registers with Sine/Cosine output enabling ENPHAC. After ENPHAC goes inactive data shifted serially. example, clock 16-bit Sine/Cosine output, ENPHAC would active cycle load output Shift Register, would then inactive following cycles clock remaining bits out. Output streams provided formats with either first first. first format available SIN15 COS15 output pins. first format available SIN0 COS0 output pins. first format, zero's follow output word loaded into Shift Register. first format, sine extension follows data word loaded. output signal DACSTRB provided signal first output word valid (Figure NOTE: unused pins SIN(15:0) COS(15:0) should left floating. test mode supplied which enables user access phase input Sine/Cosine ROM. TEST both high, MSBs phase input Sine/Cosine Section made available SIN(15:0) COS(15:4). SIN(15:0) outputs represent address. Timing Diagrams Figures show pipeline delays through HSP45106 NCO16 from time that data applied inputs until outputs affected change. delay shown number clock cycles, with attempt made accurately represent setup hold times clock output delays.
Timer Accumulator Section
Timer Accumulator consists register which incremented every clock. amount which increments loaded into Timer Increment Input Registers latched into Timer Increment Register rising edges while ENTIREG low. output Timer Accumulator accumulator carry out, TICO. TICO used timer enable periodic sampling output NCO-16. number programmed into this register equals:
(EQ.
where INT[x] integer portion result computation.
Sine/Cosine Section
Sine/Cosine Section (Figure converts instantaneous phase from PFCS Section into appropriate amplitude values sine cosine
FN2809.8 October 2008
HSP45106
ADDRESS DECODE SINE/COSINE COSINE SINE BINFMT R.ENPHAC, TEST, PAR/SER FORMAT CONTROL OUTPUT CONTROL DACSTRB (15:0) (15:0)
SIN/COS ARGUMENT
FIGURE SINE/COSINE SECTION BLOCK DIAGRAM
tECS
ENPHAC tDSO DACSTRB
SERIAL DATA OUTPUT
FIGURE SERIAL OUTPUT TIMING DIAGRAM
WRITE INPUT REGISTER WRITE INPUT REGISTER
A(2:0) C(15:0) TRANSFER DATA CENTER OFFSET FREQUENCY REGISTER FREQUENCY DATA COS(15:0), SIN(15:0)
ENCFREG ENOFREG
FIGURE FREQUENCY OUTPUT DELAY
FN2809.8 October 2008
HSP45106
WRITE PHASE INPUT REGISTER
A(2:0)
C(15:0) TRANSFER DATA PHASE REGISTER ENPOREG PHASE DATA COS(15:0), SIN(15:0)
FIGURE PHASE OUTPUT DELAY
MOD0-2
PMSEL TRANSFER DATA PHASE REGISTER ENPOREG PHASE DATA COS(15:0), SIN(15:0)
FIGURE PHASE MODULATION OUTPUT DELAY
FN2809.8 October 2008
HSP45106
Absolute Maximum Ratings +25°C
Supply Voltage +6.0V Input, Output Voltage Applied -0.5V +0.5V Classification Class
Thermal Information
Thermal Resistance (Typical, Note (°C/W) PLCC Package. Maximum Junction Temperature PLCC Package. +150°C Maximum Storage Temperature Range .-65°C +150°C Pb-Free Reflow Profile. .see link below
Operating Conditions
Voltage Range +4.75V +5.25V Temperature Range +70°C
Characteristics
Backside Potential
CAUTION: operate near maximum ratings listed extended periods time. Exposure such conditions adversely impact product reliability result failures covered warranty.
NOTE: measured free with component mounted high effective thermal conductivity test board with "direct attach" features. Tech Brief TB379.
Electrical Specifications
PARAMETER Logical Input Voltage Logical Zero Input Voltage High Level Clock Input Level Clock Input Output HIGH Voltage Output Voltage Input Leakage Current Leakage Current Standby Power Supply Current Operating Power Supply Current
Parameters with and/or limits 100% tested +25°C, unless otherwise specified. Temperature limits established characterization production tested. SYMBOL VIHC VILC ICCSB ICCOP 5.25V 4.75V 5.25V 4.75V -400µA, 4.75V +2.0mA, 4.75V GND, 5.25V VOUT GND, 5.25V GND, 5.25V, (Note 25.6MHz, 5.25V, (Notes TEST CONDITIONS UNITS
Capacitance +25°C, (Note
PARAMETER Input Capacitance Output Capacitance NOTES: Power supply current proportional operating frequency. Typical rating ICCOP 7mA/MHz. tested, characterized initial design major process/design changes. Output load test load circuit with switch open 40pF. SYMBOL TEST CONDITIONS FREQ 1MHz, Open. measurements referenced device ground UNITS
FN2809.8 October 2008
HSP45106
Electrical Specifications
5.0V ±5%, +70°C (Note Parameters with and/or limits 100% tested +25°C, unless otherwise specified. Temperature limits established characterization production tested. 25.6MHz PARAMETER Period High Period High Setup Time A(2:0), Going High Hold Time A(2:0), from Going High Setup Time C(15:0) Going High Hold Time C(15:0) from Going High Setup Time High High Setup Time MOD(2:0) Going High Hold Time MOD(2:0) from Going High Setup Time ENPOREG, ENOFREG, ENCFREG, ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC, BINFMT, TEST, SER, PACI, INITTAC Going High Hold Time ENPOREG, ENOFREG, ENCFREG, ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC, BINFMT, TEST, SER, PACI, INITTAC from Going High Output Delay SIN(15:0), COS(15:0), TICO Output Delay DACSTRB Output Enable Time Output Disable Time Output Rise, Fall Time NOTES: testing performed follows: Input levels (CLK Input) 4.0V input levels (all other inputs) 3.0V; timing reference levels (CLK) 2.0V; others 1.5V. Output load test load circuit with switch closed 40pF. Output transition measured 1.5V 1.5V. ENOFREG, ENCFREG, ENTIREG, ENPOREG active, care must taken violate setup hold times these registers when writing data into chip C(15:0) port. Controlled design process parameters directly tested. Characterized upon initial design after major process and/or changes. SYMBOL tAWS tAWH tCWS tCWH tMCS tMCH tECS (Note NOTES 33MHz UNITS
tECH
tDSO (Note (Note
FN2809.8 October 2008
HSP45106 Test Load Circuit
(NOTE)
SWITCH OPEN ICCSB ICCOP 1.5V
NOTE: Test head capacitance.
EQUIVALENT CIRCUIT
Waveforms
tMCS MOD(2:1) tMCH
tECS ENABLE/CONTROL SIGNALS
tECH
SIN(15:0), COS(15:0), TICO tDSO DACSTRB (SERIAL MODE ONLY)
FIGURE SYNCHRONOUS TIMING
tAWS tAWH A(2:0), tCWS tCWH C(15:0)
FIGURE ASYNCHRONOUS TIMING
FN2809.8 October 2008
HSP45106 Waveforms
(Continued)
1.5V OES, COS(15:0), SIN(15:0)
1.5V
HIGH IMPEDANCE
1.7V 1.3V
HIGH IMPEDANCE
FIGURE OUTPUT ENABLE, DISABLE TIMING
2.0V 0.8V
2.0V 0.8V
FIGURE OUTPUT RISE FALL TIMES
FN2809.8 October 2008
HSP45106 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) IDENTIFIER 0.042 (1.07) 0.056 (1.42) 0.050 (1.27)
N84.1.15 (JEDEC MS-018AF ISSUE
0.004 (0.10)
LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL 0.165 0.090 1.185 1.150 0.541 1.185 1.150 0.541 0.180 0.120 1.195 1.158 0.569 1.195 1.158 0.569 MILLIMETERS 4.20 2.29 30.10 29.21 13.75 30.10 29.21 13.75 4.57 3.04 30.35 29.41 14.45 30.35 29.41 14.45 NOTES Rev. 11/97
0.025 (0.64) 0.045 (1.14)
D2/E2 D2/E2 VIEW
0.020 (0.51) PLCS
0.020 (0.51) SEATING PLANE
0.026 (0.66) 0.032 (0.81)
0.013 (0.33) 0.021 (0.53)
0.045 (1.14)
0.025 (0.64) VIEW TYP.
NOTES: Controlling dimension: INCH. Converted millimeter dimensions necessarily exact. Dimensions tolerancing ANSI Y14.5M-1982. Dimensions include mold protrusions. Allowable mold protrusion 0.010 inch (0.25mm) side. Dimensions include mold mismatch measured extreme material condition body parting line. measured seating plane contact point. Centerline determined where center leads exit plastic body. number terminal positions.
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
FN2809.8 October 2008
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