Data Sheet October 2008 FN2486.10 Decimating Digital Filter
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HSP43220
Data Sheet October 2008 FN2486.10
Decimating Digital Filter
HSP43220 Decimating Digital Filter linear phase pass decimation filter which optimized filtering narrow band signals broad spectrum signal processing applications. HSP43220 offers single chip solution signal processing applications which have historically required several boards ICs. This reduction component count results faster development times well reduction hardware costs. HSP43220 implemented stage filter structure. seen block diagram, first stage high order decimation filter (HDF) which utilizes efficient sample rate reduction technique obtain decimation 1024 through coarse low-pass filtering process. provides 96dB aliasing rejection signal pass band. second stage consists finite impulse response (FIR) decimation filter structured transversal filter with symmetric taps which implement filters with sharp transition regions. perform further decimation required while preserving 96dB aliasing attenuation obtained HDF. combined total decimation capability 16,384. HSP43220 accepts 16-bit parallel data complement format sampling rates 33MSPS. provides 16-bit microprocessor compatible interface simplify task programming three-state outputs allow connection several common bus. HSP43220 also provides capability bypass either additional flexibility.
Features
Single Chip Narrow Band Filter with 96dB Attenuation 33MHz Clock Rate 16-Bit Complement Input 20-Bit Coefficients 24-Bit Extended Precision Output Programmable Decimation Maximum 16,384 Standard 16-Bit Microprocessor Interface Filter Design Software Available Taps Pb-Free Available (RoHS compliant)
Applications
Very Narrow Band Filters Zoom Spectral Analysis Channelized Receivers Large Sample Rate Converter
Ordering Information
PART NUMBER HSP43220JC-25 PART MARKING HSP43220JC-25 TEMP. RANGE (°C) PACKAGE PKG. DWG.
PLCC N84.1.15 PLCC N84.1.15 (Pb-free) PLCC N84.1.15 PLCC N84.1.15 (Pb-free)
HSP43220JC-25Z HSP43220JC-25Z HSP43220JC-33 HSP43220JC-33
HSP43220JC-33Z HSP43220JC-33Z
NOTE: These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, 100% matte plate plus anneal termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations). Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020. NOTE: DECIMATE Software Development Tool (This software tool downloaded from internet site: www.intersil.com
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2004, 2008. Rights Reserved DECIMATEis trademark Intersil Corporation. other trademarks mentioned property their respective owners.
HSP43220 Block Diagram
DECIMATION 1024 INPUT CLOCK DATA INPUT CONTROL COEFFICIENTS HIGH ORDER DECIMATION FILTER DECIMATION DECIMATION FILTER CLOCK DATA DATA READY
Pinout
HSP43220 PLASTIC LEADED CHIP CARRIER (PLCC) VIEW
DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN CK_IN STARTOUT STARTIN ASTARTIN RESET C_BUS C_BUS C_BUS C_BUS C_BUS C_BUS C_BUS C_BUS C_BUS C_BUS C_BUS C_BUS C_BUS C_BUS C_BUS C_BUS OUT_SELH OUT_ENP OUT_ENX FIR_CK DATA_RDY DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT DATA_OUT
Description
NAME CK_IN TYPE power supply pins. device ground. Input Sample Clock. Operations synchronous with rising edge this clock signal. maximum clock frequency 33MHz. CK_IN synchronous with FIR_CK thus clocks tied together required, CK_IN divided down from FIR_CK. CK_IN CMOS level signal. Input Clock Filter. This clock must synchronous with CK_IN. Operations synchronous with rising edge this clock signal. maximum clock frequency 33MHz. FIR_CK CMOS level signal. DESCRIPTION
FIR_CK
FN2486.10 October 2008
HSP43220 Description
NAME DATA_IN0-15 TYPE (Continued) DESCRIPTION Input Data Bus. This used provide 16-bit input data HSP43220. data must provided synchronous fashion, latched rising edge CK_IN signal. data complement fractional format. MSB. Control Input Bus. This input used load filter parameters. pins used select destination data Control write Control data into appropriate register selected Output Data Bus. This 24-Bit output port used provide filtered result complement format. upper bits output, DATA_OUT16-23 will provide extension growth bits depending state OUT_SELH whether been bypass mode. Output bits DATA_OUT0-15 will provide bits through 2-15 when bypassed will provide bits 2-16 through 2-31 when bypass mode. active high output strobe that synchronous with FIR_CK that indicates that result just completed cycle available data bus. RESET asynchronous signal which requires that input clocks CK_IN FIR_CK active when RESET asserted. RESET disables clock divider clears internal data registers HDF. filter data path initialized. control register bits that cleared F_BYP, H_STAGES, H_DRATE. F_DIS set. order guarantee consistent operation part, user must reset after power-up. Write Strobe. used loading internal registers HSP43220. When asserted, rising edge will latch C_BUS0-15 data into register specified Chip Select. Chip Select input enables loading internal registers. When low, address lines decoded determine destination data C_BUS0-15. rising edge then loads appropriate register specified Control Register Address. These lines decoded determine which control register destination data C_BUS0-15. Register loading controlled inputs. ASTARTIN asynchronous signal which sampled rising edge CK_IN. used operational mode. ASTARTIN internally synchronized CK_IN used generate STARTOUT. STARTOUT pulse generated from internally synchronized version ASTARTIN. provided output multi-chip configurations synchronously start multiple HSP43220's. width STARTOUT equal period CK_IN. STARTIN Synchronous Input. high transition this signal required start part. STARTIN sampled rising edge CK_IN. This synchronous signal used start single multiple HSP43220's. Output Select. OUT_SELH input controls which bits provided output pins DATA_OUT16-23. HIGH this control line selects bits through from accumulator output. this control line selects bits 2-16 through 2-23 from accumulator output. Processing interrupted this pin. Output Enable. OUT_ENP input controls state lower bits output data bus, DATA_OUT0-15. this control line enables lower bits output bus. When OUT_ENP HIGH, output drivers high impedance state. Processing interrupted this pin. Output Enable. OUT_ENX input controls state upper bits output data bus, DATA_OUT16-23. this control line enables upper bits output bus. When OUT_ENX HIGH, output drivers high impedance state. Processing interrupted this pin.
C_BUS0-15
DATA_OUT 0-23
DATA_RDY RESET
ASTARTIN STARTOUT
STARTIN OUT_SELH
OUT_ENP
OUT_ENX
first filter section called High Order Decimation Filter (HDF) optimized perform decimation large factors. implements pass filter using only adders delay elements instead large number multiplier/ accumulators that would required using standard filter. divided into sections: filter section, clock divider, control register logic start logic (Figure
Data Shifter
After being latched into Input Register data enters Data Shifter. data positioned output shifter prevent errors overflow occurring output HDF. number bits shift controlled H_GROWTH.
FN2486.10 October 2008
HSP43220 Integrator Section
data from shifter goes Integrator section. This cascade integrator accumulator) stages, which implement pass filter. Each accumulator implemented adder followed register feed forward path. integrator clocked sample clock, CK_IN shown Figure width each integrator stage goes from bits first integrator down bits output fifth integrator. truncation performed each integrator stage because data integrator stages being accumulated thus growing, therefore lower bits become insignificant, truncated without losing significant data. There three signals that control integrator section; they H_STAGES, H_BYP RESET. Figure these control signals have been decoded labelled INT_EN1 INT_EN5. order filter loaded
A0-1 C_BUS H_DRATE CONTROL REGISTER LOGIC H_BYP CLOCK DIVIDER ISTART START LOGIC STARTOUT CK_IN RESET
control called H_STAGES. H_STAGES decoded provide enables each integrator stage. When given integrator stage selected, feedback path enabled integrator accumulates current data sample with previous sum. integrator section bypass mode H_BYP bit. When H_BYP RESET asserted, feedback paths integrator stages cleared.
Decimation Register
output Integrator section latched into Decimation Register CK_DEC. output Decimation register cleared when RESET asserted. decimation rate H_DRATE which defined HDEC convenience.
RESET
CK_IN ASTARTIN STARTIN
H_GROWTH
INT_EN1-5
COMB_EN1-5
FILTER SECTION
ISTART H_GROWTH DATA INPUT DATA SHIFTER INT_EN1-5 INTEGRATOR RESET COMB_EN1-5 COMB FILTER ROUND RESET
CK_IN CK_DEC
FIGURE HIGH ORDER DECIMATION FILTER FIGURE
FROM SHIFTER
INT_EN5
INT_EN4
INT_EN3
INT_EN2
INT_EN1
DECIMATION REGISTER
FIGURE INTEGRATOR
FN2486.10 October 2008
HSP43220
COMB_EN5 FROM DECIMATION REGISTER RESET CK_DEC COMB_EN4 COMB_EN3 COMB_EN2 COMB_EN1
RESET
RESET
RESET
RESET
ROUNDER
FIGURE COMB FILTER
Comb Filter Section
output Decimation Register passed Comb Filter Section. Comb section consists cascaded Comb filters differentiators. Each Comb filter section calculates difference between current previous integrator output. Each Comb filter consists register which clocked CK_DEC, followed subtractor, where subtractor calculates difference between input output register. truncations done each stage shown Figure first stage width bits output fifth stage bits. There three signals that control Comb Filter; H_STAGES, H_BYP RESET. Figure these control signals decoded COMB_EN1 COMB_EN5. order Comb filter controlled H_STAGES, which programmed over control bus. H_BYP used comb section bypass mode. RESET causes register output each Comb stage cleared. RESET control pins, when asserted force output registers zero data passed through subtractor unaltered. When H_STAGES control bits enable given stage output register subtracted from input. important note that Comb filter section speed limitation. Input sampling rate divided decimation factor (CK_IN/HDEC) should exceed 4MHz. Violating this condition causes output filter incorrect. When bypass mode this limitation does apply. Equation describes relationship between F_TAPS, F_DRATE, H_DRATE, CK_IN FIR_CK.
filter stage section 16-bit integer portion with 3-bit fractional part complement format. rounding algorithm follows:
POSITIVE NUMBERS Fractional Portion Fractional Portion NEGATIVE NUMBERS Fractional Portion Fractional Portion Round-Up Truncate Round-Up Truncate
output rounder latched into output register with CK_DEC. CK_DEC generated Clock Divider section. output register cleared when RESET asserted.
Clock Divider Control Logic
clock divider divides CK_IN decimation factor HDEC produce CK_DEC. CK_DEC clocks Decimation Register, Comb Filter section, output register. filter CK_DEC used indicate that data sample available processing. clock generator cleared RESET enabled until started internal start signal (see "Start Logic" page Control Register Logic enables updating Control registers which contain filter parameter data. When asserted, control register addressed bits loaded with data C_BUS.
Rounder
filter accuracy limited 16-bit data input. maintain maximum accuracy, output comb rounded bits. Rounder performs symmetric round 19-bit output last Comb stage. Symmetric rounding done prevent synthesis spectral component rounding process thus causing reduction spurious free dynamic range. Saturation logic also provided prevent roll over from largest positive value most negative value after rounding. output last comb
FN2486.10 October 2008
HSP43220 Control Registers
F_Register F_OAD F_BYP F_ESYM F_DRATE F_TAPS
F_TAPS Bits T0-T8 used specify number filter taps. number entered less than number taps required. example, specify filter F_TAPS would programmed 510. minimum number taps (F_TAPS F_DRATE Bits D0-D3 used specify amount decimation. number entered less than decimation required. example, specify decimation F_DRATE would programmed decimation, F_DRATE would equal FDRATE defined FDEC. F_ESYM used select symmetry. F_ESYM equal select even symmetry equal zero select symmetry. When F_ESYM one, data added pre-adder; when zero, data subtracted. Normally one. F_BYP used select bypass mode. bypass mode selected setting F_BYP When bypass mode selected, internally even symmetric filter, decimation (F_DRATE F_OAD equal zero side preadder. bypass mode filter parameters, except F_CLA, ignored, including contents coefficient RAM. bypass mode output data brought output lower bits output DATA_OUT 0-15. disable bypass mode, F_BYP equal zero. When F_BYP returned zero, coefficients must reloaded. F_OAD used select zero preadder mode. This mode zeros inputs pre-adder. Zero preadder mode selected setting F_OAD equal one. This feature useful when implementing arbitrary phase filters used verify filter coefficients. disable Zero Preadder mode F_OAD equal zero.
FIGURE
FN2486.10 October 2008
HSP43220 Control Registers
FC_Register F_CF (Continued)
F_CF Bits C0-C19 represent coefficient data, where MSB. writes required write each coefficient which complement fractional format. first write loads through through loaded second write cycle. coefficients written into this register they formatted into 20-bit coefficient written into Coefficient sequentially starting with address location zero. coefficients must loaded sequentially, with center being last coefficient loaded. "Coefficient RAM" page
FIGURE
FN2486.10 October 2008
HSP43220 Control Registers
H_Register RESERVED F_DIS F_CLA H_BYP H_DRATE (Continued)
H_DRATE Bits R0-R9 used select amount decimation HDF. amount decimation selected programmed required decimation minus one; instance select decimation 1024 H_DRATE equal 1023. HDRATE defined HDEC. H_BYP used select bypass mode. This mode selected setting H_BYP When this mode selected input data passes through unfiltered. Internally H_STAGES H_DRATE both zero H_GROWTH H_REGISTER must reloaded when H_BYP returned disable bypass mode H_BYP relationship between CK_IN FIR_CK this other modes defined Equation F_CLA used select clear accumulator mode FIR. This mode enabled setting F_CLA disabled setting F_CLA normal operation this should equal zero. This mode zeros feedback path accumulator multiplier/accumulator (MAC). also allows multiplier output clocked chip FIR_CK, thus DATA_RDY meaning this mode. This mode used conjunction with F_OAD read coefficients from coefficient RAM. F_DIS used select disable mode. This feature enables parameters changed. This feature selected setting F_DIS This mode terminates current cycle. While this feature selected, continues process data write into data RAM. When re-programming completed, re-enabled either clearing F_DIS, asserting start inputs, which automatically clears F_DIS.
FIGURE
FN2486.10 October 2008
HSP43220 Control Registers
H_Register RESERVED H_GROWTH H_STAGES (Continued)
H_STAGES Bits N0-N2 used select number stages order filter. number that programmed equal required number stages. order filter, H_STAGES would equal H_GROWTH Bits G0-G5 used select proper amount growth bits. H_GROWTH calculated using Equation
H_GROWTH CEILING H_STAGESx )/log(2) (EQ.
where CEILING means next largest integer result value brackets base value H_GROWTH represents position output data shifter.
FIGURE
Start Logic
Start Logic generates start signal that used internally synchronously start DDF. ASTARTIN asserted (STARTIN must tied high) Start Logic synchronizes CK_IN double latching signal generating signal STARTOUT, which shown Figure STARTOUT signal then used synchronously start other DDFs multi-chip configuration (the STARTOUT signal first would tied STARTIN second DDF). NAND gate shown Figure then passes this synchronized signal used on-chip provide synchronous start. Once started, chip requires RESET halt operation.
RESET STARTIN ASTARTIN ISTART
assert either ASTARTIN STARTIN order start DDF. timing first valid DATA_IN with respect START_IN shown Timing Waveforms. using ASTARTIN STARTIN high transition must detected rising edge CK_IN, therefore these signals must have been high more than CK_IN cycle then taken low.
Section
second filter level block diagram Finite Impulse Response (FIR) filter which performs final shaping signal spectrum suppresses aliasing components transition band HDF. This enables implement filters with narrow pass bands sharp transition bands. implemented transversal structure using single multiplier/accumulator (MAC) storage data filter coefficients shown Figure implement symmetric taps decimation divided into sections: filter section control logic.
CK_IN
STARTOUT
FIGURE START LOGIC
When STARTIN asserted (ASTARTIN must tied high) NAND gate passes STARTIN which used provide internal start, ISTART, DDF. When RESET asserted internal start signal held inactive, thus necessary
FN2486.10 October 2008
HSP43220
Coefficient
Coefficient stores coefficients current filter being implemented. coefficients loaded into Coefficient over control (C_BUS). coefficients written into Coefficient sequentially, starting location zero. only necessary write half coefficients when symmetric filters being implemented, where last coefficient written center tap. coefficients loaded into address writes. first write loads upper bits 20-bit coefficient, through C19. second write loads lower bits coefficient, through where MSB. 16-bit writes then formatted into 20-bit coefficient that then loaded into Coefficient starting address location zero, where coefficient this location outer first coefficient value). reload coefficients, Coefficient Address pointer must reset location zero that coefficients will loaded order filter expects. There methods that used reset Coefficient address pointer. first assert RESET, which automatically resets pointer, also clears alters some control register bits. (RESET does change coefficient values.) second method F_DIS control register REGISTER1. This control allows control register bits reprogrammed, does automatically modify control registers. When programming completed, re-started clearing F_DIS asserting start inputs (ASTARTIN STARTIN). F_DIS allows filter parameters changed more quickly thus recommended reprogramming method. maximum throughput filter limited single Multiplier/Accumulator (MAC). data output from being clocked into filter CK_DEC must rate that causes erroneous result being calculated because data being overwritten. Equation describes relationship between, FIR_CK, CK_DEC, number taps that implemented FIR, decimation rate decimation rate FIR. Design Considerations section "Operational Section" page there chart that shows tradeoffs between these parameters.)
CK_IN TAPS/2 FIR_CK (EQ.
This equation expresses minimum FIR_CK. minimum FIR_CK smallest integer multiple CK_IN that satisfies Equation addition, specification must (see Electrical Specifications). FDEC decimation rate (FDEC F_DRATE +1), where TAPS number taps even length filters equals number taps+1 length filters. Solving Equation maximum number taps:
FIR_CK TAPS CK_IN (EQ.
using this equation, must kept mind that CK_IN/ HDEC must less than equal 4MHz (unless bypass mode which case this limitation does apply). "Operational Section" page under Design Considerations, there table that shows trade-offs these parameters. addition, Intersil provides software package called DECI MATEwhich designs filter from System specifications. registered outputs data added subtracted 17-bit pre-adder. F_OAD control allows zeros input into side pre-adder. This provides capability implement non-symmetric filters. selection adding register outputs even symmetric filter subtracting register outputs symmetric filter provided control F_ESYM, which programmed over control bus. When subtraction selected, data subtracted from data. 17-bit output adder forms input multiplier/accumulator. control F_CLA provides capability clear feedback path accumulator such that multiplier output will accumulated, will instead flow directly output register. weightings data coefficients they processed shown follows. Input Data (from HDF) 20.2-1 2-15 Pre-adder Output 2120.2-1 2-15 Coefficient 20.2-1 2-19 Accumulator 2-34
Data
Data stores data needed filter calculation. format data where sign location. 16-bit output Output Register written into Data rising edge CK_DEC. RESET initializes write pointer data RAM. After RESET occurs, output will valid until number data samples written Data equals TAPS. filter always operates most current sample taps-1 previous samples. Thus F_DIS set, data continues written into data coming from section. When enabled again filter will operating most current data samples thus another transient response will occur.
FN2486.10 October 2008
HSP43220
Output
most significant bits accumulator latched into output register. lower bits brought output. bits output register selected output pair multiplexers. This register clocked FIR_CK (see Figure There multiplexers that route output bits from output register output pins. first multiplexer selects output register bits that will routed output pins DATA_OUT16-23 second multiplexer selects output register bits that will routed output pins DATA_OUT0-15. multiplexers controlled control signal F_BYP OUT_SELH pin. F_BYP OUT_SELH both control first multiplexer that selects upper bits output bus, DATA_OUT16-23. F_BYP controls second multiplexer that selects lower bits output bus, DATA_OUT0-15. output formatter shown detail Figure
Control Logic
DATA_RDY strobe indicates that data available output FIR. rising edge DATA_RDY used load output data into external register RAM.
Data Format
maintains bits accuracy both filter stages. data formats weightings shown Figure
PRE-ADDER LOGIC F_OAD F_ESYM COEFFICIENT
FROM
DATA
PRE-ADDER
FROM COEFFICIENT FORMATTER
MULTIPLIER ARRAY MULTIPLIER/ ACCUMULATOR SECTION F_DIS F_CLA 43-BIT ACCUMULATOR CONTROL LOGIC FIR_CK FIR_CK DATA_RDY F_CLA OUTPUT OUTPUT FORMATTER DATA_OUT
FROM CONTROL REGISTERS F_DRATE F_TAPS F_BYP
DATA_RDY
FIGURE FILTER
FN2486.10 October 2008
HSP43220
F_BYP OUT_SELH F_BYP OUT_SELH 2-16 2-23 F_BYP OUT_SELH F_BYP 2-15 F_BYP 2-16 2-31 F_BYP F_BYP
OUT_ENX
OUT_ENP
DATA_OUT16-23
DATA_OUT0
FIGURE OUTPUT FORMATTER
INPUT DATA FORMAT
Fractional Two's Complement Input 2-10 2-11 2-12 2-13 2-14 2-15
COEFFICIENT FORMAT
Fractional Two's Complement Input 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19
OUTPUT DATA FORMAT
Fractional Two's Complement Output FOR: OUT_SELH F_BYP
2-10 2-11 2-12 2-13 2-14 2-15
FOR: OUT_SELH F_BYP
2-10 2-11 2-12 2-13 2-14 2-15
2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23
FOR: OUT_SELH F_BYP
2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23
2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 FIGURE
Operational Section
Start Configurations
scenario into operational mode reset asserting RESET input, configure over control bus, apply start signal, either ASTARTIN STARTIN. Until operational mode with start pulse, ignores data inputs. asynchronous start, asynchronous active pulse applied ASTARTIN input. ASTARTIN internally synchronized sample clock, CK_IN, generates STARTOUT. This signal also used internally when asynchronous mode selected. puts operational mode allows begin accepting data. When ASTARTIN input being used, STARTIN input must tied high ensure proper operation. start synchronously, STARTIN asserted with active pulse that been externally synchronized CK_IN. Internally then uses this start pulse operate mode start accepting data inputs. When STARTIN used start ASTARTIN input must tied high prevent false starts.
FN2486.10 October 2008
HSP43220
Multi-Chip Start Configurations
Since there methods start-up DDF, there also configurations that used start-up multiple chips. first method shown Figure timing STARTOUT circuitry starts second same clock first. more DDFs also started synchronously, STARTOUT connected their STARTIN's. second method start-up DDFs multiple chip configuration synchronous start scenario. STARTIN input wired chips chain, asserted active synchronous pulse that been externally synchronized CK_IN. this DDFs synchronously started. ASTARTIN input chips tied high prevent false starts. STARTOUT outputs left unconnected. This configuration illustrated Figure
OTHER DDF'S STARTIN ASTARTIN CK_IN FIR_CK STARTOUT CK_IN FIR_CK ASTARTIN STARTIN STARTOUT
FIGURE ASYNCHRONOUS START-UP
STARTIN CK_IN FIR_CK ASTARTIN STARTOUT
ASTARTIN STARTIN
STARTOUT
CK_IN FIR_CK
FIGURE SYNCHRONOUS START-UP
Chip Application
HSP43220 ideally suited narrow band filtering Communications, Instrumentation Signal Processing applications. HSP43220 provides fully integrated solution high order decimation filtering. combination HSP43220 HSP45116 (which NCOM Numerically Controlled Oscillator Modulator) provides complete solution digital receivers. diagram Figure illustrates this concept. HSP45116 down converts signal interest baseband, generating real component imaginary component. HSP43220 then performs pass filtering reduces sampling rate each signals. system scenario involves narrow band signal that been over-sampled. signal over-sampled order capture wide frequency band containing many narrow band signals. NCOM "tuned" frequency signal interest performs complex down conversion baseband this signal, which results complex signal centered baseband. pair DDFs then pass filters NCOM output, extracting signal interest.
Design Trade-Off Considerations
Equation Functional Description section expresses relationship between number TAPS which implemented function CK_IN, FIR_CK, HDEC, FDEC. Table provides tradeoff these parameters. given speed grade ratio clocks, assuming minimum decimation HDF, number taps that implemented given Equation
FN2486.10 October 2008
HSP43220
HSP45116 NCOM (WT) HSP43220
SAMPLED INPUT DATA
(WT)
HSP43220
10MHz
20MHz
FIGURE DIGITAL CHANNELIZER TABLE DESIGN TRADE MINIMUM HDEC SPEED GRADE (MHz) 25.6 25.6 25.6 25.6 FIR_CK CK_IN HDEC FDEC (Note) (Note) (Note) FDEC TAPS FDEC FDEC FDEC
NOTE: Filter realizable.
FN2486.10 October 2008
HSP43220
DECIMATE
Intersil provides development system which assists design engineer utilizing this filter. DECIMATE software package provides user with both filter design simulation environments filter evaluation design. These tools integrated within standard environment, Athena Group's Monarch Professional Software package. software package designed specifically DDF. provides filter design software this proprietary architecture. provides user-friendly menu driven interface allow user input system level filter requirements. provides frequency response curves data flow simulation specified filter design (Figure 15). also creates information necessary program DDF, including PROM file programming control registers. This software package runs IBMPCTM, XTTM, ATTM, PS/2computer 100% compatible with following configuration: 640k 5.25" 3.5" Floppy drive hard disk math co-processor MS/PC-DOS higher CGA, MCGA, EGA, Hercules graphics adapters more information, description DECIMATE "DECIMATE" page
FN2486.10 October 2008
HSP43220
FIGURE DECIMATE DESIGN MODULE SCREENS
FN2486.10 October 2008
HSP43220
Absolute Maximum Ratings +25°C
Supply Voltage +6.0V Input, Output Voltage Applied -0.5V +0.5V Classification Class
Thermal Information
Thermal Resistance (Typical, Note (°C/W) PLCC Package. Maximum Storage Temperature Range .-65°C +150°C Maximum Junction Temperature PLCC Package. +150°C Pb-Free Reflow Profile. .see link below
Operating Conditions
Temperature Range +70°C Voltage Range +4.75V +5.25V
Characteristics
Component Count 193,000 Transistors
CAUTION: operate near maximum ratings listed extended periods time. Exposure such conditions adversely impact product reliability result failures covered warranty.
NOTE: measured free with component mounted high effective thermal conductivity test board with "direct attach" features. Tech Brief TB379.
Electrical Specifications
PARAMETER Logical Input Voltage Logical Zero Input Voltage High Level Clock Input Level Clock Input Output HIGH Voltage Output Voltage Input Leakage Current Leakage Current Standby Power Supply Current Operating Power Supply Current
Parameters with and/or limits 100% tested +25°C, unless otherwise specified. Temperature limits established characterization production tested. SYMBOL VIHC VILC ICCSB ICCOP 5.25V 4.75V 5.25V 4.75V -400µA, 4.75V +2.0mA, 4.75V GND, 5.25V VOUT GND, 5.25V 5.25V, (Note 15MHz, GND, 5.25V, (Notes TEST CONDITIONS UNITS
Capacitance +25°C, (Note
PARAMETER Input Capacitance Output Capacitance NOTES: Power supply current proportional operating frequency. Typical rating ICCOP 8mA/MHz. tested, characterized initial design major process/design changes. Output load test load circuit with switch open 40pF. SYMBOL TEST CONDITIONS FREQ 1MHz, Open, measurements referenced device ground UNITS
FN2486.10 October 2008
HSP43220
Electrical Specifications
+4.75V +5.25V, +70°C (Note Parameters with and/or limits 100% tested +25°C, unless otherwise specified. Temperature limits established characterization production tested. PARAMETER Input Clock Frequency Clock Frequency Input Clock Period Clock Period Clock Pulse Width Clock Pulse Width High Clock Skew Between FIR_CK CK_IN CK_IN Pulse Width CK_IN Pulse Width High CK_IN Setup FIR_CK CK_IN Hold from FIR_CK RESET Pulse Width Recovery Time RESET ASTARTIN Pulse Width STARTOUT Delay from CK_IN STARTIN Setup CK_IN Setup Time DATA_IN Hold Time inputs Write Pulse Width Write Pulse Width High Setup Time Address Before Rising Edge Write Setup Time On-chip Select Before Rising Edge Write Setup Time Control Before Rising Edge Write DATA_RDY Pulse Width DATA_OUT Delay Relative FIR_CK DATA Valid Delay Relative FIR_CK DATA_OUT Delay Relative OUT_SELH Output Enable Data Valid Output Disable Data Three-State Output Rise, Output Fall Times NOTES: Controlled design process parameters directly tested. Characterized upon initial design after major process and/or design changes. Transition measured ±200mV from steady state voltage with loading specified test load circuit with 40pF. Testing performed follows: Input levels (CLK Input) 4.0V Input levels (all other Inputs) 3.0V, Timing reference levels (CLK) 2.0V, (Others) 1.5V, Output load test load circuit 40pF. Applies only when H_BYP H_DRATE SYMBOL FFIR tFIR tSPWL tSPWH tCH1L tCH1H tCIS tCIH tRSPW tRTRS tAST tSTOD tSTIC tSET tHOLD tSTADD tSTCS tSTCB tDRPWL tFIRDV tFIRDR tOUT tOEV tOEZ (Note (Note from 0.8V (Note (Notes (Notes (Notes (Notes NOTES 4tCK 8tCK 2tFIR tFIR 4tCK 8tCK 2tFIR 25.6 25.6 tFIR 4tCK 8tCK 2tFIR tFIR UNITS
FN2486.10 October 2008
HSP43220 Test Load Circuit
(NOTE)
SWITCH OPEN ICCSB ICCOP 1.5V
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
Timing Waveforms
tFIR FIR_CK tSET CLK_IN DATA_IN CLK_IN tHOLD tSPWH tSPWL tCHIH tCHIL
FIGURE 16A. FIGURE INPUT TIMING
FIGURE 16B.
ASTARTIN
tAST RESET
tRSPW tRTRS
CK_IN STARTOUT tSTOD
AO-1 tSET CK_IN tSTIC STARTIN tHOLD C_BUS tSTADD
tHOLD
tHOLD
DATA_IN
tSTCB tSTCS
tHOLD
FIGURE 17A. FIGURE START TIMING
FIGURE 17B.
FN2486.10 October 2008
HSP43220 Timing Waveforms
FIR_CK tFIRDR DATA_RDY tDRPWL tFIRDV CURRENT OUTPUT tFIRDR
(Continued)
DATA_OUT 16-23 UPPER BITS OUT_SELH tOUT LOWER BITS
DATA_OUT
PREVIOUS OUTPUT
FIGURE 18A.
FIGURE 18B.
OUT_ENP OUT_ENX tOEV DATA_OUT 0-d23 2.0V 0.8V DATA_OUT 1.7V 1.3V VALID tOEZ
FIGURE 18C. FIGURE
FIGURE 18D.
FN2486.10 October 2008
HSP43220 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) IDENTIFIER 0.042 (1.07) 0.056 (1.42) 0.050 (1.27)
N84.1.15 (JEDEC MS-018AF ISSUE
0.004 (0.10)
LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL 0.165 0.090 1.185 1.150 0.541 1.185 1.150 0.541 0.180 0.120 1.195 1.158 0.569 1.195 1.158 0.569 MILLIMETERS 4.20 2.29 30.10 29.21 13.75 30.10 29.21 13.75 4.57 3.04 30.35 29.41 14.45 30.35 29.41 14.45 NOTES Rev. 11/97
0.025 (0.64) 0.045 (1.14)
D2/E2 D2/E2 VIEW
0.020 (0.51) PLCS
0.020 (0.51) SEATING PLANE
0.026 (0.66) 0.032 (0.81)
0.013 (0.33) 0.021 (0.53)
0.045 (1.14)
0.025 (0.64) VIEW TYP.
NOTES: Controlling dimension: INCH. Converted millimeter dimensions necessarily exact. Dimensions tolerancing ANSI Y14.5M-1982. Dimensions include mold protrusions. Allowable mold protrusion 0.010 inch (0.25mm) side. Dimensions include mold mismatch measured extreme material condition body parting line. measured seating plane contact point. Centerline determined where center leads exit plastic body. number terminal positions.
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
FN2486.10 October 2008
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