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HC55185 Ringing SLIC & AK2306 / 2306LV CODEC Evaluation Board User Guide Supplement

Application Note January 2002 AN9992

HC55185 Ringing SLIC & AK2306 / 2306LV CODEC Evaluation Board User Guide Supplement
Application Note January 2002 AN9992
Author: Don LaFontaine
Functional Description
This application note will first evaluate the DC performance of the system by configuring the jumpers and hardware for the External Clock / PC Control mode. Figure 1 shows the required connection between the Evaluation Board, PC and PCM4 tester. If the user prefers to evaluate the AC performance first, then skip to Test #5.
Verifying Basic Operation
The operation of the Evaluation Board can be verified by performing the following tests: 1. Normal Loop Feed Verification · · · · Tip & Ring Voltage Forward Active State, On Hook Tip & Ring Voltage Forward Active State, Off Hook Tip & Ring Voltage Reverse Active State, On Hook Tip & Ring Voltage Reverse Active State, Off Hook
2. Loop Supervisory Detection · On Hook & Off Hook Test · Tip Open State, Ground Key Test · Forward Loopback Test 3. Ringing Verification 4. Emulation of Phone Conversation 5. Gain Verification-Total System Gain (Digital to Digital) 6. Variable Gain / Frequency · Receive Gain (Digital to Analog) · Transmit Gain (Analog to Digital) 7. Total Distortion-Receive Gain (Digital to Analog)
CODEC
HC55185 RING
JP6 JP5 JP4
AK2306 / 2306LV
DR JP1
FPGA External Frame TX Clock 22 63 61
TX / RX Interface
TIP RING
HC55185
JP6 JP5 JP4
SLIC LOGIC CONTROL
FIGURE 1. AK2306 / 2306LV EVALUATION BOARD CONNECTION TO PCM4 AND COMPUTER
Application Note 9992
SLIC PART CODEC PART
VCCIO
VCCINT
Channel A
CODEC
TSYNC
RSYNC
FS FPGA BCLK
Channel B
BNC for Analog I / F FPGA control SW
Serial I / F access SW
FIGURE 2. AK2306 / 2306LV MOTHER BOARD CONNECTIONS
HC55185 SLIC
The HC55185 is optimized to match a 600 line impedance, have a ring trip threshold of 90mA, a switch hook threshold of 12mA, loop current limit of 24.6mA and a transient current limit of 100mA. Programming of the logic state of the HC55185 is performed by the toggle switches SW1 through SW6. Table 1 lists the switch name (referenced to the SLIC data sheet), switch number (reference to the PCB board layout), and the switch function. The logic states of the HC55185 are shown in Table 2.
AK2306 / 2306LV Evaluation Board
Application Note 9992
AK2306 (5V) Circuit Configuration:
AK2306LV (3.3V) Circuit Configuration:
Configuring the board for operation:
1. Connect the IBM PC / AT (25 pin) cable between the evaluation board and your computer (Figure 1). Microsoft® Windows® 95 or higher should be installed (Microsoft® Windows NT® is not supported). 2. Connect the PCM4 to the evaluation board as shown in Figure 1. 3. Connect the power supplies to the supply jacks on the evaluation board. 4. Configure SW1, SW2, SW3, SW4, SW5 as shown in Table 4.
TABLE 4. FPGA CONTROL SWITCHES SWITCH SW1 Selects PC mode SW2 PCM I / F data format set to Long Frame (LF) SW3 Sets the SYNC timing
Getting Started
POSITION
SW4 Selects internal BCLK frequency(2.048M)
SW5 Selects normal operation, selects FS and BCLK from external source (BNC)
Application Note 9992
5. Verify JUMPER positions as shown in Table 5 or 6.
NOTE: the default receive gain is 0dB.
TABLE 7. PROGRAMING HC55185 OPERATING MODES HC55185 MODE Low Power Standby Forward Active Unbalanced Ringing Reverse Active Ringing Forward Loopback Tip Open Power Denial S1 (F2) 0 0 0 0 1 1 1 1 S2 (F1) 0 0 1 1 0 0 1 1 S3 (F0) 0 1 0 1 0 1 0 1 S4 (E0) 1 1 1 1 1 1 1 1 S5 S6 (SWC) (BSEL) ----0 0 1 0 1 0 0 0
Microsoft®, Windows® and Windows NT® are registered trademarks of Microsoft Corporation
Application Note 9992
TABLE 8. REGISTER MAP A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 D7 TST13 TST11 TST9 TST7 TST5 TST3 D6 TST12 TST10 TST8 TST6 TST4 TST2 D5 MTCH1 TST1 D4 GA0R4 GA1R4 GA0T4 GA1T4 MTCH0 TST0 D3 GA0R3 GA1R3 GA0T3 GA1T3 PD TNFQ D2 GA0R2 GA1R2 GA0T2 GA1T2 PDTN ALAWN D1 GA0R1 GA1R1 GA0T1 GA1T1 PDCH1 SEL2B D0 GA0R0 GA1R0 GA0T0 GA1T0 PDCH0 PCMIF
Reserved Reserved
TABLE 10. REGISTER FUNCTIONS Address 000 Bit 0 1 2 3 4 5 6 7 001 0 1 2 3 4 5 6 7 Name GA0R0 GA0R1 GA0R2 GA0R3 GA0R4 0 0 GA1R0 GA1R1 GA1R2 GA1R3 GA0R4 0 0 0 0 Test mode Please write all "0". 0 0 0 1 1 0 0 Test mode Please write all "0". Receive gain adjustment on ch1 +6 to -18dB in 1dB steps 00000: +6dB 11xxx: -18dB Default 0 1 1 0 0 Function Receive gain adjustment on ch0 +6 to -18dB in 1dB steps 00000: +6dB 11xxx: -18dB
Application Note 9992
Application Note 9992 Test # 1 Normal Loop Feed Verification
This test verifies the correct tip and ring voltages in both onhook and offhook forward active and reverse active states. Loop current and ground key are also verified via on-board LEDs. When the forward loop back mode is initiated internal switches connect a 600 load across the outputs of the Tip and Ring amplifiers as shown in Figure 4.
TIP TIP AMP
Discussion
HC55185
RING AMP
FIGURE 4. FORWARD LOOP BACK INTERNAL TERMINATION
Measuring Tip and Ring Voltages
Most applications will operate the device from low battery while off hook. The DC feed characteristic of the device will drive Tip and Ring towards half battery to regulate the DC loop current. For light loads, Tip will be near -4V and Ring will be near VVBL + 4V. Figure 3 shows the DC feed characteristic.
VTR(OC)
VTR , DC (V)
ILOOP (mA)
7. Disconnect the 600 load from across tip and ring. 8. Repeat steps 3, 4 and 5.
TABLE 11. TIP AND RING VOLTAGES
FIGURE 3. DC FEED CHARACTERISTIC
The point on the y-axis labeled VTR(OC) is the open circuit Tip to Ring voltage and is defined by the feed battery voltage.
RL () Onhook Offhook 600 Onhook Offhook 600
TIP VOLTAGE REFERENCED TO GND -3.6 to -4.6 -4.6 to -5.6
RING VOLTAGE REFERENCED TO GND -17.2 to -21.1.0 -16.2 to -19.7
-17.2 to -21.1.0 -16.2 to -19.7
-3.6 to -4.6 -4.6 to -5.6
Application Note 9992 Test # 2 Loop Supervisory Detection
Verification of Switch Hook Detect
(EQ. 3) (EQ. 4)
20 RING R
FIGURE 5. LINEAR RINGING MODEL
Verification of Ground Key Detect
When the input signal at VRS is zero, the Tip and Ring amplifier outputs are centered at half battery. The device provides auto centering for easy implementation of sinusoidal ringing waveforms. Both AC and DC control of the Tip and Ring outputs are available during ringing. This feature allows for DC offsets as part of the ringing waveform.
Verification of Forward Loopback
Ringing Input
The ringing input, VRS , is a high impedance input. The high impedance allows the use of low value capacitors for AC coupling the ring signal. The VRS input is enabled only during the ringing mode, therefore a free running oscillator may be connected to VRS at all times. When operating from a battery of -100V, each amplifier, Tip and Ring, will swing a maximum of 95VP-P. Hence, the maximum signal swing at VRS to achieve full scale ringing is approximately 2.4VP-P. The low signal levels are compatible with the output voltage range of the CODEC. The digital nature of the CODEC ideally suits it for the function of programmable ringing generator.
Test # 3 Ringing Verification
This test will demonstrate the ability of the AK2306 / 2306LV to ring a phone through the HC55185. A telephone is the only additional hardware required to complete this test.
Discussion
The HC55185 provides linear amplification to support a variety of ringing waveforms. A programmable ring trip function provides loop supervision and auto disconnect upon ring trip. The device is designed to operate from the high battery during this mode.
Ringing the Phone
Architecture
The device provides linear amplification to the signal applied to the ringing input, VRS . The differential ringing gain of the device is 80V / V. The circuit model for the ringing path is shown in Figure 5. The voltage gain from the VRS input to the Tip output is 40V / V. The resistor ratio provides a gain of eight and the current mirror provides a gain of five. The voltage gain from the VRS input to the Ring output is -40V / V. The equations for the Tip and Ring outputs during ringing are given in Equations 3 and 4.
Application Note 9992
Test # 4 Emulation of Phone Conversation
Verification of Phone Conversation
1. Verify phone connection between both channels by picking up the receivers and talking. 2. Return dip switch SW5 to initial position (Table 4). 3. Reconnect DX and RX to PCM4.
Test # 5 Gain Verification
This test will verify the gains through the AK2306 / 2306LV and the HC55185 are operating properly. The test will show, with the receive and transmit gains programmed to 0dB, the Digital to Analog gain across both the CODEC and the SLIC is equal to -1.0 (0dB), and the Analog to Digital gain across both the SLIC and the CODEC is also equal to 1.0 (0dB). Both D / A and A / D gains will be verified by performing a Digital to Digital gain using the PCM4.
0dBm0(600) 0.7745VRMS
SYSTEM REQUIREMENTS: IMPEDANCE: 600 TRANSMIT GAIN (A / D): +5.0dB RECEIVE GAIN (D / A): 0dB INTERSIL HC55185 (1 OF 8) TIP VRX
0dBm0(600) 0.7745VRMS R7 33K R6 33K CRX 0.47µF CA 0.47µF RA 120K RF R8 49.9K 120K
AK2306 RECIEVE PATH GAIN 0dB
0dBm0(600) 0.7745VRMS DR
+ VTR RING
GST AMPT AMPLIFIER VFTN VFTP + TRANSMIT PATH GAIN 0dB DX
VTX RS 66.5K -IN CFB VFB 4.7µF CTX 0.47µF
0dBm0(600) 0.7745VRMS
-7.619dBm0(600) 0.32219VRMS
0dBm0(600) 0.7748VRMS
FIGURE 6. REFERENCE DESIGN OF THE HC55185 AND THE AK2306 WITH A 600 LOAD IMPEDANCE
Figure 6 shows the reference design of the HC55185 and the AK2306 with a 600 load impedance. Reference Application Note AN9991 for a detailed engineering analysis of the reference design.
AMPR AMPLIFIER PCM BUS
0dBm0(600) 0.7748VRMS
Application Note 9992
Total System Gain (D / D)
TABLE 12. PCM4 GENERAL PARAMETERS SETTINGS (Continued) General Parameter (9) Special Parameter: Level Display Two wire Term. Digital Channel no. Tolerance mask set 2 Clock display OFF Mark and cont. OFF Setting dBm0 Infinite Time Slot Mark and cont. Parm 11 13 16 22 23 27 33 35
Verification
Compare results to the Graph 1.
Test # 6 Variable Gain / Frequency
Discussion
Most of the SLICs in the HC55185 family feature two-wire loopback testing. During the two-wire loopback test, a 600 internal resistor is switched across the tip and ring terminals of the SLIC. This allows the DET function and the four-wire to four-wire AC transmission, right up to the subscriber loop, to be tested.
Variable Gain / Frequency (D / A) Test #6a
If previous test was Test #1, #2, #3, or #4, skip to Step 3. If previous test was Test # 5 skip to Step 5. 1. Configure hardware and software as described in section titled Getting Started.
RX Encoding Law (8) Scanner Parameter: VF-Input no. VF-Output no.
Must match encoding law 1 1
Application Note 9992
3. Set the general parameters of the PCM4 as shown in Table 12. Set the PCM4 Interface (port 14) to TX / RX. Set the RX-Impedance / (port 13) to 600. Set the TX-Impedance / (port 15) to 600. 4. Set the PCM4 transmit and receive channels to channel 0. This will enable the PCM4 to receive and transmit data to the Channel A PCM time slot. To test channel B, set the PCM4 to channel 1. 5. Remove the 600 load from across tip and ring. 6. Configure the PCM4 for the MODE A 33 test. Set PCM4 to D-A, SWP / S (single sweep). Press start to test network.
Test # 7 Total Distortion
Total Distortion (D / A) Test #7
Verification
Compare results to the Graph 2.
Verification
Compare results to the Graph 4.
GRAPH 2. (D / A) VARIABLE GAIN vs. FREQUENCY
Variable Gain / Frequency (A / D) Test #6b
1. Configure the PCM4 for the MODE A 33 test. Set PCM4 to A-D, SWP / S (single sweep). Press start to test network.
Verification
Compare results to the Graph 3.
FIGURE 4. (D / A) TOTAL DISTORTION
GRAPH 3. (A / D) VARIABLE GAIN vs. FREQUENCY
Application Note 9992 Board Schematic
INTERSIL + HC55185 (1 OF 2) IX RECEIVE BLOCK + 1:1 R IX VIN VRX + CRX VRX 0.47µF R RF R7 33K
AK2306 RECEIVE PATH DR
VFR R6 33K CA 0.47µF RA 120K GST AMPT AMPLIFIER + + GSR AMPR AMPLIFIER
FEED AMPLIFIER
FEED AMPLIFIER RSENSE V3 V4 + 20 IX - IM + + R 4R 4R 4R 4R
R8 49.9K
120K VFTN VFTP
TA FEEDBACK AMPLIFIER 3R
+ CTX VTX 0.47µF -
TRANSMIT PATH
RS 66.5K -IN CFB VFB
FIGURE 7. HC55185 SIMPLIFIED AC TRANSMISSION CIRCUIT AND AK2306
Application Note 9992 Board Schematic (continued)
INTERSIL + HC55185 (1 OF 2) IX RECEIVE BLOCK + 1:1 R IX VIN VRX + CRX VRX 0.47µF R RF R7 33K
AK2306LV RECEIVE PATH 0dB DR
VFR R6 33K CA 0.47µF RA 42.2K GST + + GSR AMPR AMPLIFIER
FEED AMPLIFIER
FEED AMPLIFIER RSENSE V3 V4 + 20 IX - IM + + R 4R 4R 4R 4R
R8 36.5K
30.1K VFTN VFTP
AMPT AMPLIFIER
TA FEEDBACK AMPLIFIER 3R
+ CTX VTX 0.47µF RS 66.5K -IN
TRANSMIT PATH 0dB
RIN 45.3K
CFB CIN VFB 0.47µF
RECEIVE GAIN FROM DR TO T / R IS +3.3dB TRANSMIT GAIN FROM T / R TO DX IS -9.3dB AK2306LV
LOW VOLTAGE CONNECTION
FIGURE 8. HC55185 DEMO DAUGHTER BOARD SCHEMATIC
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