Application Note July 2006 AN1247.0 Author: Ross Staffhorst

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Application Note July 2006 AN1247.0 Author: Ross Staffhorst

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Power Management Controller Mixed-Voltage FPGA Based Systems
Application Note July 2006 AN1247.0
Author: Ross Staffhorst
Introduction
Field Programmable Gate Arrays (FPGAs) providing path rapid prototyping implementation digital systems. classes programmable logic devices vary based memory utilization configuration. Power management systems designed support them must stand-up potential programming enhancements which boost their power requirements. Responding changing needs industry, Intersil introduces ISL6521 controller power mixed-voltage FPGAs. versatility ISL6521 lends well powering most embedded processor logic device which require regulated high current, voltage supply three independent, lower current supplies.
ISL6521 features overcurrent protection switching converter simple undervoltage protection linear controllers. more detailed description ISL6521 functionality, refer ISL6521 Data Sheet [1].
ISL6521EVAL1 Reference Design
ISL6521EVAL1 evaluation board intended provide versatile platform evaluation surface mount thru hole components. evaluation board designed meet output voltage current specifications shown Table synchronous buck converter sustain continuous load current handle step, 2.5A/µs load current transients. linear regulators designed supply continuous load current with third linear regulator providing 100mA with external pass device. board implemented 1-ounce, 2-layer, printed circuit board. pages schematic, bill materials, layout plots.
TABLE ISL6521EVAL1 DESIGN PARAMETERS PARAMETER Buck Regulator: Static Regulation VOUT1 Continuous Load Current Load-Current Transient Linear Regulators: Static Regulation VOUT2 Continuous Load Current Static Regulation VOUT3 Continuous Load Current 3.366V 2.550V 1.836V 120mA 1.764V 100mA 2.450V 3.234V 1.530V 2.5A/µs 1.470V
Intersil ISL6521
ISL6521 regulates four output voltages provides simple protection functions. controller drives external N-Channel MOSFETs synchronous buck converter topology. This output intended power internal core logic (VCCINT). integrated linear controllers drive 120mA directly, with external pass transistor. linear controllers typically power bank (VCCO), input buffer reference voltage (VREF), auxiliary logic (VCCAUX). power management block diagram FPGA shown Figure Integrated high-bandwidth error amplifiers accurate internal voltage reference insure static voltage regulation tolerance over line, load temperature ranges.
Controller
VCCINT
Static Regulation VOUT4 Core Logic Continuous Load Current
VCCO Linear VCCAUX Linear VREF Linear
Logic
Quick Start Evaluation
Circuit Setup
Connect bench power supply turrets located next Intersil logo, Figure Each output similar pair turrets labeled VOUTx GND. Each output exercised using either resistive electronic loads connected across these points. Once external supply loads connected board, supply energized. light emitting diode, should burn indicate power been applied board. red, power-down supply check external connections.
Logic
Buffer Reference
ISL6521
FPGA
FIGURE FPGA POWER MANAGEMENT BLOCK DIAGRAM
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. Rights Reserved other trademarks mentioned property their respective owners.
Application Note 1247
Output Voltage Ripple
evaluation platform designed meet core voltage ripple specification 20mV. Board performance shown Figure under room temperature conditions light loading. output voltage ripple measures less than 18mV. Adjustment output voltage ripple addressed Adapting Circuit Performance section.
Load Load
Load Load
VOUT1, 20mV/div
Power Indicator
Input Power Supply
PHASE, 5V/div 5µs/div
FIGURE EXTERNAL POWER SUPPLY LOAD CONNECTIONS
ISL6521EVAL1 Performance
Enabling Controller
Once bias voltage applied controller reaches rising Power-On Reset (POR) threshold, ISL6521 initiates soft-start interval. point which ISL6521 reaches rising threshold indicated Soft-start Begins Figure After short delay, four outputs begin ramping output levels external resistor dividers pins. controlled voltage ramp four outputs charges output capacitors each output slowly softens initial current drawn from bias supply. Reducing soft-start interval lasts about ends just after four output reach their programmed output levels. point soft-start ends indicated Soft-start Ends Figure
Soft-start Begins Soft-start Ends VOUT2, 1V/div VOUT3, 1V/div
FIGURE CORE VOLTAGE RIPPLE (VOUT1)
Protection Features
ISL6521 features overcurrent protection controller. linear controllers feature undervoltage protection which doubles overcurrent protection. controller uses upper MOSFET's on-resistance, rDS(on), monitor current flow through device. This current level then compared internally overcurrent trip point externally. overcurrent protection monitors these conditions cycle cycle basis. When overcurrent trip level exceeded, controller removes gate drive MOSFETs. ISL6521 then enters wait period equivalent three soft-start intervals. soft-start interval follows overcurrent condition remains, controller will trip again. This results hiccup mode response sustained short shown Figure controller exits this mode once output voltage soft-starts successfully bias removed from controller.
VCC, 2V/div
Event Occurs
VOUT4, 1V/div VOUT1, 1V/div
VOUT1, 0.5V/div
IOUT1, 5A/div
1ms/div
FIGURE SOFT-START INTERVAL
20ms/div
FIGURE HICCUP MODE OVERCURRENT PROTECTION
AN1247.0 July 2006
Application Note 1247
ISL6521EVAL1 designed with room temperature overcurrent trip point trip point OCSET resistor established relative rDS(on) upper MOSFET. product datasheet additional information setting this trip point. linear controllers feature undervoltage protection which also provide overcurrent protection. impedance short linear output will cause output voltage sag. When output voltage drops below output voltage point, linear controller shuts down. linear controller then enters wait period equivalent three soft-start intervals. soft-start interval follows undervoltage condition remains, linear controller will shutdown during soft-start. Until successful, linear controller will attempt restart output same hiccup mode style outlined above. Shutdown output does shutdown outputs. Figure output voltage rises response removal load inductor begins slew down original load level. controller detects output voltage rise immediately decreases upper gate pulse width. PHASE waveform shows that upper gate turned three four cycles inductor sheds load. upper gate pulse width then narrow next cycles inductor slowly picks load current. output voltage quickly settles back +1.5V point.
VOUT1, 50mV/div 1.5V
PHASE, 5V/div
Transient Response
FPGA transient specifications vary depending overall gate usage. ISL6521EVAL1 designed meet load step with slew rate 2.5A/µs. During transient, FPGA core voltage (VOUT1) must exceed ±50mV +1.5V. leading edge transient response ISL6521EVAL1 aforementioned load shown Figure core voltage waveform offset +1.5V.
VOUT1, 50mV/div 1.5V
IOUT1, 5A/div
10µs/div
FIGURE TRAILING EDGE TRANSIENT RESPONSE
PHASE, 5V/div
leading edge transient response less than 30µs trailing edge transient response less than 20µs. Achieving faster transient response time means reducing output inductance. lower inductance would allow inductor current transition faster load current changes. main trade-off speeding transient response drop efficiency reduced inductance.
Efficiency
IOUT1, 5A/div
performance ISL6521EVAL1 board, loaded from plotted Figure Measurements were taken
10µs/div
FIGURE LEADING EDGE TRANSIENT RESPONSE
core voltage sags inductor current begins slew response changing load current. controller detects load level drop output voltage responds increasing pulse width upper MOSFET. bulk output capacitors support load inductor slews. increase duty cycle seen looking PHASE waveform just before, during, after transient edge reaches inductor current rapidly increases meet demand, supplying increasing portion load. output voltage returns +1.5V point inductor picks load again.
EFFICIENCY
OUTPUT CURRENT
FIGURE EFFICIENCY LOAD CURRENT
AN1247.0 July 2006
Application Note 1247
room temperature thermal equilibrium with flow. converter design targets applications which specify minimum full load efficiency 80%. Design modifications output inductor and/or dual N-channel MOSFETs allow achieving higher efficiency.
Layout Considerations
Component placement trace layout important high frequency switching converter design. With power devices switching efficiently 300kHz, resulting current transitions from device another cause voltage spikes across interconnecting impedances parasitic circuit elements. These voltage spikes degrade efficiency, radiate noise into circuit, lead device over-voltage stress. Careful component layout printed circuit board design minimizes these voltage spikes.
Adapting Circuit Performance
board outlined this application note supports both surface mount thru hole devices. This feature adds flexibility evaluation process allowing easy replacement components with counterparts cost versus performance curve balancing. surface mount only applications designs with height restrictions, aluminum electrolytic bulk output capacitors could replaced with surface mount capacitors with similar characteristics achieve similar performance. Sanyo SVPC series Panasonic series capacitors provide surface mount options over range price points. Depending output voltage ripple requirements, inductor output capacitor selection critical achieving desired circuit performance. Care must taken adjust compensation components when changing output capacitance and/or inductance.
Component Placement
switching components should placed close ISL6521 first. Minimize length connections between input capacitors, power switch, placing them nearby. Position both ceramic bulk input capacitors close upper MOSFET drain possible. Position output inductor output capacitors between upper lower MOSFETs load. critical small signal components include bypass capacitors, feedback components, compensation components. Place converter compensation components close COMP pins. feedback resistors should located close possible with vias tied straight ground plane required.
Linear Combinations
ISL6521 linear controllers used individually provide 120mA each drive external pass device achieve linear controllers ganged together create 240mA regulator three linears tied together source 360mA. ISL6521EVAL1 evaluation platform supports evaluation this option. First, external pass devices, must removed. external pass devices, outlined yellow, highlighted Figure Next, resistors options, outlined green, must populated short output planes each linear together. feedback resistor pairs, accented red, each linear must matching provide proper voltage feedback. minimum current output, over temperature process variations, from combined linears 300mA.
Trace Routing Interconnects
Keep trace from PHASE terminal output inductor short wide. power plane layer, available, should support input power output power nodes. copper filled polygons phase node layers. Keep traces from UGATE LGATE pins MOSFET gates short wide easily handle drive current. order dissipate heat generated internal linears drivers, ground pads (pins should connected ground plane through least four vias. This allows heat move away from also ties ground plane through impedance path.
Summary
ISL6521EVAL1 adaptable evaluation tool which showcases performance ISL6521CB. Designed meet performance requirements current FPGA applications, allows user flexibility configure future designs well. following pages provide schematic board, bill materials, layout drawings support implementation this solution.
References
FIGURE COMPONENT CHANGES COMBINING LINEARS
Intersil documents available http://www.intersil.com/ ISL6521 Data Sheet, Intersil Corporation, File FN9148
AN1247.0 July 2006
Application Note 1247
Schematic
AN1247.0 July 2006
Application Note 1247 Bill Materials
REFERENCE C12, C14, C11, R11, R12, R13, P1-P10 1514-2 MA732CT SSL-LXA1725IC P1173.602T FDS6912A FZT649 PART NUMBER ISL6521CB ECU-V1H681KBV ECJ-1VB1H183K ECJ-1VB1H223K ECJ-1VBC104K EEUFC1A681L ECJ-1VB1C104K UHM0J182MPT6 ECJ-1VB0J105K GRM31CR60J226KE19L DESCRIPTION Controller with Triple Linears 680pF, 50V, X7R, 10%, Ceramic Capacitor 0.018µF, 50V, X7R, 10%, Ceramic Capacitor 0.022µF, 50V, X7R, 10%, Ceramic Capacitor 0.1µF, 16V, X7R, 10%, Ceramic Capacitor 680µF, 10V, Aluminum Electrolytic Capacitor 0.1µF, X7R, 16V, 10%, Ceramic Capacitor 1800µF, 5.3V, Special Polymer Aluminum Capacitor, 1µF, X5R, 6.3V, 10%, Ceramic Capacitor 22µF, X5R, 6.3V, 10%, Ceramic Capacitor DNP, Ceramic Capacitor Schottky Diode, 30V, 150mA 2X2.5MM Clear 6.0µH, 6.9A, Shielded Power Inductor Dual N-Channel Power MOSFET, Transistor, 25V, Resistor, 4.12k, 1/10W Resistor, 4.64k, 1/10W Resistor, 48.7k, 1/10W Resistor,4.99k, 1/10W Resistor, 18.2k, 1/10W Resistor, 5.9k, 1/10W Resistor, 12.7k, 1/10W Resistor, 5.9k, 1/10W Resistor, 9.09k, 1/10W Resistor, 7.15k, 1/10W Resistor, 2.43k, 1/10W Resistor, 37.4, 1/10W Resistors, combine linears into supply Large Test Point S-Mini SO-8 SOT-223 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 1206 Thru Hole Panasonic Lumex Pulse Fairchild Zetex Various Various Various Various Various Various Various Various Various Various Various Various Various Keystone PACKAGE SO-8 0603 0603 0603 0603 0603 0805 1206 VENDOR Intersil Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Nichicon Panasonic Murata
AN1247.0 July 2006
Application Note 1247 ISL6521EVAL1 Layout
SILK SCREEN
ASSEMBLY
AN1247.0 July 2006
Application Note 1247 ISL6521EVAL1 Layout (Continued)
LAYER
BOTTOM LAYER
Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that Application Note Technical Brief current before proceeding.
information regarding Intersil Corporation products, www.intersil.com
AN1247.0 July 2006

Application Note July 2006 AN1247.0 Author: Ross Staffhorst

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