Application Note August 2002 AN1002 Author: Chun Cheung Abst
|
|
|
Top Searches for this datasheet
200W, 470kHz, Telecom Power Supply Using ISL6551 FullBridge Controller ISL6550 Supervisor Monitor
Application Note August 2002 AN1002
Author: Chun Cheung
Abstract
This application note highlights design considerations 200W, 470kHz, telecom power supply using Intersil's ISL6551 FullBridge Controller ISL6550 Supervisor Monitor. zero-voltage switching technique ISL6551 presented detail. step-by-step design procedure 48V-to-3.3V@60A with efficiency converter based these chips, incorporating both full bridge current doubler topologies, described. tips design debugging then listed. Finally, experimental results with discussion gives users deeper understanding performance reference design advantages ISL6550 ISL6551.
Introduction
medium high power applications with extreme efficiency requirements, full-bridge topology probably best choice. Besides great transformer utilization with this topology, higher efficiency lower levels major benefits utilizing circuit parasitics, which include output capacitance bridge FETs, primary capacitance transformer, leakage inductance, achieve zerovoltage transitions (ZVT). conventional full bridge converter, these advantages cannot realized without employing significant amount soft-switching/resonant circuitry which adds cost circuit board real estate. Intersil's ISL6551 full-bridge controller implements unique control algorithm, rather than traditional phase-shifted control technique introduced TI's UC3875, achieve with components. addition, ISL6551 integrates additional sophisticated features such Leading Edge Blanking, Latching Shutdown Input, Enable Input, Current Share Support, Fast Short-Circuit Shutdown, Synchronous Drive Signals, Power Good Indication that UC3875 does provide. ISL6551 enables complete sophisticated power supply solution save board space engineering effort well cost. This application note provides detailed design considerations 200W telecom power supply reference design employing both Intersil's ISL6551 full-bridge controller ISL6550 Supervisor Monitor while taking advantage both full-bridge current doubler topologies, shown Figure alternative secondary rectification technique push-pull bridge converters introduced Laszlo Balogh paper [2]. This technique offers potential benefits better distributed power dissipation densely packed power supplies medium high power and/or high output current applications [2]. This converter designed meet specification industry-standard half brick. Most converter circuits placed central 2.50"x2.45" area limited within 0.5" height, other unnecessary components such test point connectors connectors placed beyond this area. easily modify evaluation board broader base applications, additional circuits designed
magnetics components integrated with PCB. This expands area evaluation board when compared standard half-brick design. This DC/DC converter accepts wide range input generates DACadjustable wide range output 2.64V 3.63V with 31.918mV step. ultra high efficiency 3.312V with fully loaded output been achieved.
FIGURE FULL BRIDGE CURRENT DOUBLER TOPOLOGIES
This application note first introduces unique technique ISL6551. Supervisor Monitor ISL6550 chip then briefly introduced. Thereafter, stepby-step design procedure reference design followed, including power train component selection, component power dissipation calculations, magnetics design parameter calculations, control loop design. tips design debugging listed. Finally, experimental results evaluation board discussed. Term Definitions, Block Diagram, Schematics, Layout, Bill Materials, References, Preliminary Specifications Reference Design included this paper.
Intersil Full Bridge Controller: ISL6551
diagonal bridge switches turned together conventional full bridge converter which alternatively places input voltage, VIN, across primary transformer period Ton, shown Figure limiting factor achieving optimum efficiency this circuit hard switching nature operation, which causes significant
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. Rights Reserved
Application Note 1002
switching losses high frequency, high input voltage, high current applications. switching losses reduced employing snubbers, quasi- fully resonant, soft-switching circuits [1]. driven fixed duty cycle lower switches PWM-controlled trailing edge while leading edge employs resonant delay. Figure shows drive signals four bridge FETs three options synchronous rectification. basic control principle ISL6551 different from that UC3875's phase-shift control which varies phase between duty cycle control signals [1], requiring additional circuitry derive synchronous control signals therefore adding cost. ISL6551 full bridge controller that Intersil designed medium high power AC/DC DC/DC applications with ultra high efficiency requirements. ISL6551 includes many integrated features more complete sophisticated telecom off-line power supply solution. internal architecture shown Figure Detailed operation ISL6551 will presented describing switching actions power train each time interval following sections. Refer device datasheet operation integrated features.
ON/OFF
FIGURE CONVENTIONAL FULL BRIDGE WAVEFORMS
ISL6551, rather than driving both diagonal full bridge switches together, upper switches
LATSD
BANDGAP REFERENCE
UVLO
SHUTDOWN LATCH SOFT START
BGREF PKILIM
SHUTDOWN
VDDP1
UPPER1 DRIVER R_LEB R_RESDLY RESODLY ISENSE R_RA RAMP ADJUST UPPER2 DRIVER
UPPER1
UPPER2
CLOCK GENERATOR ERROR LOGIC LOWER1 DRIVER
VDDP2
LOWER1
LOWER2 DRIVER EANI CURRENT SHARE
LOWER2
DCOK
SYNC1
PGND
SYNC2
SHARE
CS_COMP
Circuits Referenced
Circuits Referenced PGND
NOTE: numbers diagram refer SOIC package.
External Single Point Connection Required
FIGURE ISL6551 INTERNAL STRUCTURE
Application Note 1002
CLOCK
LOW1
LOW2
SYNC1
SYNC2
LOW1'
LOW2'
SYNC2
SYNC1
T8=T0
T0-T1=LOWER RIGHT-LEG POWER TRANSFER PERIOD T1-T2=UPPER LEFT-TO-RIGHT FREEWHEELING PERIOD T2-T3=Q1-TO-Q2 DEADTIME (FREEWHEELING) T3-T4=LOWER LEFT-LEG RESONANT PERIOD
T4-T5=LOWER LEFT-LEG POWER TRANSFER PERIOD T5-T6=UPPER RIGHT-TO-LEFT FREEWHEELING PERIOD T6-T7=Q2-TO-Q1 DEADTIME (FREEWHEELING) T7-T8=LOWER RIGHT-LEG RESONANT PERIOD
above Figure, through exaggerated only demonstration purposes. There three possible synchronous rectification drive schemes: Existing Synchronous Drive Signals (Sync1 Sync2) Non-inverting High Current Drivers (such MIC4422)- Synchronous Fets turned together dead time turned alternatively every clock period; Lower Drive Signals Proper Delay Inverting High Current Drivers (such MIC4421)- corresponding synchronous turned whenever voltage across secondary winding; Existing Synchronous Drive Signals Inverting High Current Drivers- synchronous FETs turned together dead time turned alternately every clock period.
FIGURE DRIVE SIGNALS TIMING DIAGRAM
Application Note 1002
(VsVo/Lo
Vo/Lo
ILO1 ILO2
)/Lo
(Vs-
2Vo/L
)/Lo
Vo/Lo
Fclock
WORST CASE
(Vs-
Vo)/L (Vs-2
2Vo/Lo
WORST CASE
WORST CASE
(Vs-2
Vo)/L
2Vo/Lo
IMAG
Vin/L
-Vin
/Lma
Vo/NLo
WORST CASE
o)/NL (Vs-V
o+Vin
Imag Imag Io-2N
SYNC1 SYNC2
LOW1' LOW2'
SYNC2 SYNC1
T0-RESDLY
T8=T0
T0-T1=LOWER RIGHT-LEG POWER TRANSFER PERIOD T1-T2=UPPER LEFT-TO-RIGHT FREEWHEELING PERIOD T2-T3=Q1-TO-Q2 DEADTIME (FREEWHEELING) T3-T4=LOWER LEFT-LEG RESONANT PERIOD
T4-T5=LOWER LEFT-LEG POWER TRANSFER PERIOD T5-T6=UPPER RIGHT-TO-LEFT FREEWHEELING PERIOD T6-T7=Q2-TO-Q1 DEADTIME (FREEWHEELING) T7-T8=LOWER RIGHT-LEG RESONANT PERIOD
above figure, through exaggerated only demonstration purposes. slope each waveform approximation. more accurate representation, losses should included. worst case happens only carrying load current during freewheeling period. current distribution through different these three drive schemes. Case best option since both synchronous FETs turned during freewheeling period. Note that case primary leakage inductance, otherwise, delay would induced, illustrated experimental results.
FIGURE CURRENT WAVEFORMS
Application Note 1002
->T1, QA-to-QD Power Transfer (Active) Period [Figure
transformer output capacitance discharged from zero voltage (~diode drop).
OFF,
SYNCHRONOUS FETS SYNC DRIVE INV_LOW DRIVE INV_SYNC DRIVE
SYNCHRONOUS FETS SYNC DRIVE INV_LOW DRIVE INV_SYNC DRIVE
FIGURE QA-TO-QD POWER TRANSFER PERIOD
FIGURE QA-TO-QC CLAMPED FREEWHEELING PERIOD
When turned been already turned previous period, resonant delay. this transfer (active) period, full input voltage (VIN) across primary transformer, VIN/N across secondary transformer once primary current catches reflected output current. primary current first flows from prior resonant current then reverses direction until current reaches zero starts ramping rate determined VIN, magnetizing inductance, output inductance. Simultaneously, should stay eliminating shootthrough currents, turned reduce conduction losses; current through positive ramp, current through negative ramp. ON-time function VIN, transformer turns ratio output load turned when peak modified current ramp signal hits error voltage, freewheeling period then begins.
QA-to-QC Clamped Freewheeling (Passive) Period [Figure
Once turned trailing edge pulse width modulation, primary current continues flowing into output capacitance (Coss) which will charged from switch Rds(on) Drop Diode Drop. Simultaneously, primary capacitance (Cp)
This transition accomplished using energy stored leakage inductance transformer, magnetizing inductance, reflected output inductance, external commutating inductance. After transition, primary current flows same direction real freewheeling period begins. transformer shorted channel other clamped body diode which only path that primary current through. losses body diode conduction freewheeling period could significant primary current (the lumped magnetizing current reflected secondary winding freewheeling current), relatively high. These conduction losses minimized employing maximum allowable turns ratio main transformer, i.e, maximum allowable duty cycle design. some applications, shunting upper switches with Schottky diodes might another possible reduce conduction losses. wide range input application, pre-regulator implemented, then fixed, high duty cycle (~100%) post full-bridge regulator achieved freewheeling time minimized. power dissipation upper FETs therefore reduced significantly. Three different synchronous rectification drive schemes implemented with ISL6551 shown Figures INV_LOW DRIVE scheme that would provide additional path secondary freewheeling
Application Note 1002
current since both turned during freewheeling time, which could reduce conduction losses reflected output current primary. amount load current split into depends voltage drop across secondary winding, Rds(on) and/or body diode drop optimum performance converter happens when load current split into both turned-on evenly. reality, body diode drop upper FETs, leakage inductance, shorted primary winding force synchronous FETs carry majority output current while other conducts minority load.
Lower Left-Leg (QB) Resonant Period [Figure
OFF,
Q1-to-Q2 Dead Time Period [Figure
OFF,
SYNCHRONOUS FETS SYNC DRIVE INV_LOW DRIVE
INV_SYNC DRIVE
FIGURE LOWER LEFT-LEG RESONANT PERIOD
SYNCHRONOUS FETS SYNC DRIVE INV_LOW DRIVE INV_SYNC DRIVE
FIGURE Q1-TO-Q2 DEAD TIME PERIOD
dead time used prevent simultaneous conduction which would cause shoot-through currents. dead time still part freewheeling period. drive control signals power switches therefore change states while drive signals synchronous FETs change levels. SYNC DRIVE scheme, both turned load current freewheels through body diodes both FETs. This introduces high conduction losses high output current applications. Shunting both synchronous FETs with schottky diodes reduce losses. INV_SYNC DRIVE scheme, both turned therefore, schottky diodes required, INV_LOW DRIVE scheme.
dead time period followed lower left-leg resonant period. begins with turned turned beginning this transition, input voltage applied first across commutating inductance (leakage external inductances), i.e, real primary stays zero until current through these inductors changes direction next time interval. This seen voltage waveforms across primary winding secondary winding, discussed EXPERIMENTAL RESULTS section pages 24-25. direction current through primary winding remains same that previous time interval. current flows into transformer primary capacitance (Cp) output capacitance (Coss) which will charged from zero voltage (~Rds(on) Drop) VIN. Simultaneously, output capacitance discharged from VINRds(on) Drop zero voltage (~diode drop). This transition accomplished with energy stored primary inductance (including leakage inductance, magnetizing inductance, external inductance). takes longer time complete this transition than reaching freewheeling period since energy stored resonant inductances decreases conduction losses power switches primary current decaying freewheeling period. Once clamped zero voltage body diode, turned zero voltage (ZVS transition). Another power transfer period followed other diagonal power switches (QC-to-QB). rest
Application Note 1002
discussion (Figures just repetition another half cycle. discharged from zero voltage (~diode drop). This transition accomplished using energy stored leakage inductance transformer, magnetizing inductance, reflected output inductance, external commutating inductance. After transition, primary current flows same direction real freewheeling period begins. transformer shorted channel other clamped body diode which only path that primary current through. Refer T1->T2 period more detailed discussion.
OFF,
QC-to-QB Power Transfer Period [Figure
SYNCHRONOUS FETS SYNC DRIVE INV_LOW DRIVE INV_SYNC DRIVE
FIGURE QC-TO-QB POWER TRANSFER PERIOD
When turned been already turned previous period, resonant delay. this transfer (active) period, full input voltage (VIN) across primary transformer, VIN/N across secondary transformer once primary current catches reflected output active current. primary current first flows from prior resonant current then reverses direction until current reaches zero starts ramping rate determined VIN, magnetizing inductance, output inductance. Simultaneously, should stay eliminating shootthrough currents, turned reduce conduction losses; current through positive ramp, current through negative ramp. ON-time function VIN, transformer turns ratio output load turned when peak modified current ramp signal hits error voltage, another freewheeling period then begins.
SYNCHRONOUS FETS SYNC DRIVE INV_LOW DRIVE INV_SYNC DRIVE
FIGURE QC-TO-QA CLAMPED FREEWHEELING PERIOD
Q2-to-Q1 Dead Time Period [Figure
dead time used prevent simultaneous conduction which would cause shoot-through currents. dead time period still part freewheeling period, drive control signals power switches therefore change states while drive signals synchronous FETs change levels. SYNC DRIVE scheme, both turned off, load current free wheels through body diodes both FETs, which introduces high conduction losses high output current applications. Shunting both synchronous FETs with schottky diodes reduce losses. INV_SYNC DRIVE scheme, both turned therefore, schottky diodes required, INV_LOW DRIVE scheme.
->T6, QC-to-QA Clamped Freewheeling Period (Passive) [Figure
Once turned off, primary current continues flowing into output capacitance (Coss) which will charged from switch Rds(on) Drop Diode Drop. Simultaneously, primary capacitance (Cp) transformer output capacitance
Application Note 1002
OFF,
OFF,
SYNCHRONOUS FETS SYNC DRIVE INV_LOW DRIVE INV_SYNC DRIVE
SYNCHRONOUS FETS SYNC DRIVE INV_LOW DRIVE INV_SYNC DRIVE
FIGURE DEAD TIME PERIOD
FIGURE LOWER RIGHT-LEG RESONANT PERIOD
T8=To, Lower Right-Leg (QD) Resonant Period [Figure
previous dead time period followed lower rightleg resonant period. begins with turned turned beginning this transition, input voltage applied first across commutating inductance (leakage external inductances), i.e, real primary stays zero until current through these inductors changes direction next time interval. This seen voltage waveforms across primary winding secondary winding, discussed EXPERIMENTAL RESULTS section page 24-25. direction current through primary winding remains same that previous time interval. current flows into transformer primary capacitance (Cp) output capacitance (Coss) which will charged from zero voltage (~Rds(on) Drop) VIN. Simultaneously, output capacitance discharged from VINRds(on) Drop zero voltage (~diode drop). This transition accomplished with energy stored primary inductance (including leakage inductance, magnetizing inductance, external inductance). takes longer time complete this transition than reaching freewheeling period since energy stored resonant inductance decreases conduction losses power switches primary current decaying freewheeling period. Once clamped zero voltage body diode, turned zero voltage (ZVS transition). this point full operating cycle completed.
Intersil Supervisor Monitor: ISL6550
ISL6550 precision flexible, VID-code-controlled reference voltage monitor high-end microprocessor memory power supplies. monitors various input signals, supervises systems with outputs. ISL6550 saves board space, design time, system cost. internal structure ISL550 shown Figure reference design implemented with MLFPpackaged ISL6550, version. Refer device datasheet operating details. reference design, ISL6550 monitors output voltage supervises ISL6551 full bridge controller. spare operational amplifier ISL6550 used differential amplifier output (VOPOUT) sent inverting input (EAI) error amplifier ISL6551. Note that VOPOUT limited under-voltage delay (UVDLY) prevents false triggering START output during startup, ISL6550 START output ON/OFF input ISL6551. output over-voltage (+8.33%) under-voltage (8.33%) conditions, START triggered latches shutdown ISL6551 controller. When ISL6550 below turn-on/off threshold, START held disables ISL6651 controller. output reference BDAC, which noninverting input (EANI) error amplifier ISL6551, programmed 5-bit VIDs resistor network that connects DACHI DACLO. Note that total resistance network recommended overall
Application Note 1002
output error should include VREF5 error external resistor divider error well internal buffer offset. reference design, output voltage programmed from 2.64V 3.63V with 31.918mV step +/-3% statics error over full operating conditions. output voltage sensed OVUVSEN, OV-UV windows centered around BDAC voltage programmed with OVUVTH from +/-5% +/-40% about BDAC voltage. reference design, over/under voltage window +/-8.33%. connected mechanical switch turn on/off converter manually. also controlled circuitries that monitor input voltage level thermal condition converter. PGOOD provides indication output voltage within over/under voltage limits (+/-8.33%).
Buffered
VREF5 Opamp VOPM VOPP VOPOUT
LOGIC BLOCK below
PEN: Enable; Disable
START
10uA
OVUVSEN
UVLOCKOUT (POR)
POR: low;
Over-Voltage; OVUVTH
THRESHOLD PROGRAM
UV/OV hysteresis Note below
PGOOD Under-Voltage; UVD: Delay timed out; time-out
DACHI
UVDELAY (each pin) 10uA
UVDLY
VID4 VID3 VID2 VID1
BDAC
VID0 DACLO
Note: UV/OV hysteresis
FAULT LATCH
Note: UV/OV hysteresis
Note: UV/OV hysteresis
Fault; Fault NOTE: latch
Fault; Fault FAULT LATCH
NOTE: input dominates
NOTE: input dominates
NOTE: numbers diagram refer SOIC package. FIGURE ISL6550 INTERNAL STRUCTURE
Application Note 1002 Converter Design
This section presents step-by-step design procedure 48V-to-3.3V, 200W, 470kHz with efficiency converter using both ISL6551 ISL6550 telecom applications (i.e VIN=36V-to-75V). converter designed with secondary-referenced, peak current-mode control, both full bridge current doubler topologies. simplicity, calculations this section neglect transitions shown Figure worst case current waveforms used even INV_LOW DRIVE scheme, unless otherwise stated.
(EQ.
Although INV_LOW scheme better choice from power dissipation standpoint, user should special attention impact having overlap between both synchronous FETs during freewheeling period current share, light load, start turn-off operations. Some discussions presented EXPERIMENTAL RESULTS section.
Select Switching Frequency Define Maximum Available Duty Cycle
Several things considered when selecting appropriate switching frequency particular application. size converter (limited sizes magnetics components), overall losses magnetics components, switching losses power MOSFETs, desired efficiency, transient response, maximum achievable duty cycle considerations. iterative process required, monitoring changes above parameters, obtain optimum switching frequency particular application. Users equations presented this paper design MathCAD worksheet, which will help obtain rough idea range optimum frequencies their applications. Note that higher switching frequency higher loop bandwidth (typical 1/10 higher switching frequency) realized, lower maximum duty cycle available. initial design evaluation board, these parameters pre-selected: Fsw=250kHz=Fclock/2, tDEAD=200ns, tRESDLY=100ns. maximum available duty cycle then calculated using (Dmaxav=85%). duty cycle defined this application note ratio ON-time interval lower clock period.
DEAD RESDLY Dmaxav Fclock (EQ.
Select Synchronous DRIVE Scheme
INV_LOW DRIVE scheme synchronous rectification employed reference design. This scheme induces less conduction losses synchronous FETs than both INV_SYNC SYNC DRIVE schemes, which explained with equations (EQ. terms used equations defined later paper, unless otherwise stated text.
(EQ.
(EQ.
power dissipation same active (transfer) period different freewheeling period three drive schemes. both INV_SYNC SYNC DRIVE schemes, only synchronous turned carrying load current during freewheeling period. conduction losses each freewheeling period approximated with
Psynfetfr Rdsonsyn (EQ.
INV_LOW DRIVE scheme, both synchronous FETs turned each carries portion load current during freewheeling period. power dissipation each this period reduced
Psynfetfr Rdsonsyn (EQ.
Define Turns Ratio
primary-to-secondary turns ratio main transformer should chosen high possible without exceeding maximum available duty cycle (Dmaxav=0.85) minimum line (Vinmin=36V, input setpoint) rated load (Io=60A) situation. higher turns ratio less load current reflected primary side, less power losses induced primary MOSFETs. maximum allowable turns ratio calculated with (Nmax=3.79).
Vomax Vmisc Vsynfet Dmaxav Vinmin Rdsonpri Vsynfet (EQ.
Comparing note that INV_LOW scheme induces less power dissipation synchronous FETs amount
Psynfetfr Rdsonsyn (EQ.
addition, INV_LOW scheme also helps down conduction losses primary FETs since primary less reflected secondary current, which decreases with difference between IQ2, shown
Application Note 1002
where Vsynfet Rdsonsyn/2 channel drop synchronous FETs half load (assuming that output load split evenly into both synchronous FETs during freewheeling period), Vomax maximum output voltage (3.63V), Vmisc miscellaneous voltage drops including contact resistance, winding resistance, copper resistance. initial guess Vmisc 0.3V having safe margin. load (Io) conducts through only synchronous during freewheeling period, then simplified (Nmax=3.77):
Vomax Vmisc synfet Dmaxav Vinmin Rdsonpri (EQ.
minimum required output capacitance (Co) estimated when limiting output ripple voltage contributed output capacitance more than dVCo.
Fclock (EQ.
addition meeting requirements output capacitors should able absorb output current, defined
Iorms (EQ.
With assumptions Rdsonpri=25 x1.2m (Tj=500C) Rdsonsyn=1.125x1.13m (Tj=500C), produces Nmax=3.77. Since size height converter limited that telecom half brick, planar transformer with number turns both primary secondary sides required. Therefore, 11/3 turns ratio preferred choices. transformer with primary turns secondary turns been used reference design availability magnetic cores stock. fact, transformer with 11/3 turns ratio generally recommended.
Output Filter Design (Current Doubler)
output filter normally defined based requirements output ripple voltage (70mV) transient response (dVtr=150mV). general, requirement transient response met, then output ripple voltage will within limit. rule thumb, overall ripple current (dIo) should more than rated load, output inductor value (for each one) defined
synfet -dIo Fclock (EQ.
output voltage ripple conservatively approximated first terms (dVESR dVESL) contributed equivalent series resistance (ESR) equivalent series inductance (ESL) output capacitors dominant ones normally accurate enough estimate ripple voltage. last term (dVCo) contributed output capacitance (Co) normally much smaller neglected since peak dVCo happens ripple current across zero does align with peak dVESR, shown Figure positive negative peaks overall ripple voltage (sum three components) relative level symmetric (caused dVCo dVESL) unless converter operates duty cycle. This asymmetry between positive negative peaks concern most applications since both dVCo dVESLare generally very small compared portion. Note that level remains constant. Refer more details.
Voripple Fclock (EQ.
dVESR
dVESL
ripple current (dI) through each inductor calculated with
synfet Fclock (EQ.
dVCo
FIGURE OUTPUT RIPPLE VOLTAGE COMPONENTS
requirement transient response major factor defining maximum overall output capacitors Note that this converter designed meet 150mV transients (dip/overshoot) rated load step (ESR 10m).
dVtr -Istep (EQ.
capacitor usually listed databooks. practically approximated with
Fres (EQ.
where Fres resonant frequency that produces lowest impedance capacitor. very edge transient, equivalent output capacitors induces spike, defined
Application Note 1002
given dI/dt, that adds existing voltage undershoot/overshoot capacitance.
f(Istep)
(EQ.
load transients. This could cause significantly large undershoot/overshoot output. reference design, loop bandwidth (fc) lower than zero [1/(2*ESR*Co)] output capacitors, which have transient component dI/dt(1A/us), therefore, required output capacitance roughly approximated with [7].
Istep dVtr (EQ.
Istep
Several lower-profile TAIYO YUDEN 100u, 6.3V capacitors (JMK212F107MM) have been used evaluation board meet electrical requirements above discussion height constraint converter. Besides ESL, ESR, capacitance output capacitors, other system parasitics such board resistance inductance should included load transient analysis [6], which will discussed this paper. Electrical design parameters output inductors summarized EQs. which specify ripple current, peak current, current each inductor.
Iindpeak Iindrms (EQ.
FIGURE TYPICAL TRANSIENT RESPONSE WAVEFORM
Thus, overall output voltage undershoot/overshoot load transients summarized which last term normally dropped very edge transient dominant peak, shown Figure
dVtr Istep (EQ.
where
Istep Istep Istep Istep Istep Istep HUMP
(EQ.
Calculations Synchronous FETs
Some fundamental formulas that used calculate values triangular trapezoid waveforms derive most equations this paper defined below.
CASE Irms1 CASE Irms3
step-up transients step-down transients
last term direct consequence amount output capacitance. After initial spike, excessive charge dumped into output capacitors step-down transients causing temporary hump output, output capacitors deliver extra charge meet load demand step-up transients causing temporary before output inductors catch load. approximate response time intervals removal application transient load defined dTp, respectively.
Istep HUMP (EQ.
where
Istep -2Vo (EQ.
Irms2
Istep
CASE
where
Istep
low-profile, high current density, high frequency applications, required output capacitance defined might enough deliver absorb energy
power transfer period, synchronous turned off, other turned conducting load
Application Note 1002
CASE
current flows through body diodes FETs, external schottky diodes. worst case, freewheeling current flows through only leg, average current dead time estimated where tDEAD dead time tRESDLY resonant time.
DEAD DEAD RESDLY 0.5T Isyndeadavg (EQ.
Irms4 WHERE
current. peak current through defined load current plus half output ripple current this period, current through each calculated with using Case formula. Note that duty cycle defined ratio ON-time interval lower over clock period (twice switching period), which explains factor equation.
Isynpeak Isynrmstr (EQ.
additional term "Isyndeadavg Vdsyn" should added SYNC DRIVE scheme implemented. Isynrmsfr however would slightly smaller. maximum voltage across synchronous approximated with adding margin ringing rising edge.
Vinmax Vsynmax (EQ.
(EQ.
worst case, load current flows through synchronous FETs during freewheeling period (including resonant dead periods simplicity), current through estimated
Isynrmsfr (EQ.
synchronous FETs should selected such that rating power rating MOSFETs greater than Vsynmax Psynfet, respectively. Four Siliconix Si4842DY MOSFETs used each leg. Note that switching losses, which will discussed later, should included calculation define maximum power dissipation.
Thus, overall current through synchronous defined while conduction losses each synchronous calculated with
Isynrms Isysrmstr Isysrmsfr (EQ. (EQ.
Calculations Primary Switches (QA,
peak current through primary winding happens active period, defined
Imag Ipripeak Rdsonpri Imag -Lmag Fclock (EQ.
Psynfet Isynrms Rdsonsyn
(EQ.
shown EQs. higher ripple current i.e., lower output inductances are, higher currents are, higher conduction losses synchronous FETs are. addition, distribution factor (FDIST) currents during freewheeling period INV_LOW DRIVE scheme included accurate calculation:
DIST (EQ.
defines peak-to-peak magnetizing current. current through power switches active period estimated which also defines overall current through lower FET.
Iprirmstr where Imag (EQ.
where percentage load current through synchronous FETs. guess made looking primary freewheeling current, shown EXPERIMENTAL RESULTS section. other drive schemes, FDIST one. SYNC DRIVE scheme, both synchronous FETs turned during dead time period. freewheeling
there time delay turn lower after output capacitance completely discharged, i.e, resonant delay longer than necessary, then current will flow through body diode lower FET, which average value defined
Imag Ipriavgres (EQ.
Application Note 1002
freewheeling current flows through channel body diode upper FETs alternate freewheeling periods alternate directions. current through channel calculated with average current through body diode upper estimated with
Iprirmsfr Imag (EQ. Ipriavgfr Imag (EQ.
happens D=0.5. Several lower-profile Paktron capacitors (105K100ST2814) external capacitor have been used evaluation board. hold time (tHOLDUP) required when input line momentarily disconnected, then helps define required hold capacitance:
HOLDUP HOLDUP HOLDUP Efficiency HOLDUP (EQ.
where
Thus, overall current through channel each upper defined
Iprirms Iprirmstr Iprirmsfr (EQ.
With above average current information, conduction losses each power switch roughly estimated with EQs. shown EQs. higher inductor ripple current magnetizing current are, i.e., lower output inductance magnetizing inductance are, larger currents are, higher power losses would induced primary switches.
Pupfet Iprirms Rdsonpri Ipriavgfr (EQ.
overall input voltage ripple induced capacitance input capacitors estimated with addition, spikes caused input capacitors should decoupled with lower ceramic capacitor.
Vinripple ESRin Ipripeak (EQ.
Furthermore, level performance, additional filter might required front end. However, combination both full bridge current doubler topologies helps reduce size this input filter.
Switches Losses Driver Losses
Plowfet Iprirmstr Rdsonpri Ipriavgres (EQ.
Four 100V Siliconix SUD40N10 MOSFETs selected bridge switches such that ratings device greater than Pupfet, Plowfet, maximum input voltage. Note that switching losses, which will discussed later, should included EQs. define maximum power dissipation primary switches, which limits MOSFET selection.
Input Filter Design
input pulsating current filtered input capacitors value while minimum required input capacitance defined
general, switching losses insignificant portion compared conduction losses power switches transitions achieved. Since commutating inductances store peak energy swing output capacitance upper from zero volt beginning freewheeling period before upper turned therefore, upper FETs lossless turn transitions. freewheeling period, commutating inductances store least energy, which might enough (especially high line and/or load conditions) swing output capacitance lower zero volt before they turned turn-on losses lower FETs approximated with turn-off losses primary switches minimized with high speed driver such Intersil HIP2100.
Ppriswon (EQ.
Iinrms
(EQ.
dVincap
(EQ.
dVINcap acceptable input ripple voltage contributed amount input capacitance, which input capacitors (ITW Patron capacitors reference design) that filter most pulsating currents. maximum value happens D~0.5, while maximum value
When lower turned off, corresponding upper clamped very short time. corresponding synchronous turned when voltage across secondary winding vanishes, therefore, there turn-on switching losses synchronous FETs. resonant delay delay caused leakage inductance have voltage across
Application Note 1002
secondary winding, illustrated EXPERIMENTAL RESULTS, prior turn synchronous FET, help achieve synchronous FETs turn off. achieve discussed previous lines, synchronous drivers however should have high current capability with little propagation delays such MICREL MIC4421 inverting drivers better. conduction losses reverse recovery losses body diodes synchronous FETs turn discussed here, they show Figure Note that drivers with high current capability shorten transition time reduce switching losses. driver losses gate charge MOSFETs should investigated thoroughly prevent over stressing. switching losses both primary secondary drivers corresponding average driver current gate charge estimated with EQs. respectively,
(EQ.
current ramp signal, which makes supply look voltage mode. reasonable small Lmag assist decrease noise sensitivity problems. Around 100uH start point telecom brick applications. addition, recommended have small transformer stabilizing magnetizing inductance that magnetizing current within controllable range. leakage inductance issue design. fact, part commutating inductance assist using stored energy. much leakage inductance however will lower effective duty cycle, resulting lower turns ratio. primary-to-secondary capacitance should minimized since robs energy from elements increasing resonant time decreasing maximum available duty cycle load range. size transformer concerned, varies with applications. reference design, transformer limited less than inch height, being able into telecom half brick.
Determine Commutating Inductance
(EQ.
where defined MOSFET datasheet.
Define Requirements Main Transformer
This section summarizes major design requirements main transformer switching frequency. turns ratio transformer derived from while defines peak current through primary winding. current through primary winding defined
Iprms Iprirms (EQ.
required external commutating inductance determined slower transition (from passive active period) since commutating inductance stores least energy ZVS. condition that energy stored commutating inductance, defined should greater than energy stored primary capacitance, defined Thus, required external commutating inductance roughly estimated with Refer detailed discussion.
Imag 2Coss (EQ.
(EQ.
current through secondary winding only half load, currents both transfer freewheeling periods defined EQs. respectively. overall current through secondary winding calculated with
Isrmstr (EQ.
Coss Imag
(EQ.
Isrmsfr
(EQ.
Note that output capacitance (Coss) MOSFET varies with drain source voltage, primary current (Ip) freewheeling period determined turns ratio current distribution factor FDIST. external commutating inductor however would better defined real circuits trial errors.
Control Loop Design
Isrms Isrmstr Isrmsfr (EQ.
magnetizing inductance (Lmag) determined number turns primary winding, core geometry, gap. Lmag however should designed low. low, high power dissipation will introduced primary switches, much ramp will added
secondary-referenced, peak current control implemented converter design. pulse transformers pass information full-bridge controller (ISL6551) high current half-bridge drivers (HIP2100s) primary. current transformer feed primary current information full-bridge controller, feed-forward loop. control loop closed error amplifier, loop compensation purpose, cascaded with
Application Note 1002
differential amplifier, remote sense purpose. Figure shows block diagram overall closed-loop system.
ISOLATION PRIMARY DRIVERS POWER STAGE OUTPUT FILTER PRIMARY SIDE HIP2100s RAMP CURRENT TRANSFORMER MIC4421s SECONDARY DRIVERS SECONDARY SIDE
ERROR AMPLIFIER
DIFFERENTIAL AMPLIFIER
REF.
FIGURE BLOCK DIAGRAM CLOSED-LOOP SYSTEM
This peak current mode controlled system simplified shown Figure setting initial feedback compensation, defines approximate openloop transfer function. factor equation that only half load sensed current transformer.
Hopen (EQ.
better representation open loop transfer function overall system defined
Hopen2 Hopen (EQ.
Refer Article another modeling loop.
Designers should initially cut-off frequency, such 1kHz, system loop with this simplified model start point then continue modify loop under stable condition with design tool such Venable System. Note that model does include slope compensation component does account subharmonic oscillation phenomenon current-mode controlled converters. high-frequency correction term given will account phenomenon [4].
-2Lo
G=2N*Ncs/Rcs
Zo(S)
ERROR AMP. [He(S)]
DIFFERENTIAL AMP. [Hd(S)]
(EQ.
FIGURE SIMPLIFIED CLOSED-LOOP MODEL
REF.
Application Note 1002
Special Notes Configuring ISL6551
controller easily configured using Table ISL6551 datasheet. this section, several things that require users' attention highlighted. detailed configuration, please refer device datasheet. tighter tolerance operating frequency, ceramic capacitor recommended resonant delay should long, otherwise, residual resonant current will flow through body diode lower additional losses generated. maximum available duty cycle will also decreased. amount slope contributed magnetizing current given while amount slope contributed internal circuit given overall slope added current ramp signal these equations. internal ramp (programmed R_RA resistor) might required ramp contributed Lmag enough slope compensation.
-Lmag (EQ.
startup, especially applications with constant current load. Hence, EANI should higher than EAO, otherwise, output voltage cannot have monotonic startup. (This problem could solved setting soft start EANI instead allowing clamping voltage come very high speed.) reference design, synchronous FETs turned during start achieving monotonic rise resistive load applications. FETs turned after certain load then cannot turned even back no-load, which achieves better dynamic performance. Users however completely remove current peak detecting circuits (D23., they only handy circuits users turned synchronous FETs whenever necessary) rely R134 C132 achieve monotonicity output voltage startup. BGREF should kept clean possible, otherwise, over current trip point PKILIM would lower than expected noise/ripple bandgap reference. 0.1uF ceramic capacitor recommended decoupling. internal race condition, ISL6551 cannot work properly without 399kW resistor connecting between BGREF pins. additional reference load more than 1mA), this pull-up resistor should scaled accordingly such that converter start properly. other words, should source least amount BGREF external load current through pull-up resistor. SHARE requires load. 0.1uF higher ceramic capacitor should connected CS_COMP design much lower current loop bandwidth than that voltage regulation loop current share operation. critical that input signal ISENSE decays zero prior during clock dead time, otherwise, could cause severe errors signal reaching comparator. Examine current ramp tail converter maximum duty cycle full load operations, extend dead time reset current ramp tail oscillations occur. peak current detecting circuits (page schematics) causes tail current ramp. removed, smaller dead time used while maintaining proper operations.
BGREF
(EQ.
voltage ISENSE should scaled appropriately such that desired peak current equals less than Vclamp-200mV-Vramp, defined addition, turns ratio current transformer, Ncs, should selected that power losses (current sense resistor) lowest line maximum output load less than power rating SMT0805 resistors that minimum losses induced less board space required.
Vclamp 200mV -Fclock -Rcs Ipripeak -Ncs (EQ.
peak current limit PKILIM lower than cycle-by-cycle current limit controlled Vclamp reference design reasons: ISENSE full load) designed greater than minimum reference voltage (2.64V) EANI pin, otherwise, monotonic output startup full load cannot achieved; high losses introduced ISENSE full load) pushed Vclamp (3.75V) with turns ratio (150:1) current transformer. reference design, ISL6550 would latch ISL6551 overload conditions. voltage EANI should designed lower than Vclamp, otherwise output will regulated Vclamp output load will limited equivalent current voltage. Since both EANI clamped same voltage (Vclamp), output voltage would current ramp exceeds during
Layout Considerations
When doing layout, users should special attention PGND returns (Analog Ground Power Ground). reference ground, return VDD, control circuits must kept clean possible from switching noises. should connected PGND only location close practical. secondary control system, should connected after output capacitors, i.e., output return pinouts. primary control system, should
Application Note 1002
connected before input capacitors, i.e., input return pinouts. Heavy copper traces should connected bias pins (VDD, VDDP1, VDDP2) ground pins (VSS PGND) heat spreading. copper routings from drivers FETs should kept short wide, especially very high frequency applications, reduce inductance traces that drive signals kept clean, bouncing. MLFP package, underneath center "floating" thermal substrate. "thermal land" design this exposed should include thermal vias that drop down connect buried copper plane(s). This combination vias vertical heat escape buried planes heat spreading allows MLFP achieve full thermal potential. recommended connect this noise copper plane Vss. additional tips, please refer "PCB Design Guidelines Reduced EMI" [5].
34.3V
33.3V LATCH RESET LATCHED LATCHED W/70ms DELAY LATCH RESET LATCH CANNOT RESET
ENABLE (PEN)
ON/OFF (START) PKILIM BGREF
ILIM_OUT (INTERNAL)
PKILIM BGREF LATCH RESET
LATSD
LATCHED
SOFT START 9.6V
8.6V
VOUT
DCOK (+/-3, FAULT GOOD
CONVERTER OVERCURRENT VOUT INPUT (VOUT 1-8.33%) BEYOND DISABLED TURN-ON WITH DELAY 1+/-8.33% THRESHOLD
MASTER (4.0V)
INPUT TURN-ON TURN-OFF TURN-OFF THRESHOLD THRESHOLD THRESHOLD
FIGURE SHUTDOWN TIMING DIAGRAM CONVERTER
Shutdown Timing Diagram Converter
INPUT (1): With biases powered mechanical switch turned converter enabled after input reaches turn-on threshold (34.3V). output voltage rises regulation point following soft start. soft start capacitor continues charged clamping voltage (Vclamp). DCOK pulled indicating "GOOD" once output reaches within point. ENABLE (2): When pulled low, soft start capacitor discharged very quickly drivers disabled. DCOK pulled high indicating "FAULT" when
output voltage discharged below point. When released, soft start initiated. OVER CURRENT (3): output converter over loaded, i.e, PKILIM above bandgap reference (BGREF), soft start capacitor discharged quickly drivers turned off. Once output voltage below -8.33% regulation point, capacitor under-voltage delay ISL6550 then charged START latched when voltage capacitor reaches ISL6551 controller quickly shut down START. over load removed converter return normal operation within under-voltage delay
Application Note 1002
(around 70mS), then START will latched. latch reset signal, which controlled input voltage, mechanical switch, thermal condition converter. latching converter overload conditions allowed, then version ISL6550 used. Then converter would running hiccup mode overload conditions. OUPUT LOCAL (4): output voltage beyond +/-8.33% point does reach master setpoint (4.19V) reason, START then latched, converter. latch reset PEN. OUPTUT MASTER (5): master circuit triggered, LATSD pulled high latches controller off. latch reset ONLY cycling VDD. CANNOT reset toggling ENABLE (PEN). RESET LATCH (6): soft start capacitor starts charged after increases above ISL6551 ISL6550 turn-on thresholds. LOCKOUT (7): turned when below ISL6551 ISL6550 turn-off thresholds. soft start reset. INPUT LOCKOUT (8): When input voltage below turn-off threshold 33.3V, converter disabled latched off. soft start reset. Summary Design Table BDAC output programming code.
TABLE BDAC OUTPUT PROGRAMMING CODE VID4 VID3 VID2 VID1 VID0 VOUT 2.642 2.674 2.706 2.738 2.770 2.801 2.833 2.865 2.897 2.929 2.961 2.993 3.025 3.057 3.089 3.121 3.153 Iindrms Iindpeak Iorms Iinrms TABLE BDAC OUTPUT PROGRAMMING CODE VID4 VID3 VID2 VID1 VID0 VOUT 3.185 3.216 3.248 3.280 3.312 3.344 3.376 3.408 3.440 3.472 3.504 3.536 3.568 3.599 3.631
Table summarizes major design parameter requirements. Most components selected designed based these values. Users should generate similar table their applications select components with derating guideline datasheet their companies.
TABLE DESIGN PARAMETER REQUIREMENTS PARAMETER CONDITION VALUE UNIT
DUTY CYCLE SWITCHING FREQUENCY Dmaxav tDEAD=200ns, tRESDLY=100ns, Fsw=250kHz CT=180pF INPUT CAPACITORS D=0.5, dVincap=1.65V Vin=48V, D~0.5, Vo=3.63V OUTPUT CAPACITORS fc=Fsw/10=23.5kHz Lo=0.8uH, Vin=75V, Vo=3.63V Vin=75V, Lo=8uH, Vo=3.63V dVtr 150mV Load Step OUTPUT INDUCTORS Lo=0.8uH, Vin=75V, Vo=3.63V Io=60A, Vin=75V, Vo=3.63V assuming load evenly distributed between both output inductors Io=60A, Vin=75V, Vo=3.63V assuming load evenly distributed between both output inductors 16.3 38.2 12.9
34.7
Application Note 1002
TABLE DESIGN PARAMETER REQUIREMENTS (Continued) PARAMETER CONDITION MAIN TRANSFORMER ELEMENTS Imag Ipripeak Iprms Isrms Nmax Lmag=60uH (Limited Core), Vo=3.63V, Vin=75V, Vo=3.63V VIN=75V, Vo=3.63V Vin=75V, Vo=3.63V Limited Core Vin=36V, Vomax=3.63V, Vmisc=0.3V, Dmaxav=0.85 CURRENT TRANSFORMER PRIMARY SWITCHES Ipriavgfr Ipriavgres Iprirms Iprirsmtr Iprirsmtr Vin=75V, Vo=3.63V Vin=36V, Vo=3.63V Vin=75V, Vo=3.63V Vin=75V, Vo=3.63V Vin=36V, Vo=3.63V Each Primary Driver Vcc(max)=13.2, Qg=50nC VGS=10V, Siliconix SUD40N1025 Vin=75V, Vd=0.78V, Vo=3.63V Vin=36V, Vd=0.75V, Vo=3.63V with Td=40n. worse case could Vin=75 switching losses SYNCHRONOUS FETs Isynpeak Isynrms Vin=75V, Vo=3.63V Vin=75V, Vo=3.63V Each Secondary Driver Vcc(max)=13.2V, Qg=30nC VGS=4.5V Four Siliconix Si4842DY Vin=75V, Four Siliconix Si4842DYs. Body Diode Conduction Recovery Losses Included Here 66.4 42.5 1.09 Copper Biases other than Drivers Guess Overall Magnetics Core (20% Conduction) Miscounted Switching Losses, Body Diodes Conduction Reverse Recovery Losses Bridge FETs Synchronous FETs, Contact Resistance, Clamping Losses, Error TOTAL 0.095 4.94 2.57 3.71 0.42 150:1 0.92 11.4 33.4 3.77 VALUE UNIT TABLE FULL LOAD POWER LOSSES ANALYSIS POWER DISSIPATION LOAD
CALCULATION CONDITIONS Clock Dead Time Resonant Time Switching Frequency Transformer Turns Ratio Magnetizing Inductance Output Inductor MOSFET Rds(on) Value PRIMARY SIDE Upper FETs Conduction Lower FETs Conduction Primary Winding Copper Current Sense Winding Pinouts Current Sense Transformer Full Bridge Drivers 2.616W 0.819w 1.023W 0.110W 1.521W 0.677W 3.371W 0.630W 1.087W 0.082W 1.141W 0.677W 4.179W 0.427W 1.155W 0.053W 0.731W 0.677W 175ns 50ns 40ns 235kHz 60uH 0.8uH Tj=500C
SECONDARY SIDE Synchronous FETs Conduction 0.90 Secondary Winding Copper Output Inductors Copper Synchronous Drivers Current Sense Resistor Current Sense Rectifiers 2.290W 1.005W 2.575W 1.805W 0.122W 0.075W OTHERS 0.656W 1.096W 0.360W 0.942W 3.914W 0.697W 1.126W 0.360W 0.973W 3.492W 0.741W 1.157W 0.360W 1.006w 5.625W 2.293W 1.054W 2.642W 1.8056W 0.095W 0.055W 2.296W 1.106W 2.716W 1.805W 0.063W 0.034W
Pupfet Plowfet
Psynfet
Table summarizes rough full load power losses analysis 3.3V output reference design.
27.33W
27.87W
31.03W
Application Note 1002 Thoughts After Design
Users these thoughts make some possible improvements reference design. input capacitors (C13-C15) replaced with ceramic capacitors with smaller footprints such SMT1812 C4532X7R2A105M. output capacitors (2220 footprint) replaced with smaller footprint 1812 capacitors such product, C4532X5R0J107M. main transformer (T2) output chokes tall brick applications with current design form factors. They integrated with save board space reduce losses. external inductance however might required operation because integrated transformer would have very leakage inductance, which could store enough energy swing primary capacitance. current sense transformer (T4) runs high pinout resistance (more than 10m) eats much space, users should redesign current sense transformer better form factor (like J-lead) thermal performance. addition, cannot placed symmetrically board space constraint. applications space limitation, should relocated. overall layout improved removing test point connectors (TP1-TR34), which required real design. peak current limit PKILIM lower than cycle-by-cycle current limit controlled Vclamp, i.e., PKILIM triggered earlier than cycle-by-cycle limit.Thus, reference-based clamp circuit, cycle-by-cycle current limit accuracy, necessary. Users completely remove current peak detecting circuits (D23, C61., they only handy circuits users turned synchronous FETs whenever necessary) rely R134 C132 achieve monotonicity output voltage startup. dead time then down. replaced with wire users look primary current. ideal zero Ohm, couple milliOhms could induce 0.2% higher less efficiency. narrower range input (48V+/-10%) and/or lower output voltage application, higher turns ratio (4:1) improve efficiency much through body diodes upper FETs shortest period. power dissipation upper FETs therefore reduced significantly high primary current applications. narrower input line range higher turns ratio main transformer chosen, higher efficiency achieved. power losses cost pre-regulator however should taken into account overall performance evaluation. external commutating inductor added series with primary side transformer assist transitions energy stored leakage inductance magnetizing inductance less than energy stored output capacitance (2*Coss) power switches, primary capacitance (Cp), external capacitance. Extending range with external inductor penalties additional component cost less effective duty cycle resulting lower turns ratio, which adds power losses primary side. external capacitor parallel with primary side transformer help lower dV/dt noise level without introducing additional losses when zerovoltage switching still retained. penalties, discussed above, still hold. External high current bridge drivers cascading with ISL6551 drivers help absorb power that supposed dissipate controller that controller over stressed high gate capacitive load applications, which extends application range much higher power level. higher switching frequency higher system closed-loop bandwidth realized, lower input output capacitances required overcoming load transients. This, however, comes cost efficiency. current ramp signal ISENSE should decay zero prior during clock dead time. Hence, dead time should long enough reset trailing-edge tail current ramp maximum duty cycle operation, otherwise, oscillations could occur. leakage inductance pulse transformers would induce propagation delay depending drive current through higher energy through pulse transformer longer delay would save board space, silk screen text deleted, some brick manufacturers today. initial design, SOD123 diode (such MBR0530T1) series with VDDP pins protect ISL6551 from being damaged reverse biasing, especially design with package, which cannot replaced easily. design, diode substituted with zero resistor. high current density multi-layer design, buried vias used save space, cost added. current share support paralleling operation redundancy. When used redundant systems, requires OR'ing circuit inserting between converter common output bus.
Design Tips Using ISL6551
Since upper FETs carry only active currents through their channels also freewheeling currents through their body diodes, power dissipation upper FETs higher than lower FETs QB), which replaced with smaller size MOSFETs such SO-8 moderate primary current applications. switching losses however should taken into account. With assistance pre-regulator, post full-bridge regulator designed operate fixed maximum duty cycle (~100%). Thus, freewheeling currents flow
Application Note 1002 Debugging TIPS
This section discusses some easy ways bring power train least amount time. transformer current ramp signal that into ISL6551. asymmetric behaviors should seen percent load good start point. converter stable, ceramic capacitor (say 0.1uF) feedback network down cut-off frequency until converter becomes stable. simplified model Figure design cut-off frequency system loop. Later, optimize loop with tool. Enable synchronous drivers. timing properly, shoot-through currents between secondary winding synchronous FETs would induced affect converter's performance, especially light load conditions. Start with some load (10% rated load) work backward. Check current ramp signal ISENSE ISL6551 longer blanking time required. Tune Design proper resonant delay programming R_RESDLY resistor changing possible) elements such magnetizing inductance, leakage inductance, external commutating inductor, output capacitance bridge FETs, external primary capacitance. Note that loop that used measure primary current induce additional commutating inductance, depending upon enclosed area, extends load range. instance, 5.0" 14AWG wire contribute much 80nH inductance.
Before/After Build
Before building board, wise check magnetics components such current transformer, main transformer, output inductors, input inductor, commutating inductor designed properly using magnetics design tools waveforms across magnetics method. addition, components, especially power train components, should checked their power/thermal derating guidelines met. After build, check placed properly.
Apply Biases with Current Voltage Limiting
Before applying input voltage converter, quick check control circuits always first step. Table page ISL6551 datasheet design checklist. Disable anything that prevents both ISL6551 ISL6550 from free running. reference design, disconnecting resistor (R6) between START ISL6550 ON/OFF ISL6551 will allow both chips free running. series forward diodes with bias lines that will damaged reverse biasing. reference design built-in diodes. Apply biases with current limiting. Check both voltage levels each ISL6550 pinout correct. noises over stressed. Check both voltage levels each ISL6551 pinout correct. noises over stressed. Check nice sawtooth equal pulse width between upper drive signals. Check both voltage levels drive signals bridge FETs synchronous FETs correct. noises over stressed. Check delays such Dead Time, Resonant Delay, Delay designed properly. Check timing synchronous signals designed properly. shoot through.
Experimental Results
evaluation board intended test ISL6551 200W half brick form factor. specification this converter summarized this paper. Most converter circuitries placed central 2.50"x2.45" area limited within 0.5" height, unnecessary components such test point connectors Input/Output connectors placed beyond center.This DC/DC converter accepts wide range input, 75V, generates wide range output, 2.64V 3.63V with 31.918mV step full load. ultra high efficiency, efficiency 3.3V fully loaded output, been achieved. following sections, some critical aspects converter examined with detailed experimental data.
Drive Signal Timing
drive signals taken when ISL6551 free running, which done removing input line that connects START ISL6550. resonant delay turn lower switch after corresponding upper switch turned off, shown Figure helps achieve zero-voltage switching (ZVS). dead time turn upper after corresponding lower switch turned off, shown Figure helps eliminate shoot-through currents through primary switches during switching transitions. Figures show resonant delay dead time ISL6551 prior processed through pulse transformers andT5) bridge drivers (Intersil HIP2100).
Power Slowly with Current Voltage Limiting
possible, disconnect secondary winding from secondary side, then increase input voltage slowly. primary timing until (very low) current drawn from input line. check magnetizing current proper level. Connect secondary winding back circuit disable synchronous drivers such that current conducts only through body diodes synchronous FETs. Increase input voltage slowly with input output current limiting monitor current through main
Application Note 1002
dead time resonant delay, with turn-on threshold primary switches, converter summarized Table real delays primary switches shorter than "delays" ISL6551 long propagation delays falling edges both upper lower drive signals. Furthermore, leakage inductances pulse transformers also would induce additional propagation delays depending drive current through higher energy through pulse transformer longer delay would
TABLE RESONANT DELAY DEAD TIME DELAY Resonant Delay Dead Time SWITCH'S GATE ISL6551 FIGURE RESONANT DELAY ISL6551. CHANNEL LOWER DRIVE SIGNAL; CHANNEL UPPER DRIVE SIGNALS
FIGURE RESONANT DELAY LOWER FET. CHANNEL LOWER DRIVE SIGNAL; CHANNEL UPPER DRIVE SIGNALS FIGURE DEAD TIME ISL6551. CHANNEL LOWER DRIVE SIGNAL; CHANNEL UPPER DRIVE SIGNALS
FIGURE DEAD TIME LOWER FET. CHANNEL LOWER DRIVE SIGNAL; CHANNEL UPPER DRIVE SIGNALS
synchronous drive signals inverting version both lower drive signals with little propagation delays. turn-on gate resistors, R33, soften rising edge lower drive signals, while diodes, D19, reduce their falling edge delay. Meanwhile, diodes, minimize turn-off delay synchronous drive signals, while resistors, R18, increase their turnon delay. shown Figure synchronous turned off/on (Channel whenever corresponding lower switch turned on/off (Channel There overlap between these drive signals. Hence, shoot-through currents between secondary winding synchronous FETs eliminated.
Application Note 1002
Figure shows operation waveforms INV_SYNC DRIVE scheme. Since only synchronous turned conducts currents during freewheeling period, freewheeling current reflected primary higher than that INV_LOW DRIVE scheme. Hence, INV_LOW DRIVE scheme produces much higher efficiency than INV-SYNC DRIVE scheme.
FIGURE SYNCHRONOUS DRIVE SIGNAL. CHANNEL LOWER DRIVE SIGNAL ISL6551; CHANNEL SYNCHRONOUS DRIVE SIGNAL; CHANNEL LOWER DRIVE SIGNAL LOWER
Switching Waveforms
WINDING VOLTAGE CURRENT Figures show voltage waveforms across transformer primary currents through Note that replaced with 5.0" 14AWG wire that primary current measured this loop, which should shorted when determining load range. delay between primary voltage secondary voltage leading edge, shown Figures caused leakage inductance transformer. input voltage applied first across leakage inductor resetting current, voltage across real primary secondary must stay zero until current through leakage inductor changes direction reaches value reflected load. higher load results larger stored energy leakage inductor that needs reset before going into active mode, longer delay There almost delay zero load operation, shown Figure shown Figure with synchronous FETs turned converter still runs continuous mode (CCM) with large duty cycle even no-load operation. Figure shows operation waveforms with synchronous FETs off. this case, synchronous FETs block negative current, which forces converter discontinuous mode (DCM) cutting down duty cycle significantly.
FIGURE TRANSFORMER WAVEFORMS VIN=48V, VOUT=3.3V, IOUT=60A. CHANNEL PRIMARY CURRENT (IP); CHANNEL PRIMARY VOLTAGE (VP); CHANNEL SECONDARY VOLTAGE (VS)
FIGURE TRANSFORMER WAVEFORMS VIN=48V, VOUT=3.3V, IOUT=30A. CHANNEL PRIMARY CURRENT (IP); CHANNEL PRIMARY VOLTAGE (VP); CHANNEL SECONDARY VOLTAGE (VS)
Application Note 1002
TRANSITIONS
FIGURE TRANSFORMER WAVEFORMS VIN=48V, VOUT=3.3V, IOUT=0A (SYN ON). CHANNEL PRIMARY CURRENT (IP); CHANNEL PRIMARY VOLTAGE (VP); CHANNEL SECONDARY VOLTAGE (VS)
Figures show resonant transitions lower various situations, they taken shortening loop that used measure primary current. Table summarizes conditions converter various input output voltages (which apply every converter since conditions each converter heavily dependant upon leakage inductance output capacitance primary switches). nominal input 3.3V output condition, converter loses transitions below full load, shown Figure line (36V) situation, transitions extend full load, shown Figure since energy stored parasitic capacitance proportional VIN2 reaches minimum. other hand, high line (75V) completely loses transitions even 100% load since energy stored parasitic capacitance reaches maximum energy commutating inductance enough resonate tank valley, shown Figure
TABLE LOAD RANGE VIN\VOUT 2.64V <50% <75% >100% 3.30V <42% <62% >100% 3.63V <33% <58% <92%
FIGURE TRANSFORMER WAVEFORMS VIN=48V, VOUT=3.3V, IOUT=0.5A (SYN OFF). CHANNEL PRIMARY CURRENT (IP); CHANNEL PRIMARY VOLTAGE (VP); CHANNEL SECONDARY VOLTAGE (VS)
FIGURE RESONANT TRANSITION VIN=48V, VOUT=3.3V, IOUT=60A. CHANNEL VOLTAGE LOWER FET; CHANNEL LOWER GATE DRIVE SIGNAL
FIGURE TRANSFORMER WAVEFORMS VIN=48V, VOUT=3.3V, IOUT=60A (INV_SYNC DRIVE SCHEME). CHANNEL PRIMARY CURRENT (IP); CHANNEL PRIMARY VOLTAGE (VP); CHANNEL SECONDARY VOLTAGE (VS)
Application Note 1002
FIGURE RESONANT TRANSITION VIN=48V, VOUT=3.3V, IOUT=37A. CHANNEL VOLTAGE LOWER FET; CHANNEL LOWER GATE DRIVE SIGNAL
FIGURE RESONANT TRANSITION (LOST) VIN=75V, VOUT=3.3V, IOUT=60A. CHANNEL VOLTAGE LOWER FET; CHANNEL LOWER GATE DRIVE SIGNAL
FIGURE RESONANT TRANSITION (LOST) VIN=48V, VOUT=3.3V, IOUT=0A. CHANNEL VOLTAGE LOWER FET; CHANNEL LOWER GATE DRIVE SIGNAL
FIGURE VIN=48V, VOUT=3.3V, IOUT=60A. CHANNEL VOLTAGE FET; CHANNEL SYNCHRONOUS GATE DRIVE SIGNAL
FIGURE RESONANT TRANSITION VIN=36V, VOUT=3.3V, IOUT=25A. CHANNEL VOLTAGE LOWER FET; CHANNEL LOWER GATE DRIVE SIGNAL
FIGURE VIN=48V, VOUT=3.3V, IOUT=0A. CHANNEL VOLTAGE FET; CHANNEL SYNCHRONOUS GATE DRIVE SIGNAL
Application Note 1002
shown Figures synchronous FETs zero-voltage switching turn have negligible switching losses turn during light load. Nevertheless, bumps, shown Figure caused body diode conduction and/or reverse recovery turn off, which induce losses.
Shutdown Timing (Shorted Circuit,
OUTPUT SHORTED CIRCUIT When output shorted, START (channel latched after UVDLY (channel capacitor (C26) charged above threshold shown Figure Note that additional delay induced probe ISL6550 UVDLY pin. short removed output voltage returns normal level before under-voltage delay, around 70ms, time out, then START would latched.
FIGURE OUTPUT UNDER-VOLTAGE DELAY. CHANNEL UVDLY; CHANNEL START SIGNAL; CHANNEL OUTPUT VOLTAGE
FIGURE OUTPUT SHORTED CIRCUIT. CHANNEL OUTPUT VOLTAGE; CHANNEL START SIGNAL; CHANNEL UVDLY ISL6550; CHANNEL OUTPUT CURRENT
FIGURE OUTPUT UNDER-VOLTAGE DELAY. CHANNEL UVDLY; CHANNEL START SIGNAL; CHANNEL OUTPUT VOLTAGE
OUTPUT UNDER-VOLTAGE DELAY shown Figure output voltage (Channel huge dip, returns normal level before undervoltage delay time out, hence, START (channel pulled low. Figure shows that UVDLY starts rise when output voltage below under-voltage threshold, START latched when UVDLY reaches threshold.
OUTPUT OVER-VOLTAGE When pulled ground, error voltage jumps causes over voltage output (channel START (Channel latched, shown Figure LATSD (Channel triggered since output voltage does exceed master over-voltage setpoint. With quick touch output zero load) with voltage source, both local master over-voltage setpoints violated. Figure shows that START triggered lower voltage level than LATSD. START nominally latched around 108.33% output voltage, while LATSD latched higher fixed voltage, around 4.19V above maximum BDAC output voltage. master over-voltage monitoring circuit designed with bandgap reference ISL6551, rather than ISL6550 internal reference that used local over-voltage setpoint, about 108.33% BDAC voltage. Thus, converter gain additional protection against failure ISL6550 internal reference mis-configuration
Application Note 1002
ISL6550. instance, when somehow shorted debris solder, output voltage would programmed (the reference ISL6550) local over-voltage setpoint also moved relative output voltage level. such situation, master overvoltage circuit will over-ride local over-voltage setpoint whenever greater than 4.19V protect processor load from being over-stressed.
Efficiency Curves
Figures show efficiency curves different output voltages, data taken around airflow with PAPST-MOTOREN 4600 fan. Each figure illustrates that lower input line higher efficiencies which converter operates. This mainly because higher input line lower duty cycle higher conduction switching losses primary switches are. Note that input output voltages measured TP10 TP5, respectively. Figure shows full-load efficiencies converter various input lines. Each curve shows that higher output voltage higher efficiency same reasons, mentioned above.
FIGURE OVER VOLTAGE (VOUT=3.6V). CHANNEL OUTPUT VOLTAGE; CHANNEL LATSD SIGNAL; CHANNEL START SIGNAL
Efficiency
Iout
FIGURE EFFICIENCY CURVES VOUT=2.64V@~400
FIGURE OVER VOLTAGE (VOUT=3.63V). CHANNEL OUTPUT VOLTAGE; CHANNEL LATSD SIGNAL; CHANNEL START SIGNAL
Efficiency
Iout
FIGURE EFFICIENCY CURVES VOUT=3.3V @~400
Application Note 1002
Figure shows case temperature lower (Q17). higher input voltage higher switching losses lower are. high line, case temperature rises significantly since transitions completely lost switching losses dominate channel conduction losses. Figure shows case temperature current sense transformer (T4). line, case temperature much higher since current ramp through current sense transformer larger duty cycle produces higher value higher resistive losses. Figures Figure show case temperature main transformer (T2) synchronous (Q1), respectively. Figure shows synchronous driver (M2) case temperature. curves this figure look flatter than those other figures since driver losses heavily depend gate charge synchronous FETs (which remains almost constant), rather than output load. Figure shows case temperature output inductor (L2). high line, inductor gets hotter since ripple current well value higher.
Efficiency
Iout
FIGURE EFFICIENCY CURVES VOUT=3.64V @~400
Efficiency
data points Figures Figure taken various output full load operating conditions with around airflow. shown these figures, worst operating point high line maximum output voltage cases except current sense transformer (T4), which worst operating point line maximum output voltage.
Vout
Case Temperature
Output Load
FIGURE UPPER (Q14) CASE TEMPERATURE
FIGURE EFFICIENCY DIFFERENT VOUT @~400
THERMAL DATA thermal data taken with Fluke 80T-IR Infrared Temperature Probe 210C ambient temperature while PAPST-MOTOREN 4600 (estimated around more) placed vertically 2.0" away from input converter. data used only relative comparison purpose, therefore, users should thermal derating based these thermal curves because data points necessarily presenting absolute values operating condition. data points Figures taken VOUT=3.3V. Figure shows upper (Q14) case temperature. higher input voltage longer freewheeling period therefore, higher conduction losses upper Thus, case temperature higher high line.
Application Note 1002
Output Load
Case Temperature
Case Temperature
Output Load
FIGURE LOWER (Q17) CASE TEMPERATURE
FIGURE SYNCHRONOUS (Q1) CASE TEMPERATURE
Output Load
Case Temperature
Output Load
Case Temperature
FIGURE CURRENT TRANSFORMER (T4) CASE TEMPERATURE
FIGURE SYNCHRONOUS DRIVER (M2) CASE TEMPERATURE
Output Load
Case Temperature
Case Temperature
Output Load
FIGURE OUTPUT INDUCTOR (L2) CASE TEMPERATURE
FIGURE MAIN TRANSFORMER (T2) CASE TEMPERATURE
Application Note 1002
Case Temperature
2.64V
Case Temperature
2.64V 3.3V 3.63V
3.3V 3.63V
Input Voltage
Input Voltage
FIGURE UPPER (Q14) CASE TEMPERATURE
FIGURE MAIN TRANSFORMER (T2) CASE TEMPERATURE
Case Temperature
2.64V
Case Temperature
2.64V 3.3V
3.3V 3.63V
3.63V
Input Voltage
FIGURE LOWER (Q17) CASE TEMPERATURE
Input Voltage
FIGURE SYNCHRONOUS (Q1) CASE TEMPERATURE
Input Voltage
Case Temperature
Case Temperature
2.64V 3.3V 3.63V
2.64V 3.3V 3.63V
Input Voltage
FIGURE CURRENT TRANSFORMER (T4) CASE TEMPERATURE
FIGURE SYNCHRONOUS DRIVERS (M2) CASE TEMPERATURE
Application Note 1002
Current Share Slave Master)
48V-3.3V 75V-2.64V 36V-3.63V
Case Temperature
2.64V 3.3V
3.63V
Input Voltage
FIGURE OUTPUT INDUCTOR (L2) CASE TEMPERATURE
Load Current
FIGURE CURRENT SHARE CURVES
Current Maste Slave Unit
shown figures above, current transformer main transformer hottest components. Without airflow, their case temperatures would rise significantly exceed device ratings heavy load operations. Users should more thorough analysis worst case operating condition evaluate thermal stress each device. current transformer roughly measured above 130°C room ambient temperature, input 3.3V, output without airflow heavy glossy pinout, recommended that users redesign current sense transformer better form factor thermal performance.
48V-3.3VM 48V-3.3VS 75V-2.64VM 75V-2.64VS 36V-3.63VM 36V-3.63VS
Current Share
equal length inch) size AWG) wires split load into each individual converter, thus, impedance mismatching current-carrying traces from converters load minimized. current delivered each converter measured with only current probe reduce measurement error. With this kind setup measurement method, impedance difference measurement error still greater than that building both converters board with symmetric layout measuring current with precise current sense resistors. measurement error increases with decreasing load. Figure shows current share curves various input lines output voltages. current sharing inversely proportional load, slave unit share load within master unit full load operation. Since offset error amplifier difference output reference well difference power train components between both units remains constant, difference load currents delivered master slave units almost remains constant, shown Figure addition, no-load operation, master unit will source current into slave units because higher voltage (master) back drives lower voltage (slave).
Load Current
FIGURE CURRENT MASTER SLAVE UNIT
FIGURE TURN SLAVE (CHANNEL CHANNEL FIRST. MASTER: CHANNEL CHANNEL
Application Note 1002
FIGURE TURN MASTER (CHANNEL CHANNEL FIRST. SLAVE: CHANNEL CHANNEL
FIGURE TRANSIENT RESPONSE VIN=75V VOUT 2.64V 0A-15A STEP, 1A/us
Figures Figure show interaction between master slave units different turn-on sequences. When slave unit turned first, acts "master" during start master unit. takes longer time both converters switch back their proper roles settling down than that master unit turned first.
Step Responses
This section summarizes step responses converter various input lines output voltages (Figures 69). figures this section, Channel represents load step, channel represents output voltage. transients from 60A, channel shows only load. Table summarizes transient voltage spikes different operating conditions. Note that measurement including ripple voltage. actual transient voltages excluding ripple voltage should smaller very different cases since cut-off frequency corresponding phase loop cases very close, illustrated Loop Response section.
TABLE TRANSIENT RESPONSE INPUT OUTPUT 2.64V 2.64V 3.30V 3.30V 3.63V 3.63V LOAD STEP 0-15A, 1A/us 45-60A, 1A/us 0-15A, 1A/us 45-60A, 1A/us 0-15A, 1A/us 45-60, 1A/us TRANSIENT Vp-p 353mV 350mV 328mV 319mV 316mV 306mV Vp-p 177mV 175mV 164mV 160mV 158mV 153mV
FIGURE TRANSIENT RESPONSE VIN=75V VOUT 2.64V 45A-60A STEP, 1A/us
FIGURE TRANSIENT RESPONSE VIN=48V VOUT 3.3V 0A-15A STEP, 1A/us
Application Note 1002
Loop Response
experimental results presented this section measured with Venable system. injection point R131 instead since located noise sensitivity nodes. Since current mode control system, transfer function plant mainly determined characteristic load including output resistive, capacitive, inductive impedance, which varies with different applications. only five "pure" resistive loads available testing lab. load constructed with these five resistors 3.3V output. shown Figure load characterized 0.086 resistor series with inductance induced 5.0" 10AWG wires that connect load. open loop response slightly varies with input voltage, shown Figure
FIGURE TRANSIENT RESPONSE VIN=48V VOUT 3.3V 45A-60A STEP, 1A/us
Gain (dB) Phase (Degrees)
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
Measured Gain Measured Phase Model Gain Model Phase
(Hz)
FIGURE TRANSIENT RESPONSE VIN=36V VOUT 3.63V 0A-15A STEP, 1A/us
FIGURE RESISTIVE LOAD CHARACTERISTIC
PHASE
GAIN
FIGURE TRANSIENT RESPONSE VIN=36V VOUT 3.63V 45A-60A STEP, 1A/us
FIGURE OPEN LOOP RESPONSE 3.3V@38A RESISTIVE LOAD. RED-48V, BLUE-75V, BLACK-36V
Application Note 1002
GAIN
PHASE
FIGURE PLANT FREQUENCY RESPONSE 3.3V@38A RESISTIVE LOAD. RED-48V, BLUE-75V, BLACK-36V
FIGURE PLANT RESPONSE THREE KINDS LOADS 48V, 3.3V@38A. RED(1)-"PURE" RESISTIVE LOAD, BLUE(2)-ELECTRONIC CONSTANT CURRENT LOAD, BLACK(3)ELECTRONIC RESISTIVE LOAD.
AREA INTEREST
FIGURE FREQUENCY RESPONSE PLANT (Vo/Ve), FEEDBACK COMPENSATION, DIFFERENTIAL AMPLIFIER, OPEN LOOP VIN=48V, VOUT=3.3V@38A RESISTIVE LOAD. RED-GAIN BLUE-PHASE
FIGURE OPEN LOOP RESPONSE THREE KINDS LOADS 48V, 3.3V@38A. RED-"PURE" RESISTIVE LOAD, BLUE-ELECTRONIC CONSTANT CURRENT LOAD, BLACKELECTRONIC RESISTIVE LOAD
Figure shows three portions system loop 3.3V resistive loaded output: Plant (Vo/Ve), Feedback compensation, Differential amplifier. overall loop these components, which feedback compensation differential amplifier fixed elements plant variable depending load. Figure shows loop responses three different types loads: "pure" resistive load, electronic constant current load, electronic resistive load. responses vary significantly frequencies, frequencies interest that define phase margin gain margin shift little high frequencies, therefore, system stability studied just looking loop response against constant current load.
Figures show loop responses various input output conditions including four corners. concluded that system stable under input output operating conditions since 20-30kHz loop bandwidth, around 10dB gain margin, above phase margin. thing that should noted that tail gain, caused output capacitors, above 200kHz increases with frequency. still exists causes problem real system, users lower pole differential amplifier stage smooth (say 100pF both C28). gain feedback compensation however should adjusted, necessary, design favorable gain margin phase margin system.
Application Note 1002
FIGURE OPEN LOOP RESPONSE 2.64V@60A CONSTANT CURRENT LOAD. RED-48V, BLUE75V, BLACK-36V
FIGURE OPEN LOOP RESPONSE 2.64V CONSTANT CURRENT LOAD. RED-48V, BLUE-75V, BLACK-36V
FIGURE OPEN LOOP RESPONSE 3.3V@60A CONSTANT CURRENT LOAD. RED-48V, BLUE75V, BLACK-36V
FIGURE OPEN LOOP RESPONSE 3.3V@6A CONSTANT CURRENT LOAD. RED-48V, BLUE-75V, BLACK-36V
FIGURE OPEN LOOP RESPONSE 3.64V@60A CONSTANT CURRENT LOAD. RED-48V, BLUE-75V, BLACK-36V
FIGURE OPEN LOOP RESPONSE 3.64V@6A CONSTANT CURRENT LOAD. RED-48V, BLUE75V, BLACK-36V
Application Note 1002
addition above loop measurement, following presents some modeling results using simplified loop system including high-frequency correlation term discussed Control Loop Design section page feedback compensation differential amplifier stages verified with Venable System, shown Figures They well matched with theoretical results except that phase differential amplifier stage smaller above 100kHz than expected. addition, each TAIYO YUDEN capacitor characterized with 100uF capacitance series with 1.8m defined which also verified with Venable System.
Zcap 1.8x10 j6x10 j100x10 (EQ.
-100 -120 -140 -160 -180 1.0E+02
Gain (dB) Phase (Degrees)
Measured Gain Measured Phase Model Gain Model Phase
1.0E+03 1.0E+04 1.0E+05 1.0E+06
Frequency (Hz) (Hz) FIGURE OUTPUT CAPACITOR MODELING
Thus, only variable plant, i.e., load power train.
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 Fequency (Hz) Frequency (Hz)
FIGURE COMPENSATION STAGE
1.0E+02
Measured Gain Measured Phase Model Gain Model Phase
Gain Measured Phase Model Gain Model 1.0E+0 1.0E+0 1.0E+0 1.0E+0 1.0E+0 Phase Frequency (Hz) Frequency (Hz)
Measured
Gain (dB) Phase (Degrees)
Gain (dB) Phase (Degrees)
FIGURE OUTPUT LOAD
Gain (dB) Phase (Degrees)
Gain (dB) Phase (Degrees)
-100 -120 -140 -160 -180 -200 -220 -240 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
Measured Gain Measured Phase Model Gain Model Phase
1.0E+03 1.0E+04 1.0E+05 1.0E+06
Measured Gain Measured Phase Model Gain Model Phase
Frequency (Hz) Fequency (Hz) FIGURE DIFFERENTIAL STAGE
Frequency (Hz) Fequency (Hz)
FIGURE PLANT RESPONSE "PURE" RESISTIVE LOAD
Application Note 1002
Measured Gain (60A) Measured Phase (60A) Measured Gain (6A) Measured Phase (6A) Model Gain (60A) Model Phase (60A) Model Gain (6A) Model Phase (6A)
Gain (dB) Phase (Degrees)
Gain (dB) Phase (Degrees)
-100 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
Measured Gain Measured Phase Model Gain Model Phase
AREA INTEREST
-100 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
Fequency (Hz)
FIGURE LOOP RESPONSE "PURE" RESISTIVE LOAD
Fequency (Hz)
FIGURE LOOP RESPONSE 75V, 2.64V@6A
Output Voltage
measured loop plant responses input 3.3V output with resistive load, which characterized Figure have reasonable match with that simplified model, shown Figure loop response overall "pure" resistive load conditions tested. Instead, electronic constant current load used. results significantly from that "pure" resistive load within frequencies interest, shown Figure Figures Figure show good prediction phase margin gain margin system using simplified model overall operating conditions. OUTPUT RIPPLE VOLTAGE output ripple voltage different operating conditions greater than 60mV, summarized Table results show that output largest output ripple voltage highest input line highest output voltage since highest output ripple current this operating point. Note that ripple current table discontinuous mode. Figure shows converter operating burst mode very light load. Figure show converter operates 48V, 3.3V, 0.5A load with synchronous FETs turned respectively. with synchronous FETs turned larger duty cycle than with synchronous FETs turned off, which runs discontinuous mode since body diodes turnedoff FETs block output inductor current from flowing negatively. Note that channel represents output ripple voltage channel represents voltage across secondary winding.
TABLE OUTPUT VOLTAGE RIPPLE VOUT 3.63V 3.31V 2.64V 3.63V 0.5A 21.9mV 25.0mV 56.2mV 59.4mV 0.5A 25.0mV 28.1mV 37.5mV 46.9mV LOAD 32.8mv 34.4mV 48.4mV 59.4mV RIPPLE CURRENT 5.4A 9.0A 10.8A 12.9A
Gain (60A) Phas (60A) Gain (6A) Phas (6A) Gain (60A) Phas (60A) Gain (6A) Phas (6A)
Gain (dB) Phase (Degrees)
-100 -120 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06
AREA INTEREST
Fequency
FIGURE LOOP RESPONSE 36V, 3.63V@6A
Application Note 1002
FIGURE OUTPUT VOLTAGE RIPPLE (CHANNEL VIN=75V, VOUT=3.63V, IOUT=0.5A.
FIGURE OUTPUT VOLTAGE RIPPLE (CHANNEL VIN=48V, VOUT=3.3V, IOUT=0.5A.
FIGURE OUTPUT VOLTAGE RIPPLE (CHANNEL VIN=75V, VOUT=3.63V, IOUT=0.5A.
FIGURE OUTPUT VOLTAGE RIPPLE (CHANNEL VIN=48V, VOUT=3.3V, IOUT=0.5A.
FIGURE OUTPUT VOLTAGE RIPPLE (CHANNEL VIN=75V, VOUT=3.63V, IOUT=60A
FIGURE OUTPUT VOLTAGE RIPPLE (CHANNEL VIN=48V, VOUT=3.3V, IOUT=60A
Application Note 1002
Output Start
start characteristic output voltage heavily depends load. "pure" resistive load electronic load with slew rate (0.01A/us), output voltage comes smoothly, shown Figures case high slew rate electronic load, monotonicity output voltage lost, shown Figures During startup, load demands more current than what converter deliver, which causes output dipping. higher load higher current ramp needed, higher error voltage required push duty cycle further. error voltage limited soft start voltage (Vclamp) that comes with slower speed, therefore, duty cycle limited causing repetitive up/downs output voltage, shown Figure 100. applications with similar behavior electronic load, this problem resolved speeding startup soft start with possible options: increase soft start speed above start-up speed error voltage reducing capacitive load ISL6551; soft start output reference (EANI) completely remove capacitive load pin. general, second option practical one. Note that delay electronic load caused turn-on threshold.
FIGURE OUTPUT VOLTAGE (CHANNEL VIN=75V, VOUT=2.64V, IOUT=60A, 0.01A/US ELECTRONIC CONSTANT CURRENT MODE (CHANNEL LOAD)
FIGURE OUTPUT VOLTAGE (CHANNEL VIN=75V, VOUT=2.64V, IOUT=60A, 1A/US ELECTRONIC RESISTIVE MODE (CHANNEL LOAD)
FIGURE OUTPUT VOLTAGE (CHANNEL VIN=48V, VOUT=3.3V, 0.083 RESISTIVE LOAD
FIGURE OUTPUT VOLTAGE (CHANNEL VIN=48V, VOUT=2.64V, IOUT=60A, 1A/US ELECTRONIC CONSTANT CURRENT MODE. CHANNEL ERROR VOLTAGE; CHANNEL VCLAMP VOLTAGE; CHANNEL CURRENT RAMP (ISENSE). EACH CHANNEL 1V/DIV 2MS/DIV.
Application Note 1002
FIGURE 100. OUTPUT VOLTAGE STARTUP EXPANSION (CHANNEL VIN=48V, VOUT=2.64V, IOUT=60A, 1A/US ELECTRONIC CONSTANT CURRENT MODE. CHANNEL ERROR VOLTAGE; CHANNEL VCLAMP VOLTAGE; CHANNEL CURRENT RAMP (ISENSE). 100US/DIV.
FIGURE 101. VIN=48V, VOUT=3.3V, IOUT=60A ELECTRONIC LOAD WITH ADDITIONAL CAP. CHANNEL OUTPUT VOLTAGE; CHANNEL SYNCHRONOUS GATE SIGNAL; CHANNEL OUTPUT CURRENT
Output Turned Characteristic
When converter turned operator fault, energy stored output inductors capacitors dissipated parasitic resistance output inductors capacitors, load, synchronous FETs. Figure 101, output current lags from output voltage, which means that output load (electronic load) behaves inductively when converter turned off. Note that electronic load activated until input above 0.95V. delay turn synchronous FETs induced peak current detecting circuit page schematics, which allows negative currents through Channels during this period. Since electronic load does behave resistively losses Rds(on) synchronous FETs relatively small, output resonant tank cannot heavily dampened, which causes output ringing down undesired negative voltage (-2V). With 1000uF Aluminum capacitor output, resonant frequency decreases stored energy increases; however, negative spike does down small amount, shown Figure 102. With assistance additional output capacitance additional circuits, shown page schematics (D131.), turn synchronous FETs fault operator, negative spike reduced acceptable level (200mV), shown Figure 104. Note that 1000uF Aluminum capacitor output necessary help reduce negative spike controllable level.
FIGURE 102. VIN=48V, VOUT=3.3V, IOUT=60A ELECTRONIC LOAD WITH 1000uF ALUMINUM CAPACITOR. CHANNEL OUTPUT VOLTAGE; CHANNEL SYNCHRONOUS GATE SIGNAL; CHANNEL OUTPUT CURRENT
FIGURE 103. VIN=48V, VOUT=3.3V, IOUT=60 ELECTRONIC LOAD WITH ADDITIONAL CAP. CHANNEL OUTPUT VOLTAGE; CHANNEL SYNCHRONOUS GATE SIGNAL; CHANNEL OUTPUT CURRENT
Application Note 1002
shown Figure 105, output voltage output current phase since load resistive (two DALE NH-25 0.1W parallel, they operate only short period their power ratings). negative spike much smaller than that previous case because load helps dissipate some residual energy. When synchronous FETs turned shutdown converter, body diodes synchronous FETs help dissipate large portion energy block negative current through output inductors resulting zero negative spike, shown Figure 106. this case, extra capacitor required.
Equipment List
FIGURE 104. VIN=48V, VOUT=3.3V, IOUT=60A ELECTRONIC LOAD WITH 1000UF ALUMINUM CAPACITOR. CHANNEL OUTPUT VOLTAGE; CHANNEL SYNCHRONOUS GATE SIGNAL; CHANNEL OUTPUT CURRENT TABLE EQUIPMENT LIST EQUIPMENT Boards Used Power Supplies EQUIPMENT DESCRIPTIONS ISl6551EVAL1 Rev. 6653A S/N: 3621A-03425 Lamda LQ521 S/N: 3570 XANTREX 100-10 S/N: 72963 XANTREX 100-6 S/N: 66287 HP6205C S/N: 2411A-06136 LeCroy LT364L S/N: 01106 Hewlett Packard HP1141A Fluke 8050A S/N: 2466115 3200834 Chroma 63103 S/N: 631030002967 Chroma 63103 S/N: 631030003051 Four DALE NH-25 LeCroy AP015 970139 Fluke 80T-IR Infrared Temperature Probe (93/09) POPST-MOOREN 4600X (4098547)
Oscilloscope Differential Probe Multimeters Load
Current Probe Amplifier Temperature Probe FIGURE 105. VIN=48V, VOUT=3.3V, IOUT=60A PURE RESISTIVE LOAD WITH ADDITIONAL CAP. CHANNEL OUTPUT VOLTAGE; CHANNEL SYNCHRONOUS GATE SIGNAL; CHANNEL OUTPUT CURRENT
Schematics Description
There pages schematics. first page secondary side power train including output filter synchronous rectifiers with their drivers. Additional circuits used turn synchronous FETs during start clamp ringings across FETs leading edge. page primary power train. consists input filter, current transformer, main transformer, pulse transformer, full-bridge power switches with their drivers. page main supervisor circuits ISL6550 with some external resistor components, which differentially sense output voltage, output under-voltage over-voltage protection, program output reference with four inputs, appropriate output under-voltage lockout delay. page full-bridge controller master over-voltage circuit. page input undervoltage thermal condition detecting circuits. circuits last page used monitor output load level during start turns synchronous FETs during start load conditions. Once FETs turned
FIGURE 106. VIN=48V, VOUT=3.3V, IOUT=60A PURE RESISTIVE LOAD WITH ADDITIONAL CAP. CHANNEL OUTPUT VOLTAGE; CHANNEL SYNCHRONOUS GATE SIGNAL; CHANNEL OUTPUT CURRENT
Application Note 1002
they will turned again unless converter restart load conditions. addition that, some circuits used turn synchronous FETs high speed eliminate negative voltage spike when converter shut down operator fault.
LL_SYNOFF(p6) Master OV(p4)
Output Capacitors ISL6551(p4)& ISL6550 Bridge Driver (p3) Clamp Diode(p2)
Layout
components converter placed both bottom layers within particular area. Figures show where each portion circuit placed both layers. Since high current density design, layers with copper have been used layout. addition, buried vias technique also been applied. careful proper layout helps lower reduce bugs development time. Users should much time needed possible layout board very carefully following guidance. Some guidance laying reference design discussed Layout Considerations section page Refer additional layout guidelines.
5.00" BJ5, BJ6, &C32 SYN1 FETS Driver (p1) XFMR Rectifiers Output Inductors SYN2 FETS Driver (p1) BJ17
Input Thermal(p5)
FIGURE 108. COMPONENT PLACEMENT OUTLINE BOTTOM LAYER
Conclusion
technique ISL6551 full-bridge controller presented. superior performance ISL6551, with companions Intersil's HIP2100 half-bridge driver ISL6550 Supervisor Monitor, been demonstrated reference design 200W, 470kHz telecom power supply incorporating both full-bridge current doubler topologies.The converter implemented with secondaryside peak current mode control includes output overload, input under-voltage, output over-voltage under-voltage protection features. footprint thermistor ready users implement thermal protection primary side. ultra high efficiency 3.3V output full load been achieved. This application note includes step-by-step design procedure converter, which allows easier component selection customization this reference design broader base applications. Users equations, presented CONVERTER DESIGN section determine turns ratio main transformer switching frequency, estimate power dissipation primary switches synchronous rectifiers, calculate filters design parameters. entering these calculations worksheet, users numerical iterations choose appropriate components their applications easier manner. open loop response system roughly approximated using simplified model. addition, extensive experimental results give users better understanding operation converter, ISL6551, ISL6550.
2.50"
Pulse XFMRs Input Caps (p2) 2.45"
Test Points
SBJ1
Test Points
6.45"
BJ3, BJ4, &C16
Main XFMR
Pri. FETs
Test Points
Test Points
BJ1, BJ2, C12,
FIGURE 107. COMPONENT PLACEMENT OUTLINE LAYER
HIP2100
HIP2100
Application Note 1002
TERM DEFINITIONS Coss Dmaxav dVCo dVESL dVESR dVincap dVtr ESRin Fclock FDIST Hopen Hopen2 Iindpeak Iindrms Iinrms ILO1 ILO2 Imag Input Capacitance Output Capacitance Output Capacitance MOSFET Primary Capacitance Transformer Ratio On-Time Interval Lower Clock Period (1/Fclock), Duty Cycle Ripple Current thru Each Output Inductor Overall Ripple Current thru Output Capacitors Maximum Available Duty Cycle Output Ripple Voltage Output Capacitance Ripple Voltage Contributed Output Capacitance Ripple Voltage Contributed Output Capacitors Allowable Input Ripple Voltage Contributed Input Capacitors Output Transient Step Load Transient Output Capacitance Initial Transient Spike Energy Stored Primary Parasitic Capacitance Energy Stored Commutating Inductance Overall Output Capacitors Overall Input Capacitors Overall Output Capacitors System Closed-Loop Bandwidth Internal Clock Frequency Current Distribution Factor thru Synchronous FETs Switching Frequency Transfer Function Error Amplifier Transfer Function Differential Amplifier Open Loop Transfer Function Simplified Model Open Loop Transfer Function with Subharmonic Ramp Components Added High-frequency Correction Term Subharmonic Phenomenon Driver Current Peak Current thru Each Output Inductor Current thru Each Output Inductor Current thru Input Capacitors Overall Ripple Current thru Output Inductors Ripple Current thru Inductor Ripple Current thru Inductor Magnetizing Current Plowfet Ppriswon Isynrmsfr Lext Lmag Nmax Isynpeak Isynrms Isynrmstr Isrms Istep Isyndeadavg Ipripeak Iprirmsfr Iprirmstr Iprirms Iprms Isrmstr Isrmsfr Iorms Ipriavgfr Ipriavgres TERM DEFINITIONS (Continued) Output Load Current Current Turn-on Current thru Output Capacitors Current thru Primary Winding Average Current thru Body Diode Upper Freewheeling Period Average Current thru Body Diode Lower turn-on delay longer than Required Resonant Delay Peak Current thru Primary Winding /Power Switches Current thru Channel Upper Freewheeling Period Current thru Primary Switches Power Transfer Period Overall Current thru Upper Overall Current thru Primary Winding Current thru Synchronous Leg, Current thru Another Synchronous Leg, Current thru Secondary Winding Current thru Secondary Winding Transfer Period Current thru Secondary Winding Freewheeling Period Overall Current thru Secondary Winding Transient Load Step Average Current thru Body Diode Synchronous FETs/External Schottky SYNC DRIVE Scheme Dead Time Peak Current thru Synchronous Overall Current thru Synchronous FETs Current thru Synchronous FETs Power Transfer Period Current thru Synchronous FETs Clamped Freewheeling Period External Commutating Inductance Leakage Inductance Magnetizing Inductance Inductance Each Output Inductor Main Transformer Turns Ratio (Np/Ns) Current Sense Transformer Turns Ratio Maximum Allowable Turns Ratio Main Transformer Driver Switching Losses Power Dissipation Lower Switching Losses Primary Switches Turn-on
Application Note 1002
TERM DEFINITIONS (Continued) Psynfet Psynfetfr Pupfet Rdsonpri Rdsonsyn tDEAD tRESDLY Vdsyn Vinmax Vinmin Vinripple Vmisc Output Power Power Dissipation Synchronous Losses Freewheeling Period Power Dissipation Upper Gate Charge MOSFET Current Sense Resistor Rds(on) Primary Switches Output Load Impendence Rds(on) Synchronous FETs External Slope Added Positive Slope Output Inductor Current Clock Period Clock Dead Time Primary MOSFET Switching Time Turn Resonant Delay Bias Voltage Drivers Body Diode Drop Synchronous FETs Input Voltage Maximum Input Line Minimum Input Line Input Ripple Voltage Output Voltage Miscellaneous Voltage Drops Including Contact Resistance, Winding Resistance, Copper Resistance Maximum Output Voltage Primary MOSFET Turn-on Output Ripple Voltage Voltage across Primary Winding Voltage across Secondary Winding Voltage Drop Synchronous Rds(on) Half Load Maximum Voltage across Impedance Output Capacitors Load
Laszlo Balogh, "The Current doubler Rectifiers: Alternative Rectification Technique Push-Pull Bridge Converters," Design Note-63, Unitrode Integrated Circuit Corporation. "Simplified Analysis Converters Using Model Switch Part Continuous Conduction Mode." IEEE Transactions Aerospace Electronics Systems 1990 490-496. "Designers's Series Part Current-Mode Control Modeling." Switching Power Magazine. July 2001, Volume Issue "PCB Design Guidelines Reduced EMI." Texas Instrument: SZZA009, November 1999. Rais Miftakhutdinov. Analytical Comparison Alternative Control Technique Powering Next Generation Microprocessors." TI-Unitrode Power Supply Design Seminar, 2001 Series. Analytical Methods Power Electronics (Lecture Note). California Institute Technology.
Appendix
Block diagram converter evaluation board. Evaluation board schematics pages). Evaluation board layout pages). Bill Materials evaluation board pages). Preliminary specifications converter.
Vomax Voripple Vsynfet Vsynmax
Acknowledgement
author acknowledges support Magnetics designing providing magnetics samples.
References
Laszlo Balogh, "Design Review: 100W, 400kHz, DC/DC Converter With Current Doubler Synchronous Ratification Achieve Efficiency." Unitrode Integrated Circuit Corporation.
Application Note 1002 Application Note 1002
Secondary Rectification
Max. 2.4V
1.3V 1.1V Inverting Driver
SYNP_G
2.43k Si4842DY
SYNC2 DNP603
SYNP_IN R105 SAPGND BAS40-06LT1 DNP0603
MIC4421BM Reverse Voltage D27, least
SYNOFF
SARTN 5.6n, SARTN
100uF
100uF
100u
100u
100u
100u
100u
DNP1210 R107 SBRTN 5.6n, R108 SA+12V SARTN
0.8uH
SARTN
2.2N, 630V
0.1u, 100V,
DNP0603
DNP0603 R106
SYNN_G
SYNC drivers drive only 20p, therefore cannot turnoff delay SYNC signals used.
MIC4421BM
LOWER1
Application Note 1002 Application Note 1002
3.3Vout
C5-C8 used smaller footprint caps. JMK550BJ107MM
MMJT9410
0.8uH
2.43k LOWER2 SYNC1 YNN_IN Inverting Driver
SAPGND
SARTN
Title Telecom Power Supply Schematics, 3.3V@60A Size Date: Document Number ISL6551EVAL1 Thursday, April 2002
Sheet
SB+48VF SB+48V
R451010 SBRTN SB+12V 47u, 100V
Primary Full-Bridge Power Train
100u, XUP_1 TP11
Primary Full-Bridge Power Train
105K100ST2824, Paktron TP10
C13-C15 replaced with smaller footprint ceramic caps.
SBBIAS MBR0530T1 SBICRTN SAVDDP TP15 R101 36.5 0.1u XUP_4 TP20 LOWER1 TP21 MBR0530T1 2N7002LT1 R102 36.5 DNP0603
SUD40N10-25
TP13
DNP0603
0.1u
DNP0603 36.5 LW1_G LW1_S
HIP2100IB TP19
DNP0603
0.1u 0.1u
5.8V 5.4V
TP24
SBRTN
TP12
UP2_G
0.1u
TP14
Application Note 1002 Application Note 1002
VSSBRTN 3900pF 3900pF LW2_S
UPPER1 TP17 UPPER2
TP16
TP18
ISENSE
LOWER2
DNP0603
SAICRTN TP22 36.5 UP2_S LW2_G TP23
HIP2100IB DNP0603
MMSD914T1
TP25
XLO_4 SAPGND
Title Telecom Power Supply Schematics, 3.3V@60A Size Date:
Document Number ISL6551EVAL1 Thursday, April 2002
Sheet
(6550) Circuits (6550) Circuits
SA+12V
110k BAV70LT1 R100 1.2k 3.65k 26.7k SAICRTN
SAPGND
SAICRTN
DNP0603
3.3Vsense R131
49.9k
Differential Amp. Output 0.1u 0.1u SAICRTN SAICRTN UVDLY VOPP OVUVSEN PGOOD VOPM VOPOUT START VREF5 VID0 VID1 BDAC OVUVTH VID2 DACHI VID3 DACLO VID4 VOPOUT TP26
Application Note 1002 Application Note 1002
TP27 START ENABLE TP28
3.3Vout
0.1u SAICRTN
SAICRTN
REMOTE_SENSE these last output SARTN
5-Bit
ISL6550CIR 28.7k 26.7k
SAICRTN BDAC
SENSE_RTN
Output Reference
Title Telecom Power Supply Schematics, 3.3V@60A SAICRTN Size Date:
Document Number ISL6551EVAL1 Thursday, April 2002
Sheet
(ISL6551) Circuits (ISL6551) Circuits
SABIAS
SA+12V 49.9k
Protect from reverse biasing 100u,
MBR0530T1
LM393D
SAVDDP BGREF 1.263V 180p, NPO, TP30 7.5k 49.9k ISENSE 1.24k
LM393D
Note:
3.3Vsense F_SW=235kHz Tdead=171ns Resonant_Delay=40ns Ramp=5.05E+4V/S LEB=255n SoftStart=10ms Vclamp=3.75V >Voutmax=3.63V TP31 R132 73.2 73.2 2.21k 0.1u MMBT3906LT1, BDAC 100, DNP0603 0.1u 120k 220pF SAICRTN
46.4k SARTN
0.1u
Application Note 1002 Application Note 1002
0.1u 0.1u TP29 R_RESDLY R_RA ISENSE PKILIM BGREF R_LEB CS_COMP EANI VDDP1 VDDP2 PGND UPPER1 UPPER2 LOWER1 LOWER2 SYNC1 SYNC2 ON/OFF DCOK LATSD SHARE SAICRTN 0.1u 5.1K TP32 470p, NPO, SAICRTN 100p 0.1u SAPGND this Synchonous Drivers UPPER1 UPPER2 LOWER1 LOWER2 SYNC1 SYNC2 START
399k
49.9k ISL6551IR
22n, NPO, TP33 TP34 SAICRTN Size Date:
SHARE
VOPOUT 1.5k
30.1k Title Telecom Power Supply Schematics, 3.3V@60A DNP0603
DNP0603
Document Number ISL6551EVAL1 Thursday, April 2002
Sheet
Input Thermal Circuits Input Thermal Circuits
SB+48VF
45.3k, 45.3k, 45.3k,
200k 60.4k 16.2k
DNP0603
TL431AID
Cathode Anode Anode Anode Anode
BAV70LT1
24.9k 100k
IL217AT
100k, DNP0603
R103
RTH1
LM393D this resistor front input capacitor 11/1/2001
SBRTN
SBICRTN Title Telecom Power Supply Schematics, 3.3V@60A Size Date: Document Number ISL6551EVAL1 Thursday, April 2002
MMBT5551LT1, 160V, B=80, SB+12V C131 SA+12V
least 1.3mA 12VREF least 0.7mA 2.5VREF 0.1u
499k
Application Note 1002 Application Note 1002
Anode Cathode Base Collector Emitter
Vsat=0.7
ENABLE 100k 34.3V 33.3V
LM393D
SBICRTN
2N7002LT1
SAICRTN
0.1u
Sheet
Turn TurnSynchronous FETs Synchronous FETs Start-up Power-down Mode Start-up Power-down Mode
SA+12V
200k
ISENSE 220p
LM393D
BAS40-06LT1 100p
SAICRTN
LM393D
R134
C132 2.2n SAICRTN Title Telecom Power Supply Schematics, 3.3V@60A Size Date:
4.99k 3.01k 0.1u 2.67k R133 2.67k
1.263V
BGREF
R104
Application Note 1002 Application Note 1002
SYNOFF
SAICRTN
SAICRTN
SAICRTN
START D131 BAS40-06LT1
ENABLE
Document Number ISL6551EVAL1 Thursday, April 2002
Sheet
Application Note 1002
Application Note 1002
Application Note 1002
Application Note 1002
Application Note 1002
Application Note 1002
Application Note 1002
Application Note 1002
Application Note 1002
Application Note 1002
Application Note 1002
Application Note 1002
Application Note 1002
BILL MATERIALS (1/2)
Item Quantity Reference BJ4,BJ2 C1,C10,C20,C23,C29,C49, C52,C62,C63,C68,C69 C2,C3,C11 C4,C5,C6,C7,C8,C74,C75 C13,C14,C15 C32,C16 C17,C18,C19,C21,C22,C25, C26,C35,C36,C38,C39,C42, C50,C56,C59,C76,C80 C24,C30,C34,C53,C54,C71, C72,C73,C77,C131 C27,C28 C31,C33,C44,C51,C55,C78 C41,C57,C58 C60,C45 C64,C65 C67,C66 C132 D1,D2,D3,D4,D5,D10,D11, D13,D14,D19,D22,D26,D27, D28,D29,D30 D6,D7,D8,D9,D15,D16,D17, D18,D34,D35,D36,D37,D38, D20,D31 D21,D24 D23,D25,D131 D32,D33 JP1,JP2 Jumpers L2,L3 M2,M1 M3,M4 PC1, Q1,Q2,Q3,Q4,Q7,Q8,Q9,Q10 Q13,Q14,Q16,Q17 Q15,Q18,Q19,Q20,Q23 RTH1 R1,R16,R34 R3,R18 R4,R15,R107 R19,R5 Part binding post White binding post Yellow binding post Green binding post Black binding post Blue binding post DNP0603 X7R, 100u, 6.3V 0.1u, 100V 47u, 100V 100V 100u, 0.1u, X7R, Footprint BINDING/POST BINDING/POST BINDING/POST BINDING/POST BINDING/POST BINDING/POST SM/C_0603 SM/C_0805 SM/L_2220 SM/C_0805 CPCYL1/D.400/LS.200/.034 SM/ST2824 CYL/D.200/LS.079/.034 SM/C_0603 Vendor Johnson Components Johnson Components Johnson Components Johnson Components Johnson Components Johnson Components Various Various Taiyo Yuden Panasonic Paktron Panasonic Various Vendor Part Number 111-0702-001 111-0701-001 111-0707-001 111-0704-001 111-0703-001 111-0710-001 Various JMK550BJ107MM ECA-2AHG470 105K100S2824 ECA-1CHG101 Various
10n, X7R, 10p, X7R, X7R, 180p, NPO, 220p, X7R, DNP0603 33n, X7R, 100p, X7R, 0.1u, 470p, NPO, 22n, X7R, 220p, X7R, 5.6n, X7R, 3900pF, X7R, 2.2N, X7R, 630V, 1206 2.2n, X7R, MMSD914T1
SM/C_0603 SM/C_0603 SM/C_0603 SM/C_0603 SM/C_0603 SM/C_0603 SM/C_0603 SM/C_0603 SM/C_0805 SM/C_0603 SM/C_0805 SM/C_0603 SM/C_0805 SM/C_0603 SM/L_2220 SM/C_0603 SOD123
Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Semiconductor
Various Various Various Various Various Various Various Various Various Various Various Various 5.6n, X7R, Various C3216X7R2J222M Various MMSD914T1
MBR0530T1
SOD123
Semiconductor
MBR0530T1
BAV70LT1 BAS40-06LT1 R451010 3-Pin Connector Jumpers &JP2 0.8uH MIC4421BM HIP2100IB ISL6550CIR ISL6551IR TL431AID IL217AT KPA8CTP Si4842DY MMJT9410 SUD40N10-25 2N7002LT1 MMBT3906LT1 MMBT5551LT1 100k, DNP0603 DNP603 2.43k
DL-35 SM/SOT23_123 SM/SOT23_123 SOD123 SM/C_1812 TP\3P SM/R_2512 IND/DTPC1000-0002 SOG.050/8/WG.244/L.200 SOG.050/8/WG.244/L.200 MLFP.65M/20/5X5 MLFP.65M/28/6X6 SOG.050/8/WG.244/L.200 SOG.050/8/WG.244/L.200 BINDING/POST_2_REV2 SOG.050/8/WG.244/L.200 SM/SOT223_BCEC TO252AA-DPAK SM/SOT23_123 SM/SOT23_123 SM/SOT23_123 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0805 SM/R_0805
Digi-Key Semiconductor Semiconductor Semiconductor LittleFuse Digi-Key Various Various Magnetics Micrel Semiconductor Intersil Intersil Intersil Texas Instrument Infineon Burndy Vishay Siliconix Semiconductor Vishay Siliconix Semiconductor Semiconductor Semiconductor Western Electronic Components Corp. Various Various Various Various Various
160-1173-2-ND BAV70LT1 BAS40-06LT1 MMSD914T1 R451010 S1012-03-ND Jumpers &JP2 Various 015138 MIC4421BM HIP2100IB ISL6550CIR ICL6551IR TL431AID IL217AT KPA8CTP Si4842DY MMJT9410 SUD40N10-25 2N7002LT1 WSTL06104R
Application Note 1002
BILL MATERIALS (2/2)
Item Quantity Reference R6,R7,R12,R13,R14,R25, R28,R30 R8,R48,R60,R67 R77,R17 R20,R27,R56,R57 R23,R24,R26,R33 R29,R31,R52,R53,R54 R32,R51,R55,R72,R87,R88, R35,R49,R95 R36,R37,R38,R39,R41,R45 R42,R47 R108,R46 R65,R64 R66,R71,R82 R76,R98,R131 R78,R79,R80 R97,R81 R83,R101,R102,R103,R104, R105,R106 R89,R91 R133,R93 R99,R134 R100 R132 TP1,TP2,TP3,TP4,TP5,TP6, TP7,TP8,TP9,TP10,TP11, TP12,TP13,TP14,TP15,TP16, TP17,TP18,TP19,TP20,TP21, TP22,TP23,TP24,TP25,TP26, TP27,TP28,TP29,TP30,TP31, TP32,TP33,TP34 T5,T3 U1,U2,U3 board Part 49.9k DNP1210 DNP0603 36.5 28.7k 26.7k 110k DNP0603 DNP0805 46.4k 7.5k 1.24k 399k 120k 73.2 3.65k 5.1K 30.1k 1.5k 45.3k 200k 60.4k 499k 16.2k 100k 24.9k 4.99k 2.67k 3.01k 1.2k 2.21k 5-Bit Switch ON/OFF Switch Test Point Footprint SM/R_0805 SM/R_0603 SM/R_1210 SM/R_1210 SM/R_1210 SM/R_0603 SM/R_0805 SM/R_2512 SM/R_0805 SM/R_0805 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0805 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0805 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0805 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0805 SM/R_0805 SM/R_0603 SM/R_0603 SM/R_0603 SM/R_0603 DIPSW.100/10/W.300/L.550 SWITCH_DPST Vendor Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Various Components Keystone Vendor Part Number Various 208-5 GT11MSCKE 5002
Main Transformer IND/DTPC1000-0001 Pulse Transformer DT_X_330X260_REV11 Current Sense Transformer DT_XC_640X400_REV3 LM393D SOG.050/8/WG.244/L.200 layers, Copper, Buried Vias
Magnetics Magnetics Magnetics Semiconductor Various
010107 UGDT125100 010109 LM393D layers, Copper
Application Note 1002
CONVERTER PRELIMINARY SPECIFICATIONS
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
Other recent searches
W39V040A - W39V040A W39V040A Datasheet
SPX5205M5-5 - SPX5205M5-5 SPX5205M5-5 Datasheet
SPI80N06S2-08 - SPI80N06S2-08 SPI80N06S2-08 Datasheet
SPP80N06S2-08 - SPP80N06S2-08 SPP80N06S2-08 Datasheet
SPB80N06S2-08 - SPB80N06S2-08 SPB80N06S2-08 Datasheet
SOT23L-6 - SOT23L-6 SOT23L-6 Datasheet
K2006 - K2006 K2006 Datasheet
HMC-APH403 - HMC-APH403 HMC-APH403 Datasheet
AN1177 - AN1177 AN1177 Datasheet
78P2351R - 78P2351R 78P2351R Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
