QUALITY SEMICONDUCTOR, INC. Skew Clock Driver/ Buffer Mobile with

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QS5810 ADVANCE INFORMATION
QUALITY SEMICONDUCTOR, INC.
Skew Clock Driver/ Buffer Mobile with SO-DIMMS
QS5810 ADVANCE INFORMATION
DESCRIPTION
QS5810 high speed, noise non-inverting buffer designed SDRAM clock buffer applications. outputs them could used drive four SDRAM SO-DIMMs, remaining used external feedback stage synchronization master clock. QS5810 also includes interface, which enable disable each output clock driver. Turning unused outputs reduces EMI.
output buffer/driver Tri-state testing programming capability Power Supply Voltage 3.3V Skew outputs (<250ps) Multiple noise reduction SSOP package
Figure Functional Block Diagram
SDATA SCLK DECODING PORT
SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM
BUF_IN SDRAM SDRAM SDRAM
MDSC-00046-00 SEPTEMBER 1998
QUALITY SEMICONDUCTOR, INC.
QS5810 ADVANCE INFORMATION Figure Configuration (All Pins View)
SSOP
SDRAM SDRAM SDRAM SDRAM BUF_IN SDRAM VDDI2C SDATA
SDRAM SDRAM SDRAM SDRAM SDRAM GNDI2C SCLK
Table Description
Name SDRAM (0:3) SDRAM (4:7) SDRAM (8:9) BUF_IN SDATA SCLK Number 2,3,6,7 22,23,26,27 11,18 Type
1,5,10,19,24,28 4,8,12,17,21,25
GNDI2C VDDI2C
Functional Description SDRAM Byte Clock outputs. SDRAM Byte Clock outputs. SDRAM Byte Clock outputs. Input buffers. Data input. 100k internal pull VDD. Clock input. 100k internal pull VDD. Tri-state output enable. When asserted HIGH, clock outputs high impedance. 100k internal pull VDD. 3.3V power supply output buffers. Ground output buffers Ground circuitry. 3.3V power supply circuitry.
Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V 4.6V Output Voltage VOUT -0.5V 4.6V Input Voltage -0.5V 4.6V Input Diode Current with -20mA Maximum Power Dissipation 85°C, 600mW TSTG Storage Temperature -65° 150°C
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage devices that result functional reliability type failures.
QUALITY SEMICONDUCTOR, INC.
MDSC-00046-00 SEPTEMBER 1998
QS5810 ADVANCE INFORMATION Table Recommended Operating Conditions
Symbol Description Power Supply Voltage Operating Temperature Load Capacitance Input Capacitance(1) 3.135 3.465 Unit
Table Electrical Characteristics Over Operating Range
Symbol Parameter Input High Voltage Input Voltage Test Condition inputs inputs except inputs inputs (SDATA SCLK) Input High Input Current Input Current BUF_IN SDATA, SCLK Supply Current 0pF; 66.66MHz(1) 0pF; 100MHz(1) 30pF; 66.66MHz(1) 30pF; 100MHz(1) BUF_IN VDD, other inputs Output High Voltage SDRAM (0:9) -36mA Output Voltage SDRAM (0:9) 25mA Output Voltage SDATA IOLI2C -100 Unit
VOLI2C
Table Electrical Characteristics Over Operating Range
Symbol TPHL TPLH TPZL TPZH TPLZ TPHZ Parameter Rise Time(1) Fall Time(1) Duty Cycle(1)
Ompa
Skew (output output)(1) Propagation Delay Enable Delay DisableDelay
1.5V; Figure 1.5V: Figure
Test Condition 0.4V 2.4V; 30pF 2.4V 0.4V; 30pF 1.5V; 30pF; With Input Clock 1.5V; 30pF outputs; Figure 1.5V
Unit
Note: Applies SDRAM (0:9) outputs. Guaranteed design, subject 100% production testing.
MDSC-00046-00 SEPTEMBER 1998
QUALITY SEMICONDUCTOR, INC.
QS5810 ADVANCE INFORMATION Serial Interface Control
interface permits individual enable/disable each clock output: unused outputs disabled reduce EMI. QS5810 slave receiver device. read back data stored latches verification. data transfer rate supported interface 100k bits/sec. Data transferred bytes (with addition start, stop, acknowledge bits) sequential order from lowest highest byte with ability stop after complete byte been transferred. first bytes transferred must Command Code followed Byte Count. Both these bytes ignored device. address QS5810
Address read/write writes reads. During read back, first byte read Byte Count representing number bytes following (fixed
Table Serial Configuration Command Bitmaps
Byte SDRAM Active/Inactive Register Enable, Disable), Default Enable
Description Initialize Initialize Initialize Initialize SDRAM (Active/Inactive) SDRAM (Active/Inactive) SDRAM (Active/Inactive) SDRAM (Active/Inactive)
Byte SDRAM Active/Inactive Register Enable, Disable), Default Enable
Byte SDRAM Active/Inactive Register Enable, Disable), Default Enable
Description SDRAM (Active/Inactive) SDRAM (Active/Inactive) Reserved, power Reserved, power Reserved, power Reserved, power Reserved, power Reserved, power
Description SDRAM (Active/Inactive) SDRAM (Active/Inactive) SDRAM (Active/Inactive) SDRAM (Active/Inactive) Initialize Initialize Initialize Initialize
QUALITY SEMICONDUCTOR, INC.
MDSC-00046-00 SEPTEMBER 1998
QS5810 ADVANCE INFORMATION Figure Test Circuit
Pulse Generator VOUT 7.0V Parameter Switch Tested Position Closed tPLZ, tPZL Others Coax Oscilloscope Open
30pF
Figure Timing Diagram
ENABLE
DISABLE
CONTROL INPUT OUTPUT NORMALLY tPZL SWITCH CLOSED tPZH SWITCH OPEN 0.5VCC 0.5VCC
tPLZ 0.3V tPHZ 0.3V
1.5V 3.5V
INPUT
OUTPUT NORMALLY HIGH
Enable Disable Times
1.5V tPLH OUTPUT tPHL 2.0V 0.5VCC 0.8V
INPUT tPHL 1.5V tPLH OUTPUT 0.5VCC
Propagation Delay
Pulse Skew tSK(p)
MDSC-00046-00 SEPTEMBER 1998
QUALITY SEMICONDUCTOR, INC.
QS5810 ADVANCE INFORMATION
Figure Ordering Information
Clock Management Product Prefix (QS5) Part Number Package (200-mil SSOP)
Figure Packaging Information 200-mil SSOP Package Code
Shrink Small Outline Package
Note: Refer applicable symbol list. dimensions inches. number lead positions. referance datums molded body include mold flash/protrusions. Mold flash/ protrusions shall exceed .006in. side. Interlead flash protrusions shall exceed .008in. side.
BASE PLANE
SEATING PLANE
GAGE PLANE
JEDEC# DWG# Symbol .065 0.295 0.025 0.079 0.002 0.010 0.004 0.394 0.205
MO-150-AH 0.008 0.015 0.008 0.409 0.212 0.0256 0.319 0.040 .071 .010 .035 MDSC-00046-00 SEPTEMBER 1998
QUALITY SEMICONDUCTOR, INC.

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