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QUALITY SEMICONDUCTOR, INC. Guaranteed Skew CMOS Clock Driver/Buf


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QS5807T, QS52807T
QUALITY SEMICONDUCTOR, INC.
Guaranteed Skew CMOS Clock Driver/Buffer
DESCRIPTION
QS5807T QS52807T
output, skew clock signal buffer output voltage swing on-chip resistors available noise Input hysteresis better noise margin Guaranteed skew 0.35ns same transition 0.45ns opposite transition 0.75ns different devices Industrial temperature range Available QSOP SOIC (SO)
QS5807T clock driver/buffer circuits used clock buffering schemes where skew parameter. QS5807T generates non-inverting outputs. Designed QSI's proprietary QCMOS process, these devices provide propagation delay buffering with on-chip skew 0.35ns sametransition, same-bank signals. QS52807T on-chip series termination resistors lower noise clock signals. series resistor versions recommended driving unterminated lines with capacitive loading other noise sensitive clock distribution circuits. These clock buffer products designed high-performance workstations, embedded personal computing systems. Several devices used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. Application Note AN-21 more information low-skew clock buffers.
Figure Functional Block Diagram
MDSC-00023-01 OCTOBER 1998
QUALITY SEMICONDUCTOR, INC.
QS5807T, QS52807T Figure Configurations (All Pins View)
Table Description
Name Description Clock Input Clock Outputs
Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V 7.0V Output Voltage VOUT -0.5V 7.0V Input Voltage -0.5V 7.0V Input Voltage (for pulse width 20ns) -3.0V Input Diode Current with -20mA Output Current Max. Sink Current/Pin 120mA Maximum Power Dissipation 85°C, QSOP 0.82 watts SOIC 0.75 watts TSTG Storage Temperature -65° 150°C
Note: Stresses greater than those listed under absolute maximum ratings cause permanent damage devices that result functional reliability type failures.
Table Capacitance
25°C, 1MHz, QSOP Pins SOIC Unit
Note: Capacitance characterized tested.
QUALITY SEMICONDUCTOR, INC.
MDSC-00023-01 OCTOBER 1998
QS5807T, QS52807T Table Electrical Characteristics Over Operating Range
Industrial: -40°C 85°C, 5.0V ±10% Symbol ROUT Parameter Input HIGH Voltage Input Voltage Clamp Diode Voltage Output HIGH Voltage QS5807T Output HIGH Voltage QS52807T Output Voltage QS5807T Output Voltage QS52807T Input Leakage Current Short Circuit Current Input Hysteresis Output Resistance QS52807T
(2,3)
Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs Min., -18mA
Typ(1) -0.7
-1.2 0.50 0.50
Unit
Min.,VIN=VIH VIL, -15mA -32mA Min.,VIN=VIH VIL, -8mA Min.,VIN=VIH VIL, 48mA Min.,VIN=VIH VIL, Max., VOUT VTLH VTHL Inputs Min., 12mA
Notes: Typical values indicate 5.0V 25°C. more than output should used test this high power condition duration second. Guaranteed design tested. Output resistance represents total output impedance logic device includes added series termination resistance.
-250
MDSC-00023-01 OCTOBER 1998
QUALITY SEMICONDUCTOR, INC.
QS5807T, QS52807T Table Power Supply Characteristics
Industrial: -40°C 85°C, 5.0V ±10% Symbol Parameter ICCD Quiescent Power Supply Current Power Supply Current Input HIGH Test Conditions Max., Max., 3.4V Input toggling duty cycle 0.09 3.4V 3.4V 21.5 Unit
Dynamic Power Supply(1) Max., outputs enabled, Current Output Total Power Supply(2) Current Examples Max., Input duty cycle, 10MHz Max., Input duty cycle, 2.5MHz
Notes: Guaranteed tested. 0pF. (ICC)(DH)(NT) ICCD (fO)(NO) where: Input duty cycle Number HIGH inputs (one) Output frequency Number outputs (ten)
Table Switching Characteristics Over Operating Range
Industrial: -40°C 85°C, 5.0V ±10% QS5807T, CLOAD 50pF, RLOAD 500. QS52807T, CLOAD 50pF resistor) 5807T 52807T 0.70 0.75 0.60 0.65 0.35 0.45 0.50 0.75
Symbol Description(1) tSK(O1) tSK(p) Skew between outputs same transition Pulse Skew: Skew between 5807T opposite transitions 52807T same output (tPHL-tPLH) Part-to-part skew(2) Propagation Delay(3) Output Rise Fall Time
Unit
0.70 0.75
tSK(t) tPLH tPHL
Notes: Skew parameters guaranteed across temperature range, production tested. Test Circuit Waveforms. Minimums guaranteed tested. tSK(t) only applies devices same transition, same part type, same temperature, power supply voltage, loading, package speed grade. propagation delay range indicated Min. Max. specifications results from process environmental variables. These propagation delay limits imply skew.
QUALITY SEMICONDUCTOR, INC.
MDSC-00023-01 OCTOBER 1998
QS5807T, QS52807T Figure Test Circuits Waveforms
Pulse Generator VOUT
50pF
Pulse generator pulses: 1.0MHz; 2.5ns; 2.5ns
Test Circuit
INPUT tPLH OUPUT tPHL 2.0V 1.5V 0.8V
OUPUT
INPUT
1.5V
tSK(p) tPHL tPLH
INPUT tPLH1
tPLH
tPHL
1.5V
1.5V
Propagation Delay
Pulse Skew tSK(p)
INPUT
tPLH1 tPHL1 tSK(O1) tSK(O1) tPLH2
1.5V
1.5V tPHL1 PART OUTPUT tSK(t) 1.5V tSK(t) PART OUTPUT 1.5V tPLH2 tPHL2
OUPUT
1.5V
1.5V tPHL2
OUPUT
tSK(O1) |tPLH2 tPLH1| |tPHL2 tPHL1|
tSK(T) |tPLH2 tPLH1| |tPHL2 tPHL1|
Output Skew tSK(O1)
Part-to-Part Skew tSK(t)
MDSC-00023-01 OCTOBER 1998
QUALITY SEMICONDUCTOR, INC.
QS5807T, QS52807T
ORDERING INFORMATION Example:
QS52807ATClock Management Product Prefix (QS5) Resistor Option (blank) Part Number Package (150 wide QSOP) (300 wide SOIC) Level Designator Speed (blank)
QUALITY SEMICONDUCTOR, INC.
MDSC-00023-01 OCTOBER 1998

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