IDT74LVCH162952A 3.3V CMOS 16-BIT ADVANCE REGISTERED TRANSCEIVER INFOR

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IDT74LVCH162952A 3.3V CMOS 16-BIT ADVANCE REGISTERED TRANSCEIVER INFOR

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IDT74LVCH162952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
IDT74LVCH162952A 3.3V CMOS 16-BIT ADVANCE REGISTERED TRANSCEIVER INFORMATION WITH 3-STATE OUTPUTS, VOLT TOLERANT I/O, BUS-HOLD
Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP 0.40mm pitch TVSOP packages Extended commercial range -40°C +85°C 3.3V ±0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs Volt tolerant Supports insertion
DESCRIPTION:
This 16-bit registered transceiver built using advanced dual metal CMOS technology. This high-speed, power device organized independent 8-bit D-type registered transceivers with separate input output control independent control data flow either direction. example, A-to-B enable (CEAB) must enter data from port. CLKAB controls clocking function. When CLKAB toggles from lowto-high, data present port will clocked into register. OEAB performs output enable function port. Data flow from port port similar requires using CEBA, CLKBA, OEBA inputs. Full 16-bit operation achieved tying control pins independent transceivers together. pins driven from either 3.3V devices. This feature allows this device translator mixed 3.3V/5V supply system. LVCH162952A series resistors device output structure which will significantly reduce line noise when used with light loads. driver been designed drive ±12mA designated threshold levels. LVCH162952A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
Drive Features LVCH162952A: Balanced Output Drivers: ±12mA switching noise
APPLICATIONS:
3.3V mixed voltage systems Data communication telecommunication systems
Functional Block Diagram
CEBA CLKBA OEAB CEAB CLKAB CEAB CLKAB OEAB CEBA CLKBA
OEBA
OEBA
SEVEN OTHER CHANNELS
SEVEN OTHER CHANNELS
1999 Integrated Device Technology, Inc.
FEBRUARY 1999
DSC-4690/-
IDT74LVCH162952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
CONFIGURATION
1OEAB 1CLKAB 1CEAB
ABSOLUTE MAXIMUM RATINGS
1OEBA 1CLKBA 1CEBA
Unit
Link
SO56-1 SO56-2 SO56-3
Symbol VTERM(2) VTERM(3) TSTG IOUT
Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each
Max. +6.5 +6.5 +150 ±100
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25OC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
Link
2CEAB 2CLKAB 2OEAB
2CEBA 2CLKBA 2OEBA
NOTE: applicable device type.
FUNCTION TABLE
xCEAB Inputs xCLKAB xOEAB
(1,2)
Outputs
SSOP/ TSSOP/ TVSOP VIEW
DESCRIPTION
Names xOEAB xOEBA xCEAB xCEBA xCLKAB xCLKBA Description A-to-B Output Enable Inputs (Active LOW) B-to-A Output Enable Inputs (Active LOW) A-to-B Clock Enable Inputs (Active LOW) B-to-A Clock Enable Inputs (Active LOW) A-to-B Clock Inputs B-to-A Clock Inputs A-to-B Data Inputs B-to-A 3-State Outputs(1) B-to-A Data Inputs A-to-B 3-State Outputs(1)
NOTE: These pins have "Bus-hold". other pins standard inputs, outputs, I/Os.
1998 Integrated Device Technology, Inc.
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance Low-to-High Transition Level before indicated steady-state input conditions were established A-to-B data flow shown; B-to-A data flow similar uses xCEBA, xCLKBA, xOEBA.
DSC-123456
IDT74LVCH162952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40OC +85OC
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, 18mA 3.3V 3.6V 5.5V(2) Quiescent Power Supply Current Variation input 0.6V other inputs
Link
Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 5.5V 5.5V
Min.
Typ.(1)
Max.
Unit
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
Link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74LVCH162952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 2.7V 3.0V Output Voltage 2.3V 3.6V 2.3V 2.7V 3.0V 12mA 0.1mA 12mA Min. Max. 0.55 0.55
Link
Unit
2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C +85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance transceiver Outputs enabled Power Dissipation Capacitance transceiver Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
SWITCHING CHARACTERISTICS
Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xCLKAB, xCLKBA xBx, Output Enable Time xOEBA, xOEAB xAx, Output Disable Time xOEBA, xOEAB xAx, Set-up Time, HIGH xAx, before xCLKAB, xCLKBA Hold Time, HIGH xAx, after xCLKAB, xCLKBA, Set-up Time, HIGH xCEAB, xCEBA before xCLKAB, xCLKBA Hold Time, HIGH xCEAB, xCEBA after xCLKAB, xCLKBA Pulse Width HIGH xCLKAB xCLKBA Output Skew(2)
2.7V Min. Max.
3.3V±0.3V
Min.
Max.
Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH162952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) 2.7V VCC(2)= 2.5V ±0.2V Unit
Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT OPPOSITE PHASE INPUT TRANSITION
Link
TEST CIRCUITS OUTPUTS
Pulse Generator D.U.T. LOAD Open
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT ITCH NORMALLY CLOSE tPZH OUTPUT ITCH NORMALLY OPEN HIGH LOAD/2 DISABLE LOAD/2
Link
DEFINITIONS: Link Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTE: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tREM
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
Open
Link
OUTPUT SKEW
INPUT OUTPUT OUTPUT tPLH2 tPHL2 PLH1 PHL1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
tPLH2 tPHL2 PHL1
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank. Link
IDT74LVCH162952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
ORDERING INFORMATION
Bus-Hold XXXX Device Type Package ange
952A
Shrink Outline Package 56-1) Thin Shrink Outline Package 56-2) Thin Very utline Package (SO56-3) 16-Bit Registered Transceiver Double-Density with Resistors, ±12m Bus-hold -40°C +85°C
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IDT74LVCH162952A 3.3V CMOS 16-BIT ADVANCE REGISTERED TRANSCEIVER INFOR

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