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Version February 1999
2975 Stender Way, Santa Clara, California 95054 Telephone: (800) 345-7015 TWX: 910-338-2070 FAX: (408) 492-8674 Printed U.S.A. 1999 Integrated Device Technology, Inc.
Integrated Device Technology, Inc. reserves right make changes products specifications time, without notice, order improve design performance supply best possible product. does assume responsibility circuitry described other than circuitry embodied product. Company makes representations that circuitry described herein free from patent infringement other rights third parties which result from use. license granted implication otherwise under patent, patent rights other rights, Integrated Device Technology, Inc.
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This hardware user's manual includes both hardware software information RC64474 RC64475, high-performance 64-bit microprocessors that extend RISCore4000 family choices offered Integrated Device Technology (IDT). Operational overviews, functional descriptions, diagrams, flowcharts provided assist system developers obtaining optimum device performance.
Information included this manual such mechanicals, package pin-outs electrical characteristics found data sheet these devices, which available from website (www.idt.com) well through your local sales representative.
Chapter "RC64474/RC64475 Overview," provides complete introduction performance capabilities these 64-bit processors. Included this chapter summary features devices well table that provides feature's summary IDT's RISCore4000 family. Chapter "CPU Instruction Overview," presents general overview three instruction formats MIPS architecture. Instruction summary tables also provided. Chapter "RISCore4000 Pipeline," discusses operation 5-stage pipeline design used RISCore4000 core well exception interlock handling. Chapter "Memory Management Unit," contains discussion virtual-to-physical address translation, Translation Lookaside Buffer management User, Kernel, Supervisor modes operation. Chapter "System Control Coprocessor (CPO)," contains illustrations, definitions descriptions memory management exception processing registers. explanation address translation process also provided. Chapter "CPU Exception Processing," contains illustrattions, definitions descriptions various exception processing registers discusses exceptions handling processes involved. Chapter "The Floating-Point Unit," describes RISCore4000 floating-point status control registers includes programming model, single double precision floating-point operation formats well information RISCore4000 floating-point pipeline. Chapter "Floating-Point Exceptions," provides explanation floating-point unit exception types; exception trap processing; exception flags; saving restoring state, when handling exception, trap handlers IEEE Standard exceptions. Chapter "Processor Signal Descriptions," describes signals used conjunction with RC64474 RC64475 processors. Tables provide signal name, definition, direction description. Each table listed according functional groupings. Chapter "The Clocking, Reset Initialization Interface," contains timing diagrams descriptions basic system clocks timing parameters used RC64474 RC64475 processors. processor signal-summary table provided that lists each signal their possible states.
Chapter "Cache Organization, Operation Coherency," describes on-chip cache memory attributes accessibility. Cache states, cache line ownership cache locking feature also discussed. Chapter "System Interface Overview," explains system interface process from standpoint both processor external agent. Chapter "The Read Interface," discusses specifics read interface read operation processes. Processor read protocols defined, request response timing diagrams included. Chapter "The Write Interface," discusses specifics Write protocol associated operations. Timing diagrams included. Chapter "Processor Interrupts," provides information hardware software interrupt processes RC64474 RC64475 processors. Chapter "Processor Error Checking," describes parity error detection well error checking correcting processes internal transactions. table provided that summarizes these error checking operations. Chapter "Standard JTAG Support Interface," introduces standard JTAG interface used board-level debugging. description table provides description pins added support this feature. description Test Access Port (TAP) interface controller state assignments also included. Appendix "Cache Operations' Timing," lists cycle operation counts caveats RC64474/RC64475 cache operations timing. Appendix "Entering Standby Mode," details power management feature RC64474 RC64475 processors. flowchart standby operation included. Appendix Coprocessor Hazards," identifies RC64474/475 coprocessor hazards.
RC64474/RC64475 Overview Chapter Introduction. Performance. Device compatibility. RISCore4000 Family Summary features. Device overview. RISCore4000 pipeline RISCore4000 registers. instruction sets. Data formats addressing. RISCore4000 coprocessors. System control coprocessor, Floating-point coprocessor, Floating-point units Address mapping Joint translation-lookaside buffer (JTLB). 1-10 Instruction translation lookaside buffer (ITLB). 1-10 Data translation (DTLB). 1-10 Cache memory. 1-10 Instruction cache (I-cache). 1-10 Data cache (D-cache) 1-11 Write buffer. 1-11 System interfaces. 1-11 System address/data bus. 1-12 System command bus. 1-12 SDRAM timing protocols 1-12 Handshake signals. 1-13 Non-overlapping system interface. 1-13 Write reissue pipeline write 1-13 External requests 1-13 Boot-time options 1-13 Instruction Overview Chapter Instruction formats. Load store instructions (I-type). Load delay slot scheduling Defining access types Computational instructions (R-type I-type). Operations with 32-bit operands Cycle timing multiply divide instructions. Jump Branch instructions (J-type R-type) Jump instruction overview Branch instruction overview Special instructions (R-type) Exception instructions Coprocessor instructions (I-type) Instruction summary. RISCore4000 Pipeline Chapter Pipeline operations. Branch delay
Load delay. Interlock Exception handling Exception conditions Stall conditions Slip conditions RISCore4000 write buffer. Memory Management Unit. Chapter Address spaces. Physical address space. Virtual-to-Physical address translation 32-bit virtual address translation 64-bit virtual address translation Operating modes. User Mode 32-bit User mode (useg). 64-bit User mode (xuseg) Supervisor mode operations 64-bit Supervisor mode, user space (xsuseg) 64-bit Supervisor mode, current supervisor space (xsseg) 64-bit Supervisor Mode, Separate Supervisor Space (csseg). Kernel mode operations 32-bit kernel mode, User Space (kuseg) 32-bit kernel mode, Kernel Space (kseg 32-bit kernel mode, Kernel Space (kseg1) 32-bit kernel mode, Supervisor Space (ksseg). 32-bit kernel mode, Kernel Space (kseg3) 64-bit kernel mode, user space (xkuseg) 4-10 64-bit kernel mode, current supervisor space (xksseg). 4-10 64-bit kernel mode, physical spaces (xkphy. 4-10 64-bit kernel mode, Kernel Space (xkseg) 4-11 64-bit kernel mode, compatibility spaces (ckseg1:0, cksseg, ckseg3) 4-11 System Control Coprocessor (CP0) .Chapter Format entry Registers Index Register Random Register EntryLo0 (2), EntryLo1 Registers. PageMask Register (5). Wired Register EntryHi Register (10) Processor Revision Identifier (PRId) Register (15). Config Register (16) Load Linked Address (LLAddr) Register (17) Cache Registers/TagLo(28) TagHi(29) Address translation process misses. 5-10 instructions. 5-10 Exception Processing .Chapter Exception processing registers Context register (4). Virtual Address register (BadVAddr) (8). Count register (9). Compare register (11) Status register (12) Status register modes access states. Cause register (13).
Exception Program Counter (EPC) register (14) XContext register (20) Error Checking Correcting (ECC) register (26). Cache Error (CacheErr) register (27) Error Exception Program Counter (Error EPC) register (30) 6-10 Processor exceptions 6-11 Reset exception process 6-11 Cache Error exception process 6-11 Soft Reset exception process 6-12 General exception process. 6-12 Exception vector locations. 6-12 Exception priority 6-13 Reset exception. 6-14 Soft Reset exception 6-14 Nonmaskable Interrupt exception. 6-15 Address Error exception 6-15 exceptions. 6-16 Invalid exception 6-16 Modified exception 6-17 Cache Error exception. 6-17 Error exception 6-17 Integer Overflow exception. 6-18 Trap Exception 6-18 System Call exception 6-18 Breakpoint exception 6-19 Reserved Instruction exception 6-19 Coprocessor Unusable exception. 6-19 Floating-Point exception 6-20 Interrupt exception. 6-20 Handling/Servicing flowcharts 6-20 Floating-Point Unit. Chapter Features General registers (FGRs) Control registers (FCRs) Implementation/revision register, (FCR0). Control/Status register (FCR31) IEEE Standard 754. Floating-Point formats Binary fixed-point format instruction overview. Load, store, move instructions 7-10 Transfers between memory. 7-10 Transfers between 7-10 Load delay hardware interlocks. 7-11 Floating-Point conversion instructions. 7-11 Floating-Point computational instructions. 7-11 Branch condition instructions 7-11 Floating-Point compare operations. 7-11 Instruction pipeline overview 7-12 Resource scheduling rules 7-13 Floating-Point Exceptions .Chapter Exception types Exception Trap Processing. Flags. exception types
Inexact exception Invalid operation exception Division-by-Zero exception Overflow exception (O). Underflow exception Unimplemented instruction exception (E). Saving restoring state. Trap handlers Processor Signal Descriptions .Chapter System interface signals Clock/Control interface Interrupt interface Initialization interface. JTAG interface RC64475 signal summary RC64474 RC64475 signal summary. Clocking, Reset Initialization Interface .Chapter System clocks 10-1 System timing parameters. 10-2 Alignment MasterClock. 10-2 Phase-Locked loop (PLL) 10-2 components operation 10-3 Passive components 10-3 Connecting external agent 10-4 Initialization reset interface. 10-4 Signal descriptions 10-4 Power-on reset 10-6 Cold reset 10-6 Warm reset. 10-6 Initialization sequence 10-6 Boot-Mode settings 10-8 Cache Organization, Operation Coherency.Chapter Cache operation overview 11-1 RC64474/RC64475 cache attributes. 11-2 Organization accessibility. 11-2 Primary instruction cache (I-Cache) organization. 11-3 Primary data cache (D-Cache) organization 11-4 Accessing primary caches. 11-5 Cache states 11-5 Cache-line ownership. 11-6 Cache write policy 11-7 Cache state-transition diagrams. 11-7 Cache coherency overview 11-7 Cache coherency attributes. 11-8 Uncached 11-8 Noncoherent 11-8 Cache locking. 11-8 Data cache locking example. 11-9 Instruction cache locking 11-9 Synchronization support. 11-10 Test-and-Set. 11-10 Counter. 11-11 Load linked Store conditional 11-12 Examples Using 11-13 System Interface Overview.Chapter Terminology. 12-1
System interface description 12-1 Interface buses 12-1 Address data cycles 12-2 Issue Cycles 12-2 Handshake Signals. 12-3 System Interface Protocols 12-3 Master slave states 12-4 Moving from master slave state. 12-4 External arbitration 12-4 Uncompelled change slave state. 12-4 Processor external requests. 12-5 Processor Request Rules. 12-5 Processor requests. 12-6 Processor read request 12-7 Processor write request. 12-7 External requests. 12-7 External read request 12-9 External write request. 12-9 System interface endianness 12-9 System interface cycle time. 12-9 Release Latency. 12-9 64-bit system interface addresses. 12-10 Addressing conventions 64-bit wide interface 12-10 32-bit system interface addresses. 12-10 Addressing conventions 32-bit wide interface 12-10 Read Interface Chapter Read response 13-1 Handling requests 13-1 Load miss 13-2 Store miss. 13-2 Store 13-3 Uncached loads. 13-3 CACHE operations 13-3 Load linked/Store conditional operation 13-4 Processor read protocols 13-4 Processor read request 13-4 Processor read request protocol steps. 13-5 External instruction read response time 13-6 Instruction read latency steps system clock 13-6 External data read response time 13-6 Data read latency steps system clock 13-7 Example Ddata single read with zero wait-state. 13-7 External cycles read latency. 13-7 Read response protocol 13-8 Data rate control. 13-10 Read data pattern. 13-10 64-bit mode. 13-11 64-bit mode block read operation 13-11 64-bit mode single (Uncached) read operation. 13-11 32-bit mode. 13-12 32-bit mode block read operation 13-12 32-bit mode single (Uncached) read operation. 13-13 Subblock ordering 13-13 Generating subblock order doublewords. 13-15 Generating subblock order words. 13-16 Interface commands data identifiers 13-17
Command data identifier syntax 13-17 System interface command syntax. 13-17 Read requests 13-18 System interface data identifier syntax. 13-19 Noncoherent data 13-19 Data identifier definitions 13-19 Write Interface .Chapter Processor write protocols 14-1 Processor write-request protocol. 14-2 Processor single-write request 14-2 R4000 compatible write mode. 14-2 Write reissue. 14-3 Pipelined write 14-4 Processor block-write request 14-4 Write data transfer patterns 14-5 Processor request flow control. 14-6 64-bit mode. 14-7 64-bit mode block write operation. 14-7 64-bit mode single (Uncached) write operation 14-7 R4000 family compatible write mode. 14-7 Write reissue. 14-8 Pipelined writes 14-8 32-bit mode. 14-9 32-Bit mode block write operation 14-9 32-bit mode single (Uncached) write operation 14-10 R4000 family compatible write mode. 14-10 Write reissue. 14-11 Pipelined writes 14-11 Sequential ordering 14-12 Interface commands data identifiers 14-15 Command data identifier syntax 14-16 System interface command syntax. 14-16 Write requests 14-16 System interface data identifier syntax. 14-18 Data identifier definitions 14-18 External Request Interface. Chapter Processor external request protocols 15-2 External request protocols. 15-3 External arbitration protocol. 15-3 External read request protocol 15-4 External null request protocol 15-5 External write request protocol 15-6 Interface commands data identifiers 15-6 Command data identifier syntax 15-7 System interface command syntax. 15-7 Null Requests 15-7 System interface data identifier syntax. 15-8 Noncoherent data 15-8 Data identifier definitions 15-8 System interface addresses 15-9 Addressing conventions 15-9 Processor internal address map. 15-10 Processor Interrupts Chapter Asserting interrupts. 16-1 Processor Error Checking. Chapter Parity error detection 17-1
System interface. 17-2 System interface command 17-2 Standard JTAG Support Interface .Chapter Test access port (TAP) interface. 18-2 controller. 18-2 controller state assignments. 18-3 Instruction Register (IR) 18-4 Test Data Register (DR). 18-5 Bypass Register 18-5 Boundary-Scan Register 18-6 Device Identification Register 18-6 Cache Operations' Timing. Appendix Caveats about cache operations.A-1 Cache operations tables. Fill_I equation definitions. Entering standby mode Appendix Standby Mode Operation.B-1 Coprocessor Hazards Appendix Index Index
Table Table Table Table Table Table Table Table Table Table Table Table Table 2.10 Table 2.11 Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 6.10 Table 6.11 Table 6.12 Table Table Table Table Table Summary Features RISCore4000 Family .1-2 System Control Coprocessor (CP0) Register Definitions.1-8 Single Double Precision Latency Cycles.1-9 RISCore4000 Integer Multiply/Divide Operation .2-4 Instruction Set: MIPS /MIPS 2/MIPS Load Store Instructions .2-6 Instruction Set: MIPS /MIPS MIPS Arithmetic Instructions (ALU Immediate) .2-7 Instruction Set: Arithmetic (3-Operand, R-Type).2-7 Instruction Set: MIPS MIPS MIPS Multiply Divide Instructions .2-8 Instruction Set: Jump Branch Instruction (Page .2-8 Instruction Set: Shift Instruction .2-10 Instruction Set: Coprocessor Instructions.2-10 Instruction Set: Special Instructions. 2-11 MIPS 2/MIPS Exception Instructions. 2-11 RC64474/RC64475 Instructions. 2-11 Pipeline Exceptions .3-6 Pipeline Interlocks .3-6 32-bit 64-bit User Mode Segments.4-5 32-bit 64-bit Supervisor Mode Segments .4-7 32-bit Kernel Mode Segments.4-9 64-bit Kernel Mode Segments.4-10 Cacheability Coherency Attributes 4-11 Page Coherency Values .5-3 Index Register Field Descriptions.5-4 Random Register Field Descriptions.5-5 Mask Field Values Page Sizes .5-5 Wired Register Field Descriptions .5-6 PRId Register Fields Config Register Fields .5-8 Cache Register Fields .5-9 Translation Lookaside Buffer Instructions 5-11 Exception Processing Registers (Page 2).6-1 Context Register Fields .6-2 Status Register Fields .6-5 Cause Register Fields .6-7 Cause Register ExcCode Field .6-7 XContext Register Fields.6-9 Register Fields.6-9 CacheErr Register Fields .6-10 Exception Vector Base Addresses 6-13 Exception Vector Offsets 6-13 Exception Priority Order .6-13 List Exception Flowcharts.6-21 Floating-Point Control Register Assignments.7-3 FCR0 Register Fields .7-4 Control/Status Register Fields.7-5 Rounding Mode Decoding.7-6 Equations Calculating Values Single Double-Precision Floating-Point Format .7-7
Table Table Table Table Table 7.10 Table 7.11 Table 7.12 Table 7.13 Table 7.14 Table Table Table Table Table Table Table Table Table Table Table 10.1 Table 10.2 Table 11.1 Table 11.2 Table 11.3 Table 11.4 Table 11.5 Table 12.1 Table 13.1 Table 13.2 Table 13.3 Table 13.4 Table 13.5 Table 13.6 Table 13.7 Table 13.8 Table 13.9 Table 13.10 Table 13.11 Table 13.12 Table 13.13 Table 13.14 Table 13.15 Table 13.16 Table 13.17 Table 13.18 Table 14.1 Table 14.2 Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.7
Floating-Point Format Parameter Value Minimum Maximum Floating-Point Values. Binary Fixed-Point Format Fields Instruction Summary: Load, Move Store Instructions. Instruction Summary: Conversion Instructions Instruction Summary: Computational Instructions 7-10 Instruction Summary: Compare Branch Instructions 7-10 Mnemonics Definitions Compare Instruction Conditions 7-12 Floating-Point Operation Latencies 7-13 Default Exception Actions Exception-Causing Conditions RC64475 System Interface Signals. RC64474 RC64475 32-Bit Mode System Interface Signals Clock/Control Interface Signals Interrupt Interface Signals Initialization Interface Signals JTAG Interface Signals RC64475 Processor Signal Summary RC64474 RC64475 Processor Signal Summary RC64474/RC64475 Processor Signal Summary. 10-5 Boot-time Mode Stream (Page 10-9 RC64474/RC64475 Cache Attributes. 11-2 Primary I-Cache Field Descriptions 11-3 D-Cache Field Descriptions 11-4 Primary Cache States. 11-6 Coherency Attributes Processor Behavior. 11-8 Release Latency External Requests 12-10 Load Miss Primary Cache 13-2 Store Miss Primary Cache 13-3 System Interface Requests 13-4 Steps Single Read With Zero Wait-State 13-6 Steps Data Block Read With Zero Wait-State 13-7 Sequence Doublewords Transferred Using Subblock Ordering: Address 13-15 Sequence Doublewords Transferred Using Subblock Ordering: Address 112. 13-16 Sequence Doublewords Transferred Using Subblock Ordering: Address 13-16 Sequence Words Transferred Using Subblock Ordering: Address 0102 13-16 Sequence Words Transferred Using Subblock Ordering: Address 1102. 13-17 Encoding SysCmd (7:5) System Interface Commands 13-18 Encoding SysCmd (4:3) Read Requests. 13-18 Encoding SysCmd (2:0) Block Read Request. 13-18 Doubleword, Word, Partial-Word Read Request Data Size Encoding SysCmd (2:0). 13-19 Processor Data Identifier Encoding SysCmd (7:3) 13-20 External Data Identifier Encoding SysCmd (7:3) 13-20 Partial Word Transfer Byte Lane Usage-64-Bit Mode 13-21 Partial Word Transfer Byte Lane Usage-32-Bit Mode 13-22 System Interface Requests 14-1 Transmit Data Rates Patterns 64-Bit Mode 14-5 Transmit Data Rates Patterns 32-Bit Mode 14-6 Partial Word Transfer Byte Lane Usage 14-14 Partial Word Transfer Byte Lane Usage-32-Bit Mode 14-15 Encoding SysCmd (7:5) System Interface Commands 14-16 Write Request Encoding SysCmd (4:3) 14-17
Table 14.8 Table 14.9 Table 14.10 Table 14.11 Table 14.12 Table 14.13 Table 14.14 Table 14.15 Table 15.1 Table 15.2 Table 15.3 Table 16.1 Table 16.2 Table Table Table
Block Write Request Encoding SysCmd (2:0) 14-17 Doubleword, Word, Partial-Word Write Request Data Size Encoding SysCmd (2:0) 14-17 Processor Data Identifier Encoding SysCmd(7) 14-18 System Interface Requests 15-3 Encoding SysCmd (7:5) System Interface Commands External Null Request Encoding SysCmd (4:3). 15-8 Processor Data Identifier Encoding SysCmd (7:3) 15-9 External Data Identifier Encoding SysCmd (7:3) 15-9 Even Parity Bits Various Data Values 17-1 Error Checking Correcting Summary Internal Transactions 17-2 Error Checking Correcting Summary External Transactions. 17-3 JTAG Interface Descriptions Type 18-1 Instruction Register Definition 18-5 Primary Data Cache Operations.A-2 Primary Instruction Cache Operations.A-3 Coprocessor Hazards .C-1
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 5.10 Figure 5.11 Figure 5.12 Figure 5.13 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 6.10 Figure 6.11 Figure 6.12 RC64474/RC64475 Functional Block Diagram .1-3 RC64474/RC64475 registers .1-4 Big-Endian Byte Ordering .1-5 Little-Endian Byte Ordering .1-5 Little-Endian Data Doubleword .1-6 Big-Endian Data Doubleword .1-6 Big-Endian Misaligned Word Addressing .1-7 Little-Endian Misaligned Word Addressing .1-7 Typical System Block Diagram .1-12 Instruction Formats .2-1 Byte Access within Doubleword .2-3 RISCore4000 5-stage Instruction Pipeline .3-1 Pipeline Activities .3-3 Pipeline Branch Delay .3-4 Pipeline Load Delay .3-4 Correspondence Pipeline Stage Interlock Condition .3-5 Exception Detection .3-7 Data Cache Miss .3-7 Instruction cache miss .3-8 Overview Virtual-to-Physical Address Translation .4-2 32-bit Virtual Address Translation .4-3 64-bit Virtual Address Translation .4-4 User Mode Virtual Address Space .4-5 Supervisor Mode Virtual Address Space .4-6 Kernel Mode Address Space .4-8 Registers .5-1 Format Entry .5-2 Fields PageMask EntryHi Registers .5-2 Fields EntryLo0 EntryLo1 Registers .5-3 Index Register .5-4 Random Register .5-4 Wired Register Boundary .5-6 Wired Register .5-6 Processor Revision Identifier Register Format .5-7 Config Register Format .5-7 LLAddr Register Format .5-9 TagLo TagHi Register (P-cache) Formats .5-9 Address Translation .5-10 Context Register Format .6-2 BadVAddr Register Format .6-2 Count Register Format .6-3 Compare Register Format .6-3 Status Register .6-4 Cause Register Format .6-6 Register Format .6-8 XContext Register Format .6-8 Register Format .6-9 CacheErr Register Format .6-10 ErrorEPC Register Format 6-11 Reset Exception Processing 6-11
Figure 6.13 Figure 6.14 Figure 6.15 Figure 6.16 Figure 6.17 Figure 6.18 Figure 6.19 Figure 6.20 Figure 6.21 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6 Figure 10.7 Figure 10.8 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8 Figure 11.9 Figure 11.10 Figure 11.11 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 Figure 12.9 Figure 12.10 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4
Cache Error Exception Processing 6-12 Soft Reset Exception Processing 6-12 General Exception Processing (Except Reset, Soft Reset, NMI, Cache Error) 6-12 General Exception Handler (HW) 6-22 General Exception Servicing Guidelines (SW) 6-23 TLB/XTLB Miss Exception Handler (HW) 6-24 TLB/XTLB Exception Servicing Guidelines (SW) 6-25 Cache Error Exception Handling (HW) Servicing Guidelines (SW). 6-26 Reset, Soft Reset Exception Handling (HW) Servicing Guidelines (SW) 6-27 Functional Block Diagram Floating-Point Unit (FPU) Registers Implementation/Revision Register Control/Status Register Assignments Control/Status Register Cause, Flag, Enable Fields Single-Precision Floating-Point Format Double-Precision Floating-Point Format Binary Fixed-Point Format Instruction Pipeline 7-12 Control/Status Register Exception/Flag/Trap/Enable Bits RC64474/RC64475 Logic Diagram Signal Transitions 10-1 Clock-to-Q Delay 10-1 RC64474/RC64475 System Clocks Data Setup, Output, Hold timing 10-2 Passive Components 10-3 RC64474/RC64475 Processor System 10-4 Power-on Reset 10-7 Cold Reset 10-7 Warm Reset 10-8 Logical Hierarchy Memory 11-1 Cache Support RC64474/RC64475 11-3 RC64474/RC64475 Primary I-Cache Line Format 11-3 Primary D-Cache Line Format 11-4 Conceptual Primary Cache Lookup Sequence 11-5 Primary Cache Data Organization 11-5 Primary Data Cache State Diagram 11-7 Synchronization with Test-and-Set .11-11 Synchronization Using Counter 11-12 Test-and-Set using 11-13 Counter Using 11-14 System Interface Buses 12-2 State RdRdy* Signal Read Requests 12-2 State WrRdy* Signal Write Requests 12-3 System Interface Register-to-Register Operation 12-4 Requests System Events 12-5 Back-to-Back Write Cycle Timing (RISCore4000 family) 12-6 Processor Requests 12-6 Processor Request 12-7 External Requests 12-8 External Requests 12-8 Read Response 13-1 Processor Read Request Protocol 13-5 Uncached Read-External Cycles 13-7 Processor Read Cycle 13-8
Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Figure 13.9 Figure 13.10 Figure 13.11 Figure 13.12 Figure 13.13 Figure 13.14 Figure 13.15 Figure 13.16 Figure 13.17 Figure 13.18 Figure 13.19 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Figure 14.7 Figure 14.8 Figure 14.9 Figure 14.10 Figure 14.11 Figure 14.12 Figure 14.13 Figure 14.14 Figure 14.15 Figure 14.16 Figure 14.17 Figure 14.18 Figure 14.19 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Figure 15.7 Figure 15.8 Figure 15.9 Figure 15.10 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 18.1 Figure 18.2 Figure 18.3 Figure
Processor Word Read Request Followed Word Read Response (64-bit interface) 13-9 Block Read Response With Zero Wait-State (64-bit interface) 13-9 Block Read Transaction With Wait-State (64-bit interface) 13-10 Read Response, Reduced Data Rate, System Interface Slave State (64-bit interface) 13-10 Block Read Transaction With Wait-State 13-11 64-Bit Uncached Read-External Cycles 13-12 Block Read Transaction With Wait-State 13-12 32-Bit Mode Uncached Read Single Word 13-13 32-Bit Mode Uncached Read Double Word 13-13 Retrieving Data Block Sequential Order 13-14 Retrieving Data Subblock Order 13-14 Retrieving Data Subblock Order 13-15 System Interface Command Syntax Definition 13-17 Read Request SysCmd Definition 13-18 Data Identifier SysCmd Definition 13-19 Processor Noncoherent Word Write Request Protocol 14-2 R4000 Compatible Write Mode 14-3 Write Reissue 14-3 Pipelined Writes 14-4 Processor Noncoherent Block Write Request Protocol 14-5 Processor Write Requests, Second Write Delayed Assertion WrRdy* 14-6 Processor Noncoherent Block Write Request Protocol 14-7 R4000 Family Compatible Write Mode 14-8 Write Reissue 14-8 Pipelined Writes 14-9 Processor Noncoherent Block Write Request Protocol 14-10 R4000 Family Compatible Write Protocol 14-10 Write Reissue 14-11 Pipelined Writes 14-11 Transferring Data Block Sequential Order 14-12 Transferring Data Subblock Order 14-13 System Interface Command Syntax Definition 14-16 Write Request SysCmd Definition 14-16 Data Identifier SysCmd Definition 14-18 External Requests 15-1 Processor Control External Request, through arbitration signals 15-1 Read Response 15-2 Arbitration Protocol External Requests 15-4 External Read Request, System Interface Master State 15-5 System Interface Release External Null Request 15-5 External Write Request, with System Interface Initially Master State 15-6 System Interface Command Syntax Definition 15-7 Null Request SysCmd Definition 15-7 Data Identifier SysCmd Definition 15-8 Interrupt Register Bits Enables 16-1 RC64474/RC64475 Interrupt Signals 16-2 RC64474/RC64475 Nonmaskable Interrupt Signal 16-2 Masking RC64474/RC64475 Interrupts 16-3 Standard Boundary Scan Architecture 18-2 Controller State Diagram 18-3 Device Identification Register Format 18-6 Standby Mode Operation
Designed target applications that require high bandwidth, real-time response rapid data processing, Integrated Device Technology's (IDT) RC64474 RC64475 processors high performance devices that extend IDT's RISCore4000 processor family choices. IDT's RISCore4000 250MHz 64-bit execution core that utilizes 5-stage scalar pipeline. RISCore4000 implements MIPS-III Instruction Architecture (ISA) upwardly compatible with applications that earlier generation parts. core capable executing either big- littleendian byte ordering, without performance loss either mode. Implementation MIPS-III architecture results 64-bit operations, improved performance commonly used code sequences operating kernels faster execution floating-point intensive applications. resource dependencies made transparent programmer, insuring transportability around implementations MIPS ISA. RISCore4000 operate both 64-bit data, utilizing general-purpose registers (GPR) that used integer operations address calculation. Also, on-chip floating-point coprocessor adds floating-point registers floating-point control/status register. RC64474 RC64475 enhance IDT's entire RISCore4000 series through implementation features such boundary scan, facilitate board-level testing; enhanced timing protocols SyncDRAM, simplify system implementation improve performance; on-chip resources such larger caches translation lookaside buffer (TLB), higher level integration; tolerant I/Os, enable interfacing with earlier generation devices. RC64474 packaged 128-pin footprint package uses 32-bit external bus, offering ideal combination 64-bit processing power 32-bit low-cost memory systems. RC64475 packaged 208-pin footprint package uses full 64-bit external bus. RC64475 ideal applications requiring 64-bit performance 64-bit external bandwidth.
RC64474/475 bring high performance lower-cost systems, through separate 16KB on-chip two-way associative caches; minimized branch load delays through simple streamlined pipeline; 4GB/s aggregate bandwidth support system interface 1GB; simple input clock strategy; facilities such early restart data cache misses. RC64474/475 processors rated Dhrystone MIPS Million floating point operations second (MFLOP/s), Mhz. internal cache bandwidth these devices 3GB/s.
RC64474/475 application-software compatible with IDT's entire RISControllerseries embedded microprocessors, including devices from RISCore3000,RISCore4000, RISCore5000, RISCore32300 families. Also, through full socket compatibility, RC64474/475 offer direct migration path designs based IDT's RC4640 RC4650 processors. devices RISCore4000 family same protocols syntax, enabling range designs support chips.
64-bit RISCore4000 extensions 260MIPS @200MHz mflops, single precision only 8kB/8kB, 2-way, lockable 32-bit
64-bit RISCore4000 extensions 260MIPS @200MHz mflops, single precision only 8kB/8kB, 2way, lockable 64-bit
64-bit RISCore4000
64-bit RISCore4000
64-bit RISCore4000
Performance
260MIPS @200MHz mflops, single double precision 16kB/16kB, 2-way 64-bit
330MIPS @200MHz mflops, single double precision 16kB/16kB, 2way, lockable 32-bit, Superset compatible RC4640 3.3V, tolerant page Cache locking, JTAG, syncDRAM mode, 32-bit external
330MIPS @200MHz mflops, single double precision 16kB/16kB, 2way, lockable 64-bit, Superset compatible RC4650 3.3V, tolerant page Cache locking, JTAG, syncDRAM mode, option
Caches External
Voltages Packages Features
3.3V PQFP Base-Bounds Cache locking, on-chip MAC, 32bit external
3.3V MQUAD Base-Bounds Cache locking, on-chip MAC, 32-bit option
3.3V MQUAD page Large Primary caches
Table Summary Features RISCore4000 Family
RC64474 RC64475 uniquely achieve high performance levels, while providing costeffective solutions, through features such those listed below. addition, array hardware software tools available assist system designers rapid development RC64474 RC64475 based systems, which allows wide variety customers take full advantage processor's high-performance features while addressing today's aggressive time-to-market demands. High performance 64-bit microprocessor, based RISCore4000 Minimized branch load delays, through streamlined 5-stage scalar pipeline. Single double precision floating-point unit peak MFLOP/s Dhrystone MIPS Flexible RC4700 compatible On-chip TLB, virtual-to-physical address mapping On-chip two-way associative caches 16KB instruction cache (I-cache) 16KB data cache (D-cache) Write-through write-back support Critical word first with early restart I-cache D-cache locking facility, provides improved real-time support Enhanced, flexible interface allows simple, low-cost design 64-bit Interface option, 1GB/s bandwidth support 32-bit Interface option, 5GB/s bandwidth support SDRAM timing protocols RC4000/RC5000 family compatibility Implements MIPS-III Instruction Architecture (ISA) 3.3V with tolerant Software compatible with entire RISController Series Embedded Microprocessors
Industrial temperature range support
Active power management Powers down inactive units
Ensures device cost through lower-cost package options Superset compatibility between RC64474 RC4640 Superset compatibility between RC64475 RC4650 RC64474 available 128-pin footprint package, 32-bit only systems RC64475 available 208-pin PQUAD package, full 64/32 systems Simplified board-level testing, through full JTAG boundary scan Windows® compliant
Figure contains illustration functional elements RC64474/RC64475 processors. overview these elements follows. Operational details provided throughout manual.
64-bit RISCore4000
System Control Coprocessor (CPO)
Single/Double Precision
Control Data Instruction
16KB Instruction Cache (Lockable)
32-/64-bit Synchronized System Interface
16KB Data Cache (Lockable)
Figure RC64474/RC64475 Functional Block Diagram
Similar RISCore3000 RISCore32300 families, RISCore4000 (RC4000) execution core uses 5-stage scalar pipeline, which achieves instruction execution rate approaching instruction cycle. simplicity this pipeline allows RC64474/475 lower cost, lower powered processors than super-scalar super-pipelined processors: unlike superscalar processors, applications that have large data dependencies require great deal load/stores still achieve levels that close peak performance processor.
Consistent with MIPS-III ISA, execution core operate both 32-or 64-bit data, using thirty-two 64-bit general purpose registers, which used scalar integer operations address calculation. register file consists read ports write port fully bypassed, minimize operation latency within pipeline. registers shown Figure 1.2.
General Purpose Registers Multiply Divide Registers
Program Counter
Figure RC64474/RC64475 registers
register hardwired value zero used target register instruction whose result discarded. This register also used source when zero value needed. Jump Link (JAL) series instructions register implicit return destination address register. registers also include three special purpose registers-PC, Program Counter register that contains address instruction program being executed. Multiply Divide register, higher result, Multiply Divide register, lower result. These Multiply Divide registers will store product integer multiply operations, quotient remainder integer divide operations. Note that RC64474/475 processors have Program Status Word (PSW) register. function covered Status Cause registers incorporated within System Control Coprocessor (CP0). registers discussed detail Chapter
MIPS-ISA instructions 32-bits long grouped into three instruction formats: immediate (I-type), jump (J-type), register (R-type). Instruction decoding sped through limiting number formats three, more complicated (and less frequently used) operations addressing modes synthesized compiler, using sequences these same basic instructions. instruction sets divided further into following groups: Load Store instructions move data between memory general registers. They immediate (I-type) instructions, since only addressing mode supported base register plus 16-bit, signed immediate offset. Computational instructions perform arithmetic, logical, shift, multiply, divide operations values registers. They include register (R-type, which both operands result stored registers) immediate (I-type, which operand 16-bit immediate value) formats. Jump Branch instructions change control flow program. Jumps always made paged, absolute address formed combining 26-bit target address with high-order bits Program Counter (J-type format) register address (R-type format). Branches have 16-bit offsets relative program counter (I-type). Jump Link instructions save their return address register Coprocessor instructions perform operations coprocessors. Coprocessor load store instructions I-type.
Coprocessor (system coprocessor) instructions perform operations registers control memory management exception handling facilities processor standby mode power management. Special instructions perform system calls breakpoint operations. These instructions always R-type. Exception instructions cause branch general exception-handling vector based upon result comparison. These instructions occur both R-type (both operands result registers) I-type (one operand 16-bit immediate value) formats. Chapter contains more details MIPS instruction formats operations mentioned above includes instruction summary tables.
RC64474/475 processors four data formats: 64-bit doubleword, 32-bit word, 16-bit halfword, 8-bit byte. Byte ordering within each larger data formats-halfword, word, doubleword-can configured either big- little-endian order. Figure Figure show ordering bytes within words ordering words within multiple-word structures big-endian little-endian conventions. shown, when RC64474/475 processors configured big-endian system, byte most-significant
(left most) byte, thereby providing compatibility with 68000 conventions. Figure illustrates big-endian configuration.
Higher Address
Word Address
Lower Address
Figure Big-Endian Byte Ordering
When configured little-endian system, byte always least-significant (rightmost) byte, which compatible with iAPX conventions. Figure illustrates this configuration.
Higher Address
Word Address
Lower Address
Figure Little-Endian Byte Ordering
Throughout this text, always least-significant (rightmost) bit; thus, designations always little-endian (although instructions explicitly designate positions within words).
Endianness configuration
refers location byte within multi-byte data structure.
Figure Figure show little-endian big-endian byte ordering doublewords.
Most-significant byte
Least-significant byte Word
Byte Halfword Byte
Bits Byte
Figure Little-Endian Data Doubleword
Most-significant byte
Least-significant byte Word
Byte Halfword Byte Bits Byte
Figure Big-Endian Data Doubleword
uses byte addressing halfword, word, doubleword accesses with following alignment constraints: Halfword accesses must aligned even byte boundary 4.). Word accesses must aligned byte boundary divisible four 8.). Doubleword accesses must aligned byte boundary divisible eight 16.). following special instructions load store words aligned 4-byte (word) 8-word (doubleword) boundaries used pairs provide addressing misaligned words: Load word left (LWL) Load word right (LWR) Store word left (SWL) Store word right (SWR) Load doubleword left (LDL) Load doubleword right (LDR) Store doubleword left (SDL) Store doubleword right (SDR) Addressing misaligned data incurs additional instruction cycle over that required addressing aligned data. This extra cycle because extra instruction allowed instruction "pair" (for example, form pair). Also note that moves unaligned data same rate hardware mechanism.
Figure Figure show access misaligned word that byte address big- little-endian configurations.
Higher Address
Lower Address
Figure Big-Endian Misaligned Word Addressing
Higher Address Lower Address
Figure Little-Endian Misaligned Word Addressing
RC64474/RC64475's execution core defines three coprocessors, designated through follows: Coprocessor (CPO)-also referred System Control Coprocessor-supports virtual memory system exception handling. Coprocessor (CP1) implements MIPS floating-point instruction set.
translates virtual addresses into physical addresses manages exceptions transitions between kernel, user supervisor states. also controls cache subsystem, well providing diagnostic control error recovery facilities. also used control power management system RC64474/RC64475. This standby mode used reduce power consumption CPU's internal core. Standby mode entered executing WAIT instruction with SysAD idle exited interrupt.
registers described Table manipulate memory management exception handling capabilities CPU2.
Number 18-19 21-25 Register Name Register Type Index Random EntryLo0 EntryLo1 Context PageMask Wired Reserved BadVAddr Count EntryHi Compare Cause PRId Config CAlg Reserved XContext Reserved CacheErr TagLo TagHi ErrorEPC Reserved Table System Control Coprocessor (CP0) Register Definitions Exception Processing Exception Processing Memory Management Memory Management Exception Processing Secondary-cache error checking correcting (ECC) Primary parity Cache Error Status register Cache register Cache register Error Exception Program Counter Exception Processing Pointer kernel virtual table 64-bit address spaces. Exception Processing Exception Processing Memory Management Exception Processing Exception Processing Exception Processing Exception Processing Memory Management Memory Management Memory Management virtual address Timer Count High half entry Timer Compare Status register Cause last exception Exception Program Counter Processor Revision Identifier Configuration register Cache attributes control Memory Management Memory Management Memory Management Memory Management Exception Processing Memory Management Memory Management Description Provides User Instruction address space Base Pseudorandom pointer into array (read only) half entry even virtual page (VPN) half entry virtual page (VPN) Pointer kernel virtual page table entry (PTE) 32-bit address spaces Page Mask Number wired entries
floating-point coprocessor, CP1, includes floating-point registers floating-point control/status register. forms "seamless" interface with integer unit, decoding executing instructions parallel with integer unit.
results access reserved undefined register undefined. exception result.
floating-point execution units support single- double precision arithmetic, specified IEEE Standard 754. execution unit broken into separate multiply unit combined add/convert/divide/square root unit. Overlap multiplies add/subtract supported. multiplier partially pipelined, allowing multiply begin every cycles. Fully precise floating-point exceptions maintained while allowing both overlapped pipelined operations. Precise exceptions extremely important mission-critical environments highly desirable debugging environment. floating-point unit's operation includes floating-point add, subtract, multiply, divide, square root, conversion between fixed-point floating-point format, floating-point compare. These operations comply with IEEE Standard 754. Table gives latencies some floating-point instructions internal processor cycles.
Operation SQRT FLOAT LWC1,LDC1 SWC1, SDC1
Single Precision Latency
Double Precision Latency
Table Single Double Precision Latency Cycles
Virtual-to-physical address mapping available system software provide secure environment user processes. Bits status register determine mode operation. RISCore4000 user, supervisor kernel modes operation available. Typically used application's programs, RISCore4000's user mode provides single, uniform virtual address space 256GB (2GB when Status.UX When operating kernel mode- typically used exception handling operating system kernel functions-four distinct virtual address spaces, totalling 1024GB (4GB when Status.KX simultaneously available differentiated high-order bits virtual address. RC64474/475 processors also support supervisor mode which virtual address space 256.5GB (2.5GB when Status.SX divided into three regions based high-order bits virtual address. When uses 64-bit virtual addresses, address space layouts upwardly compatible extension 32-bit virtual address space layout.
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fast virtual-to-physical address decoding, RC64474/RC64475 uses large, fully associative TLB, which maps virtual pages their corresponding physical addresses. organized pairs even-odd entries, maps virtual address address space identifier into large, 64GB physical address space. mechanisms provided assist controlling amount mapped space, replacement characteristics various memory regions. First, page size configured-on per-entry basis-to page size 16MB multiples register loaded with page size mapping, that size entered into when entry written. Thus, operating systems provide special purpose maps; example, typical frame buffer memory mapped using only entry. second mechanism controls replacement algorithm when miss occurs. RC64474/475 provides random replacement algorithm select entry written with mapping; however, processor provides mechanism whereby system specific number mappings locked into TLB, thus avoid being randomly replaced. This facilitates design real-time systems, allowing deterministic access critical software. joint also contains information control cache coherency protocol each page. Specifically, each page attribute bits determine whether coherency algorithm uncached, non-coherent write-back, non-coherent write-through write-allocate, non-coherent write-through write-allocate, sharable, exclusive, update. Non-coherent write-back typically used both code data RC64474/475; write-through modes support more efficient frame buffer accesses than original MIPS R4000. coherent modes supported R4000 compatibility generate different transaction types system interface; however, hardware based cache coherency supported.
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RISCore4000 also incorporates 2-entry instruction TLB. Each entry maps page. instruction improves performance allowing instruction address translation occur parallel with data address translation. When miss occurs instruction address translation, leastrecently used ITLB entry filled from JTLB. operation ITLB invisible user.
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RISCore4000 also incorporates 4-entry data TLB. Each entry maps page. data improves performance allowing data address translation occur parallel with data address translation. When miss occurs data address translation, DTLB filled from JTLB. DTLB refill pseudo-LRU: least recently used entry least recently used half filled. operation DTLB invisible user.
keep RISCore4000's high-performance pipeline full operating efficiently, on-chip instruction data caches that accessed single processor cycle incorporated. Each cache 64-bit data path accessed parallel. cache subsystem provides integer floating-point units with aggregate bandwidth second 250MHz.
RC64474/475 incorporate two-way associative on-chip instruction cache. This virtually indexed, physically tagged I-cache 16KB size word parity protected. Because cache virtually indexed, virtual-to-physical address translation occurs parallel with cache access, thus further increasing performance allowing these operations occur simultaneously. holds 24-bits physical address valid parity protected.
instruction cache 64-bits wide refilled accessed single processor cycle. Instruction fetches require only bits cycle, peak instruction bandwidth 1GB/sec 250MHz. Sequential accesses take advantage 64-bit fetch reduce power dissipation, cache miss refill writes bits cycle minimize cache miss penalty. maximize performance, line size eight instructions bytes). addition, contents instruction cache (set "A") "locked" setting register. Locking prevents contents from being overwritten subsequent cache miss; refill occurs then only into "set This operation effectively "locks" time critical code into set, while allowing other service other instruction streams normal fashion. Thus, benefits cached performance achieved, while deterministic real-time response preserved.
fast, single cycle data access, RC64474/475 include 16KB on-chip data cache that two-way associative with fixed 32-byte (eight word) line size. Both D-cache I-cache accessed each pipeline cycle; thus, data bandwidth 2GB/sec MHz, addition 1GB/sec instruction bandwidth. data cache protected with byte parity protected with single parity bit. virtually indexed physically tagged allow simultaneous address translation data cache access. addition, contents data cache (set "A") "locked" setting register. Locking prevents contents from being overwritten subsequent cache miss; refill occurs then only into "set This operation effectively "locks" time critical code into set, while allowing other service other instruction streams normal fashion. Thus, benefits cached performance achieved, while deterministic real-time response preserved. Associated with data cache store buffer. When RISCore4000 executes store instruction, this single-entry buffer gets written with store data while comparison performed. matches, then data written into data cache next cycle that data cache accessed (the next non-load cycle). store buffer allows RISCore4000 execute store every processor cycle perform back-to-back stores without penalty.
Writes external memory-whether they cache miss write-backs, stores uncached write-through addresses-use on-chip write buffer. write buffer holds four 64-bit address 64-bit data pairs. entire buffer used data cache write-back allows processor proceed parallel with memory updates.
RC64475 supports 64-bit system interface that compatible with RC4650 system interface. This interface operates from input Reference clock. system interface consists 64-bit address/data with eight check bits 9-bit command bus. Eight handshake signals interrupt inputs included. interface simple timing specification capable transferring data between processor memory peak rate 1GB/sec. Additionally, RC64474/475 supports boot-time option system interface bits wide, using basically same protocols 64-bit system. This feature allows system designer reduce costs overall memory system without sacrificing computational performance. RC64474/475 clocking interface allows easily mated with external reference clocks. input clock reference clock, between 125MHz. on-chip phase-locked-loop (PLL) generates pipeline clock (PClock) through multiplication system interface clock values 2,3,4,5,6,7 defined system reset. This allows pipeline clock implemented significantly higher frequency than system interface clock.
RC64474 supports 32-bit system interface only.
##*#
System Address Data (SysAD) used transfer addresses data between processor rest system. During 64-bit operation, SysAD transfers protected with 8-bit parity check bus, SysADC. When initialized 32-bit operation, SysAD viewed 32-bit multiplexed that protected parity check bits. allow easier interfacing memory systems varying frequencies, RC64474/475 system interface configurable. frequencies reference timings RC64474/475 derived from input clock, rate which transmits data system interface programmable boot-time mode control bits. rate which processor receives data fully controlled external device. Therefore, either cost interface-requiring read write buffering-or faster, high performance interface designed communicate with RC64474/475 devices. Again, system designer flexibility make these price/performance trade-offs.
RC64474/475 interfaces have 9-bit bidirectional System Command (SysCmd) bus, which indicates whether SysAD carries address data item. RC64474/475 initiates processor requests that responded external device. External requests issued external device require RC64474/475 devices respond. RC64474/475 support single data (one eight byte) 8-word block transfers SysAD bus. case single-data transfer, low-order address bits provide byte address transfer, SysCmd indicates number bytes being transferred. Choosing 64-bit wide system interface dictates whether cache line block transaction requires doubleword data cycles single word cycles, well whether single data transfer-larger than bytes-must divided into smaller transfers.
facilitate discrete interface SDRAM, RC64474/475 interface enhanced with programmable delay that inserted between write address write data, during write cycles (for both block non-block writes). delay defined MasterClock cycles activated controlled through mode (17:15) settings selected during reset initialization sequence. `000' setting provides same write operations timing RC4640, RC4650, RC4700 RC5000 processors. Figure shows typical system using RC64474/475. this example, there SDRAM boot EPROM.
Address Boot SDRAM Control
SCSI
ENET
RC64474/ RC64475
Control Control
Memory Controller
Figure Typical System Block Diagram
RC64474/RC64475 system interface consists following handshake signals: RdRdy*, WrRdy*, ExtRqst*, Release*, ValidOut*, ValidIn* external device uses RdRdy* WrRdy* indicate RC64474/475 readiness accept read write transaction. read write requests, RC64474/475 samples RdRdy* WrRdy* before deasserting address. ExtRqst* Release* used transfer control SysAD SysCmd buses between processor external device. When external device requires control interface, asserts ExtRqst*. release system interface slave state, RC64474/475 responds asserting Release*. RC64474/475 external device, respectively, ValidOut* ValidIn* indicate that there valid command data SysAD SysCmd buses. When RC64474/475 driving these buses with valid command data, asserts ValidOut*. external device drives ValidIn* when control buses driving valid command data.
RC64474/475 require non-overlapping system interface, compatible with RC4640/ RC4650. This means that only processor request outstanding time that request must serviced external device before RC64474/475 issues another request. RC64474/475 issue read write requests external device, external device issue read write requests processors. RC64474/475 devices assert ValidOut* while simultaneously driving address read command SysAD SysCmd buses. system interface RdRdy* Read transactions asserted, then processors tristate their drivers release system interface slave state asserting Release*. external device then begin sending data RC64474/475.
RC64474/475 implement additional write protocols that double effective write bandwidth. write re-issue repeat rate optional cycles write. write issues WrRdy* asserted cycles earlier remains asserted issue cycle. WrRdy* does remain asserted, last write will re-issue. Pipelined writes have same 2-cycle write repeat rate issue additional write after WrRdy* de-asserts.
RC64474/475 responds requests issued external device. These requests take several forms: external device need supply data response RC64474/475 read request need obtain system interface control access other resources that that bus. Read Response Null external requests both supported.
#$The boot-time mode control interface initializes fundamental processor modes. boot-time mode control interface serial interface that operates very frequency (MasterClock divided 256). This low-frequency operation allows initialization information kept low-cost EPROM; alternatively, twenty-or-so bits could generated system interface ASIC simple PAL. initialize fundamental operation modes immediately after VCCOK signal asserted, processor reads serial stream bits. After initialization complete, processor continues drive serial clock output, further initialization bits read.
This chapter provides general overview three instruction formats MIPS architecture: Immediate, Jump, Register. details specific RISCore4000 instruction, refer MIPS Microprocessor Family Software Reference Manual.
Each instruction consists single 32-bit word, aligned word boundary. There three instruction formats: Immediate (I-type) Jump (J-type) Register (R-type) Limiting number instruction formats three simplifies instruction decoding (thus enable higher frequency operation) allows compiler synthesize more complicated (and less frequently used) operations addressing modes. Figure illustrates three instruction formats MIPS architecture.
immediate
target
funct
Figure: immediate target funct
6-bit operation code 5-bit source register specifier 5-bit target (source/destination) register branch condition 16-bit immediate value, branch displacement address displacement 26-bit jump target address 5-bit destination register specifier 5-bit shift amount 6-bit function field
Figure Instruction Formats
Note that MIPS architecture, coprocessor instructions implementation-dependent. Refer MIPS Microprocessor Family Software Reference Manual details individual Coprocessor instructions.
Load store immediate (I-type) instructions that move data between memory general registers. only addressing mode that load store instructions directly support base register plus 16-bit signed immediate offset.
load instruction that does allow result used instruction immediately following called delayed load instruction. instruction slot immediately following this delayed load instruction referred load delay slot. RISCore4000, instruction immediately following load instruction request contents loaded register, however, such cases, hardware interlocks insert additional real cycles. Consequently, scheduling load delay slots desirable, both performance processor compatibility. However, scheduling load delay slots absolutely required.
Access type indicates size RC64474/475 processor data item loaded stored, load store instruction opcode. Memory access types defined Appendix MIPS Microprocessor Family Software Reference Manual. Regardless access type byte ordering (endianness), address given specifies loworder byte addressed field. big-endian configuration, low-order byte most-significant byte; little-endian configuration, low-order byte least-significant byte. access type-together with three low-order bits address-define bytes accessed within addressed doubleword, which shown Figure 2.2. Only combinations shown this table permissible. Other combinations will cause address error exceptions.
Bytes Accessed
Access Type Mnemonic (Value) Doubleword Septibyte
Order Address Bits
Endian (63-31-0) Byte
Little Endian (63-31-0) Byte
Sextibyte
Quintibyte
Word
Triplebyte
Halfword
Byte
Figure Byte Access within Doubleword
Computational instructions either register (R-type) format, which both operands registers, immediate (I-type) format, which operand 16-bit immediate. Computational instructions perform following operations register values: arithmetic logical shift multiply divide
Arithmetic, logical, shift, multiply divide operations into following four categories computational instructions: Immediate instructions three-Operand Register-Type instructions shift instructions multiply divide instructions
Operands 32-bit operand opcodes must sign-extended form. 32-bit operand opcodes include non-doubleword operations, such ADD, ADDU, SUB, SUBU, ADDI, SLL, SRL, SRA, SLLV, etc. result operations that incorrect sign-extended 32-bit values unpredictable.
necessary, allow complete execution multiply divide instructions, RC64474/475 hardware interlocks. example, MFHI MFLO instructions1 interlocked that attempt read execute them before prior completion previously issued multiply divide instructions will delayed. Table gives number processor cycles (PCycles) required resolve interlock stall between various multiply divide instructions subsequent MFHI MFLO instruction. When reviewing Table 2.1, following definitions apply: Latency number clock cycles until result available. Repeat number clock cycles until instruction repeated. Stall number clock cycles will automatically stall.
Opcode MULT/U
Operand *Size 16-bit 32-bit
Latency
Repeat
Stall
DMULTU DIV, DIVU DDIV, DDIVU
Table RISCore4000 Integer Multiply/Divide Operation
Jump branch instructions change control flow program. jump branch instructions occur with delay instruction; that instruction immediately following jump branch (this known instruction delay slot) always executes while target instruction being fetched from storage
Subroutine calls high-level languages usually implemented with Jump Jump Link instructions, both which J-type instructions. J-type format, 26-bit target address shifts left bits combines with high-order bits current program counter form absolute address.
details instruction sets located Appendix MIPS Microprocessor Family Software Reference Manual Branch Likely exceptions this rule.
More
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Returns, dispatches, large cross-page jumps usually implemented with Jump Register Jump Link Register instructions, which both R-type instructions that take 32bit 64-bit byte address contained general purpose registers.
Branch instruction jump specified memory location architectural delay instruction. branch instruction target addresses computed adding address instruction delay slot 16-bit offset (shifts left bits sign-extended bits). When branch taken, instruction immediately following branch instruction, branch delay slot, executed before branch target instruction takes place. There versions Conditional branches, each treats instruction delay slot differently. "branch" instructions will execute instruction delay slot, "branch likely" instructions not. conditional branch likely taken, instruction delay slot nullified. regular conditional branches, delay slot always executed.
Special instructions allow software initiate traps. Trap instructions cause exceptions conditionally based upon result comparison. These special instructions always R-type. more information about special instructions, refer individual instruction described MIPS Microprocessor Family Software Reference Manual.
Exception instructions extensions MIPS ISA. more information about exception instructions, refer individual instruction described Appendix
manipulate memory management exception handling facilities processor, coprocessor instructions perform operations specifically System Control Coprocessor registers. Coprocessor loads stores I-type, coprocessor computational instructions have coprocessor-dependent formats. Individual coprocessor instructions described MIPS Micrprocessor Family Software Reference Manual.
Table through Table 2.11 lists instructions common MIPS R-Series processors, along with level which they first appeared. last column each table refers MIPS level which instruction first appeared. Table 2.11 shows instructions.
MIPS Level
OpCode SYNC
Note:
Description Load Byte Load Byte Unsigned Load Halfword Load Halfword Unsigned Load Word Load Word Left Load Word Right Store Byte Store Halfword Store Word Store Word Left Store Word Right Load Doubleword Load Doubleword Left Load Doubleword Right Load Linked Load Linked Doubleword Load Word Unsigned Store Conditional Store Conditional Doubleword Store Doubleword Store Doubleword Left Store Doubleword Right Sync
Tables through 1.17 this column refers level which instruction first appeared.
Table Instruction Set: MIPS /MIPS 2/MIPS Load Store Instructions
OpCode ADDI ADDIU SLTI SLTIU ANDI XORI DADDI DADDIU
Description Immediate Immediate Unsigned Less Than Immediate Less Than Immediate Unsigned Immediate Immediate Exclusive Immediate Load Upper Immediate Doubleword Immediate Doubleword Immediate Unsigned
MIPS Level
Table Instruction Set: MIPS /MIPS MIPS Arithmetic Instructions (ALU Immediate)
OpCode ADDU SUBU SLTU DADD DADDU DSUB DSUBU
Description Unsigned Subtract Subtract Unsigned Less Than Less Than Unsigned Exclusive Doubleword Doubleword Unsigned Doubleword Subtract Doubleword Subtract Unsigned
MIPS Level
Table Instruction Set: Arithmetic (3-Operand, R-Type)
OpCode MULT MULTU DIVU MFHI MTHI MFLO MTLO DMULT DMULTU DDIV DDIVU
Description Multiply (result HI/LO) Multiply Unsigned (result HI/LO) Divide Divide Unsigned Move From Move Move From Move Doubleword Multiply (Result Hi/Lo) Doubleword Multiply Unsigned (Result Hi/Lo) Doubleword Divide Doubleword Divide Unsigned
MIPS Level
Note: These IDT-proprietary extensions MIPS instruction set. Table Instruction Set: MIPS MIPS MIPS Multiply Divide Instructions
OpCode JALR BLEZ BGTZ BLTZ BGEZ BLTZAL BGEZAL
Description Jump Jump Link Jump Register Jump Link Register Branch Equal Branch Equal Branch Less Than Equal Zero Branch Greater Than Zero Branch Less Than Zero Branch Greater Than Equal Zero Branch Less Than Zero Link Branch Greater Than Equal Zero Link
MIPS Level
Table Instruction Set: Jump Branch Instruction (Page
OpCode BEQL BNEL BLEZL BGTZL BLTZL BGEZL BLTZALL BGEZALL BCzTL BCzFL Description Branch Equal Likely Branch Equal Likely Branch Less Than Equal Zero Likely Branch Greater Than Zero Likely Branch Less Than Zero Likely Branch Greater Than Equal Zero Likely Branch Less Than Zero Link Likely
MIPS Level
Branch Greater Than Equal Zero Link Likely Branch Coprocessor True Likely Branch Coprocessor False Likely
Table Instruction Set: Jump Branch Instruction (Page
OpCode SLLV SRLV SRAV DSLL DSRL DSRA DSLLV DSRLV DSRAV DSLL32 DSRL32 DSRA32
Description Shift Left Logical Shift Right Logical Shift Right Arithmetic Shift Left Logical Variable Shift Right Logical Variable Shift Right Arithmetic Variable Doubleword Shift Left Logical Doubleword Shift Right Logical Doubleword Shift Right Arithmetic Doubleword Shift Left Logical Variable Doubleword Shift Right Logical Variable Doubleword Shift Right Arithmetic Variable Doubleword Shift Left Logical Doubleword Shift Right Logical Doubleword Shift Right Arithmetic
MIPS Level
Table Instruction Set: Shift Instructions
OpCode LWCz SWCz MTCz MFCz CTCz CFCz COPz BCzT BCzF DMFCz DMTCz LDCz SDCz
Description Load Word Coprocessor Store Word from Coprocessor Move Coprocessor Move From Coprocessor Move Control Coprocessor Move Control From Coprocessor Coprocessor Operation Branch Coprocessor True Branch Coprocessor False Doubleword Move From Coprocessor Doubleword Move Coprocessor Load Double Coprocessor Store Double Coprocessor
MIPS Level
Table Instruction Set: Coprocessor Instructions
OpCode SYSCALL BREAK
Description System Call Break
MIPS Level
Table Instruction Set: Special Instructions
OpCode TGEU TLTU TGEI TGEIU TLTI TLTIU TEQI TNEI
Description Trap Greater Than Equal Trap Greater Than Equal Unsigned Trap Less Than Trap Less Than Unsigned Trap Equal Trap Equal Trap Greater Than Equal Immediate Trap Greater Than Equal Immediate Unsigned Trap Less Than Immediate Trap Less Than Immediate Unsigned Trap Equal Immediate Trap Equal Immediate Table 2.10 MIPS 2/MIPS Exception Instructions
MIPS Level
OpCode DMFC0 DMTC0 MTC0 MFC0 TLBR TLBWI TLBWR TLBP CACHE ERET WAIT
Description Doubleword Move From Doubleword Move Move Move from Read Indexed Entry Write Indexed Entry Write Random Entry Probe Matching Entry Cache Operation Exception Return Enter Standby mode
MIPS Level
RISCore4000 RISCore32300 RISCore4000 RISCore32300 RISCore4000 RISCore32300
Table 2.11 RC64474/RC64475 Instructions
This chapter describes some basic operations RISCore4000 pipeline includes descriptions delay instructions interruptions pipeline flow caused interlocks exceptions, RC64474/RC64475 implementation uncached store buffer. floating point unit (FPU) pipeline described later chapter. RISCore4000 uses 5-stage pipeline, similar RISCore3000 RISCore32300 families. simplicity this pipeline allows device lower cost lower power than super-scalar super-pipelined processors, allowing large data dependent applications close processor's peak performance levels.
Once thepipeline been filled, five instructions executed simultaneously. Figure shows five stages instruction pipeline. Functional descriptions follow.
cycle
Figure: 1I-1R Instruction cache access 1I-2I 2A-2D 1D-2D Instruction virtual physical address translation Data cache access load align Data virtual physical address translation Register file read Bypass calculation
1A-2A
Instruction decode Integer add, logical, shift Data virtual address calculation Store align Branch decision Register file write
Figure RISCore4000 5-stage Instruction Pipeline
Delay instructions follow branch load instruction pipeline.
Each five pipeline stages phases, which illustrated described below: Instruction Fetch, Phase Instruction Fetch, Phase Register Fetch, Phase Register Fetch, Phase Execution, Phase Execution, Phase Data Fetch, Phase Data Fetch, Phase Write Back, Phase Write Back, Phase Instruction Fetch, Phase During phase instruction address translation begins ITLB.
Instruction Fetch, Phase During phase, instruction cache fetch begins instruction address translation ITLB continues. Register Fetch, Phase phase occurs follows: instruction cache fetch finishes. instruction cache checked against page frame number obtained from ITLB. Register Fetch, Phase phase occurs follows: instruction decoder decodes instruction. required operands fetched from register file. Make decision either issue slip (for interlock condition). branch, branch address calculated. Execution, Phase phase occurs follows: result from stages bypassed. arithmetic logic unit (ALU) starts integer arithmetic, logical shift operation. calculates data virtual address load store instructions. determines whether branch condition true. Execution, Phase During phase, following occurs: integer arithmetic, logical shift operation will complete. data cache access will start. Store data shifted specified byte position(s). data virtual-to-physical address translation DTLB will start. Data Fetch, Phase During phase, following occurs: data cache access will continue. data address translation DTLB completes. virtual-to-physical address translation JTLB will start.
Data Fetch, Phase During phase, following occurs: data cache access will finish data shifted down extended. virtual-to-physical address translation JTLB will finish. data cache checked against from DTLB JTLB data cache access.
Write Back, Phase This phase used internally processor resolve exceptions, preparation register file write. Write Back, Phase register-to-register load instructions, result written back register file during stage. Branch instructions perform operation during this stage. Figure shows activities occurring during each pipeline stage, load, store, branch instructions.
Clock
Stage
IFetch Decode
ITLBM
ITLBR
IDEC DCAD DCAA JTLB1 DTLBM DTLBR DCLA JTLB2
Load/Store
Branch
ITLBM IDEC DCAA JTLB1 DTLBM
Instruction cache address decode Instruction address translation match Instruction check Instruction decode Operation stage Data virtual address calculation Data cache array access Address translation JTLB stage Data address translation match Data check Data cache write
ITLBR DCAD DCLA JTLB2 DTLMR
Instruction cache array access Instrustion address translation read Register operand fetch Operation stage Write back register file Data cache address decode Data cache load align Address translation JTLB stage Data address translation read Store align Branch address calculation
Figure Pipeline Activities
pipeline branch delay cycle load delay cycle. one-cycle branch delay result branch decision logic operating during pipeline phase branch instruction. This allows branch target address calculated previous phase used instruction access following phase. pipeline will begin fetch branch path well fall-through path cycle following delay slot. After branch decision made, processor will continue with fetch either branch path (for taken branch) fallthrough path (for non-taken branch). Figure illustrates branch delay.
Cycle
Cycle
Cycle
Cycle
Cycle
Branch Delay
*Branch fall-through address calculated **Address selection made
Figure Pipeline Branch Delay
completion load pipeline phase produces operand that available pipeline phase instruction following load delay slot. Figure shows load delay pipeline cycle.
Cycle
Cycle
Cycle
Cycle
Cycle
Load Delay
Figure Pipeline Load Delay
Smooth pipeline flow interrupted when cache misses exceptions occur, when data dependencies detected. Interruptions handled using hardware, such cache misses, referred interlocks, while those that handled using software called exceptions. types interlocks are: stalls, which resolved halting pipeline slips, which require back pipeline advance while front pipeline held static
each cycle, exception interlock conditions checked active instructions. Because each exception interlock condition corresponds particular pipeline stage, condition traced back particular instruction exception/interlock stage, shown Figure 3.5. instance, Reserved Instruction (RI) exception raised execution stage.
Pipeline Stage State Stall Slip MDSt FCBsy Exceptions ITLB IPErr DTLB TLBMod Intr Figure Correspondence Pipeline Stage Interlock Condition Reset DPErr Trap
Table Table describe pipeline interlocks exceptions listed Figure 3.5.
Exception ITLB Intr IPErr ExTrap DTLB TLBMod DPErr Reset
Description Instruction Translation Address Exception External Interrupt Instruction Error Reserved Instruction Breakpoint System Call Coprocessor Unusable Instruction Parity Error Integer Overflow Interrupt Stage Traps Data Translation Address Exception Modified Data Error Data Parity Error Non-maskable Interrupt Soft Reset) Reset Table Pipeline Exceptions
Interlock IICM MDSt FCBsy Instruction Miss Instruction Cache Miss
Description
Coprocessor Possible Exception Data Cache Miss Load Interlock Multiply/Divide Start Coprocessor Busy Table Pipeline Interlocks
When exception condition occurs, relevant instruction those that follow pipeline cancelled. Accordingly, stall conditions later exception conditions that have referenced this instruction inhibited; there benefit servicing stalls cancelled instruction. When exceptional condition detected instruction, RC4000 will kill that instruction instructions that follow. When this instruction reaches stage, exception flag causes write various registers with exception state, change current appropriate exception vector address clear exception bits earlier pipeline stages.
This implementation allows preceding instructions complete execution prevents subsequent instructions from completing. Thus value sufficient restart execution. also ensures that exceptions taken order execution; instruction taking exception itself killed instruction further down pipeline that takes exception later cycle. Figure shows exception detection procedure (for example, reserved instruction exception).
Kill
Exception Vector
Exception Vector Address
Figure Exception Detection
Stalls used stop pipeline conditions detected after pipe-stage. When stall occurs, processor will resolve condition then pipeline will continue. Figure shows data cache miss stall.
Detect Cache Miss Start moving dirty cache line data write buffer first doubleword into cache restart pipeline Load remainder cache line into cache
Figure Data Cache Miss
data cache miss detected pipe stage. cache line replaced dirty data moved internal write buffer next cycle. first doubleword data returned cache pipeline will then restart. remainder cache line returned subsequent cycles. data written back will returned memory some time after entire cache line returned.
During pipe-stages, internal logic will determine whether possible start current instruction this cycle. source operands available (either from register file internal bypass logic) hardware resources necessary complete instruction will available necessary time(s), then instruction "issues"; otherwise, instruction will "slip". Slipped instructions retried subsequent cycles until they issue. backend pipeline (stages will advance normally during slips attempt resolve conflict. "NOPS" will inserted into bubble pipeline. Instructions killed branch likely instructions, ERET exceptions will cause slips. Figure shows instruction cache miss.
CYCLE Issue Issue Previous Instructions
Slip
Slip
Slip
Slip Issue Issue Issue
*NOP *NOP *NOP *NOP
Detect Cache Miss entire cache line into cache Continue pipeline *NOP Inserted instructions Figure Instruction cache miss
Instruction cache misses detected shown Figure pipeline slips stage. There never writeback required instruction cache miss since dirty data never exist cache. Writes allowed cache. Note that early restart employed instruction cache misses, requested cache line will loaded into cache entirety and, after that, pipeline will restart.
RISCore4000 contains write buffer improve performance writes external memory. Writes external memory, whether cache miss writebacks stores uncached writethrough addresses, this on-chip write buffer. write buffer holds four 64-bit address data pairs. cache miss write-back, entire buffer used write-back data allows processor proceed parallel with memory update. uncached write-through stores, write buffer uncouples from write memory allowing increased performance. write buffer full, additional stores will stall until there room them write buffer.
&'((
&'((
RISCore4000 provides full-featured memory management unit (MMU) that uses on-chip Translation Lookaside Buffer (TLB), translate virtual addresses into physical addresses. This chapter describes processor's virtual physical address spaces, virtual-to-physical address translation, operation making these translations, those System Control Coprocessor (CP0) registers that provide software interface TLB.
Mapped virtual addresses translated into physical addresses using on-chip TLB.1 fully associative memory organized pairs even/odd entries maps virtual pages their corresponding physical addresses. When address mapping indicated, each entry checked simultaneously match with virtual address that extended with ASID stored EntryHi register. address mapped page ranges size from 4Kbytes 16Mbytes, multiples 4-that 16K, 64K, 256K, 16M. there virtual address match TLB, physical page number extracted from concatenated with offset form physical address (see Figure 4.1). match occurs (TLB miss), exception taken software refills from page table resident memory. Software write over selected entry hardware mechanism write into random entry. Note: detection shutdown mechanism provided occurrence multiple matches TLB. There damage possible from this condition, result undefined. expected software allow multiple matches.
processor's virtual address space either 64-bits wide, depending implementation user, supervisor kernel mode operation setting corresponding extended address Status register (UX, KX). extended address addresses 32-bits wide. extended address addresses 64-bits wide. Both 32-bit 64-bit address wrap same way. example, 64-bit mode
0xffffffffffffffff will wrap 0x0000000000000000.
Note: RISCore4000 does slip shifts >32-bits other shift variables.
There virtual-to-physical address translations that occur outside TLB. example, addresses
kseg0 kseg1 spaces unmapped translations. these spaces, physical address 0x0000 0000 VA[28:0]
Figure shows translation virtual address into physical address.
Virtual address (VA) represented virtual page number (VPN) compared with TLB.
Virtual address
ASID
Offset
there match, page frame number (PFN) representing upper bits physical address (PA) output from TLB.
ASID
Entry
Offset, which does pass through TLB, then concatenated PFN.
Offset Physical address
Figure Overview Virtual-to-Physical Address Translation
shown Figure Figure 1.3, virtual address extended with 8-bit address space identifier (ASID), which reduces frequency flushing when switching contexts. This 8-bit ASID EntryHi register, described later this chapter. Global EntryLo0 EntryLo1 registers, described later this chapter.
Using 36-bit address, processor physical address space encompasses 64Gigabytes. section following describes translation virtual address physical address.
Converting virtual address physical address begins comparing virtual address from processor with virtual address TLB; there match when virtual page number (VPN) address same field entry, either: Global entry set, ASID field virtual address same ASID field entry. This match referred hit. there match, Miss exception taken processor software allowed refill from page table virtual/physical addresses memory. there virtual address match TLB, physical address output from concatenated with Offset, which represents address within page frame space. Offset does pass through TLB. Virtual-to-physical translation described greater detail throughout remainder this chapter; Figure page flow diagram process. following sections provide descriptions 32-bit 64-bit address translations.
Figure shows virtual-to-physical-address translation 32-bit virtual address. portion Figure shows virtual address with 12-bit, 4Kbyte, page size, labelled Offset. remaining bits address represent VPN, index 1Mentry page table. bottom portion Figure shows virtual address with 24-bit, 16Mbyte, page size, labelled Offset. remaining bits address represent VPN, index 256entry page table.
Virtual Address with (220) 4-Kbyte pages
bits
ASID
Offset
Bits virtual address select user, supervisor, kernel address spaces.
Offset passed Virtual-to-physical unchanged translation physical memory 36-bit Physical Address
Offset Offset passed unchanged physical memory
Virtual-to-physical translation
2928
ASID
bits pages
Offset
Virtual Address with (28)16-Mbyte pages
Figure 32-bit Virtual Address Translation
Figure page shows virtual-to-physical-address translation 64-bit virtual address. This figure illustrates extremes range possible page sizes: 4Kbyte page bits) 16Mbyte page bits). portion Figure shows virtual address with 12-bit, 4Kbyte, page size, labelled Offset. remaining bits address represent VPN, index 256Mentry page table. bottom portion Figure shows virtual address with 24-bit, 16Mbyte, page size, labelled Offset. remaining bits address represent VPN, index 64Kentry page table.
Virtual Address with 256M (228) 4-Kbyte pages
bits 256M
ASID
Offset
Virtual-to-physical translation Bits virtual address select user, supervisor, kernel address spaces.
36-bit Physical Address
Offset passed unchanged physical memory
Offset Offset passed unchanged physical memory
Virtual-to-physical translation
Virtual Address with (216 )16-Mbyte pages
ASID
Offset
bits pages
Figure 64-bit Virtual Address Translation
processor three operating modes that function both 64-bit operations: User mode Supervisor mode Kernel mode
User mode, single, uniform virtual address space-labelled User segment-is available; size Gbytes bytes) Status.UX (useg) Tbyte (240 bytes) Status.UX (xuseg)
Figure shows User mode virtual address space.
32-bit*
FFFF FFFF FFFF FFFF FFFF FFFF
64-bit
Address Error
8000 0000 0000 0100 0000
Address Error
Mapped
0000 0000
useg
0000 0000 0000 0000
Mapped
xuseg
Note: 32-bit virtual addresses, sign-extended through bits 63:32. Failure (for example, results Address Error exception.
Figure User Mode Virtual Address Space
User segment starts address current active user process resides either useg (32-bit virtual addressing) xuseg 64-bit virtual addressing). identically maps references useg/xuseg from modes, controls cache accessibility. processor operates User mode when Status register contains following bit-values: bits conjunction with these bits, Status register selects between 64-bit User virtual addressing follows: when 32-bit useg space selected when 64-bit xuseg space selected Table lists characteristics user mode segments, useg xuseg.
Address Values
Status Register Values
Segment Name
Address Range
Segment Size
32-bit A(31) 64-bit A(63:40)
useg xuseg
0x0000 0000 through 0x7FFF FFFF
Gbyte (231 bytes)
0x0000 0000 0000 0000 Tbyte (240 bytes) through 0x0000 00FF FFFF FFFF
Table 32-bit 64-bit User Mode Segments
User mode, when Status.UX User mode virtual addressing compatible with 32-bit addressing model shown Figure 4.4, 2-Gbyte user address space available, labelled useg.
valid User mode virtual addresses have their most-significant cleared attempt reference address with most-significant while User mode causes Address Error exception. 32-bit User mode virtual addressing, refill exception vector used misses. system maps references useg through TLB, settings within entry page determine cacheability reference.
User mode, when Status.UX User mode virtual addressing extended 64-bit model shown Figure 4.4, 1-Tbyte user address space available, labelled xuseg. valid User mode virtual addresses have bits 63:40 equal attempt reference address with bits 63:40 equal causes Address Error exception. extended addressing refill exception vector used misses.
Supervisor mode designed layered operating systems which true kernel runs RISCore4000's Kernel mode while rest operating system runs Supervisor mode. processor operates Supervisor mode when Status register contains following values: conjunction with these bits, Status register selects between 64-bit Supervisor mode virtual addressing: when 32-bit supervisor space virtual addressing selected when 64-bit supervisor space virtual addressing selected Figure shows Supervisor mode address mapping, Table 4.2, which follows figure, lists characteristics supervisor mode segments. Descriptions address spaces follow.
32-bit
FFFF 0000 0000 0000 0000
64-bit
FFFF FFFF FFFF FFFF FFFF FFFF 0000 sseg FFFF FFFF 0000 4000 0100 0000 0000
Address error apped Address error Address error
Address error Mapped Address error apped
csseg
xsseg
0000 0000 0000
apped
0000
suseg
0100 0000 0000
Address error apped
xsuseg
0000 0000 0000
Note: 32-bit virtual addressing, sign-extended through bits 63:32. Failure results Address Error exception.
Figure Supervisor Mode Virtual Address Space
Status Register Values Address Values 32-bit A(31) 32-bit A(31:29) 1102 64-bit A(63:62) 64-bit A(63:62) 64-bit A(63:62) Segment Name suseg Address Range 0x0000 0000 through 0x7FFF FFFF 0xC000 0000 through 0xDFFF FFFF 0x0000 0000 0000 0000 through 0x0000 00FF FFFF FFFF 0x4000 0000 0000 0000 through 0x4000 00FF FFFF FFFF 0xFFFF FFFF C000 0000 through 0xFFFF FFFF DFFF FFFF Segment Size Gbytes (231 bytes) Mbytes (229 bytes) Tbyte (240 bytes) Tbyte (240 bytes) Mbytes (229 bytes)
sseg
xsuseg
xsseg
csseg
Table 32-bit 64-bit Supervisor Mode Segments
Supervisor mode, when Status.SX most-significant 32-bit virtual address suseg virtual address space selected; covers full bytes (2Gbytes) current user address space. virtual address extended with contents 8-bit ASID field form unique virtual address. This mapped space starts virtual address 0x0000 0000 runs through 0x7FFF FFFF. When Status.SX three most-significant bits 32-bit virtual address 1102, sseg virtual address space selected; covers 229-bytes (512Mbytes) current supervisor address space. virtual address extended with contents 8-bit ASID field form unique virtual address. This mapped space begins virtual address 0xC000 0000 runs through 0xDFFF FFFF.
Supervisor mode, when Status.SX bits 63:62 virtual address 002, xsuseg virtual address space selected; covers full bytes (1Tbyte) current user address space. virtual address extended with contents 8-bit ASID field form unique virtual address. This mapped space starts virtual address 0x0000 0000 0000 0000 runs through 0x0000 00FF FFFF FFFF.
Supervisor mode, when Status.SX bits 63:62 virtual address 012, xsseg current supervisor virtual address space selected. virtual address extended with contents 8-bit ASID field form unique virtual address. This mapped space begins virtual address 0x4000 0000 0000 0000 runs through 0x4000 00FF FFFF FFFF.
Supervisor mode, when Status.SX bits 63:62 virtual address csseg separate supervisor virtual address space selected. Addressing csseg compatible with addressing sseg 32-bit mode. virtual address extended with contents 8-bit ASID field form unique virtual address. This mapped space begins virtual address 0xFFFF FFFF C000 0000 runs through 0xFFFF FFFF DFFF FFFF.
processor operates Kernel mode when Status register contains following values: conjunction with these bits, Status register selects between 64-bit Kernel mode addressing: when 32-bit kernel space virtual addressing selected when 64-bit kernel space virtual addressing selected processor enters Kernel mode whenever exception detected remains Kernel mode until Exception Return (ERET) instruction executed. ERET instruction restores processor mode existing prior exception. Kernel mode's virtual address space divided into regions differentiated high-order bits virtual address, shown Figure 4.6.
32-bit*
FFFF FFFF FFFF FFFF FFFF FFFF
E000 0000
apped apped
kseg3
FFFF FFFF E000 0000 FFFF FFFF C000 0000
64-bit Mapped apped
Unmapped Uncached Unmapped Cached
ckseg3 cksseg ckseg1 ckseg0
ksseg
FFFF FFFF A000 0000
C000 0000
A000 0000
apped Uncached Unmapped Cached
kseg1 FFFF FFFF 8000 0000
C000 00FF 8000 0000
Address error apped
xkseg xkphys
kseg0
C000 0000 0000 0000
8000 0000
apped
8000 0000 0000 0000 4000 0100 0000 0000
Address error apped
xksseg
kuseg
apped
4000 0000 0000 0000 0000 0100 0000 0000
Address error apped
xkuseg
0000 0000
0000 0000 0000 0000
Note: 32-bit virtual addressing, sign-extended through bits 63:32. Failure results Address Error exception. Figure Kernel Mode Address Space
Table lists characteristics 32-bit kernel mode segments, Table lists characteristics 64-bit kernel mode segments
Address Values
Status Register These Values
Segment Name
Address Range
Segment Size
A(31) A(31:29) 1002 A(31:29) 1012 A(31:29) A(31:29) 1112
kuseg kseg0 kseg1 ksseg kseg3
0x0000 0000 through 0x7FFF FFFF 0x8000 0000 through 0x9FFF FFFF 0xA000 0000 through 0xBFFF FFFF 0xC000 0000 through 0xDFFF FFFF 0xE000 0000 through 0xFFFF FFFF
Gbytes (231 bytes) Mbytes (229 bytes) Mbytes (229 bytes) Mbytes (229 bytes) Mbytes (229 bytes)
Table 32-bit Kernel Mode Segments
Kernel mode, when Status.KX most-significant virtual address, A31, cleared, 32-bit kuseg virtual address space selected; covers full bytes Gbytes) current user address space. virtual address extended with contents 8-bit ASID field form unique virtual address.
Kernel mode, when Status.KX most-significant three bits virtual address 1002, 32-bit kseg0 virtual address space selected; current 229-byte (512-Mbyte) kernel physical space. References kseg0 mapped through TLB; physical address selected defined subtracting 0x8000 0000 from virtual address (physical address 0x0000 0000 VA[28:0]). field Config register, described this chapter, controls cacheability coherency.
Kernel mode, when Status.KX most-significant three bits 32-bit virtual address 1012, 32-bit kseg1 virtual address space selected; current 229-byte (512Mbyte) kernel physical space. References kseg1 mapped through TLB; physical address selected defined subtracting 0xA000 0000 from virtual address (physical address 0x0000 0000 VA[28:0]). Caches disabled accesses these addresses, physical memory memory-mapped device registers) accessed directly.
Kernel mode, when Status.KX most-significant three bits 32-bit virtual address 1102, ksseg virtual address space selected; current 229-byte (512Mbyte) supervisor virtual space. virtual address extended with contents 8-bit ASID field form unique virtual address.
Kernel mode, when Status.KX most-significant three bits 32-bit virtual address 1112, kseg3 virtual address space selected; current 229-byte (512Mbyte) kernel virtual space. virtual address extended with contents 8-bit ASID field form unique virtual address.
Address Values
Status Register These Values
Segment Name
Address Range
Segment Size
A(63:62)
xkuseg
0x0000 0000 0000 0000 through 0x0000 00FF FFFF FFFF 0x4000 0000 0000 0000 through 0x4000 00FF FFFF FFFF
Tbyte (240 bytes) Tbyte (240 bytes)
A(63:62)
xksseg
A(63:62)
xkphys
236-byte 0x8000 0000 0000 0000 through spaces 0xBFFF FFFF FFFF FFFF 0xC000 0000 0000 0000 through 0xC000 00FF 7FFF FFFF 0xFFFF FFFF 8000 0000 through 0xFFFF FFFF 9FFF FFFF bytes
A(63:62)
xkseg
A(63:62) A(61:31) A(63:62) A(61:31) A(63:62) A(61:31) A(63:62) A(61:31)
ckseg0
Mbytes (229 bytes)
ckseg1
0xFFFF FFFF A000 0000 Mbytes through (229 bytes) 0xFFFF FFFF BFFF FFFF 0xFFFF FFFF C000 0000 Mbytes through (229 bytes) 0xFFFF FFFF DFFF FFFF 0xFFFF FFFF E000 0000 through 0xFFFF FFFF FFFF FFFF Mbytes (229 bytes)
cksseg
ckseg3
Table 64-bit Kernel Mode Segments
Kernel mode, when Status.KX bits 63:62 64-bit virtual address 002, xkuseg virtual address space selected; covers current user address space. virtual address extended with contents 8-bit ASID field form unique virtual address. special feature handler, Status register set, user address region becomes 31-byte unmapped, uncached space. This allows exception code operate uncached using base register.
Kernel mode, when Status.KX bits 63:62 64-bit virtual address 012, xksseg virtual address space selected; current supervisor virtual space virtual address extended with contents 8-bit ASID field form unique virtual address.
Kernel mode, when Status.KX bits 63:62 64-bit virtual address 102, xkphys virtual address space selected; eight 236-byte kernel physical spaces. Accesses with address bits 58:36 equal cause address error. References this space mapped; physical address selected taken from bits 35:0 virtual address. Bits 61:59 virtual address specify cacheability coherency attributes, shown Table 4.5.
Value (61:59)
Cacheability Coherency Attributes Cacheable, noncoherent, write-through, write allocate Cacheable, noncoherent, write-through, write allocate Uncached Cacheable, noncoherent Reserved
Starting Address 0x8000 0000 0000 0000 0x8800 0000 0000 0000 0x9000 0000 0000 0000 0x9800 0000 0000 0000 0xA000 0000 0000 0000
Table Cacheability Coherency Attributes
Kernel mode, when Status.KX bits 63:62 64-bit virtual address 112, address space selected following: kernel virtual space, xkseg, current supervisor virtual space; virtual address extended with contents 8-bit ASID field form unique virtual address four 32-bit kernel compatibility spaces, described next section.
Kernel mode, when Status.KX bits 63:62 64-bit virtual address 112, bits 61:31 virtual address equal "-1", lower bytes address, shown Figure 4.6, select following 512-Mbyte compatibility spaces. ckseg0. This 64-bit virtual address space unmapped region, compatible with 32-bit address model kseg0. field Config register, described this chapter, controls cacheability coherency. ckseg1. This 64-bit virtual address space unmapped uncached region, compatible with 32-bit address model kseg1. cksseg. This 64-bit virtual address space current supervisor virtual space, compatible with 32-bit address model ksseg. ckseg3. This 64-bit virtual address space kernel virtual space, compatible with 32-bit address model kseg3.
System Control Coprocessor (CP0) implemented integral part CPU, supports memory management, address translation, exception handling, other privileged operations. contains registers shown Figure plus 48-entry TLB. sections that follow describe processor uses each memory management-related registers. Each register unique identification number. This unique number referred register number. instance, Page Mask register register number
EntryHi EntryHi
EntryLo0 EntryLo0 EntryLo1
Index
Context
Index
Random Random Page Mask Page Mask
Count
BadVAddr
Compare
Status
Cause
XContext
Wired Wired
CacheErr
PRId
("Safe" entries) (See Random Register, contents Wired)
ErrorEPC
Config
TagHi
LLAddr
TagLo
Used with memory management system.
Used with exception processing. Chapter details.
Note: *Register number
Figure Registers
Figure shows entry formats both 64-bit virtual addressing. Each field entry corresponding field EntryHi, EntryLo0, EntryLo1, PageMask registers, shown Figure Figure 5.4; example Mask field entry also held PageMask register.
64-bit Virtual Addressing
256-bit entry 64-bit virtual addressing
MASK
VPN2
ASID
Figure Format Entry
format EntryHi, EntryLo0, EntryLo1, PageMask registers nearly same entry. exception Global field bit), which used reserved EntryHi register. Figure describes entry fields that shown Figure 5.2.
PageMask Register
Mask
Mask Page comparison mask. Reserved. Must written zeroes, returns zeroes when read.
EntryHi Register
64-bit FILL VPN2 ASID
VPN2.Virtual page number divided (maps pages). ASID.Address space field. 8-bit field that lets multiple processes share TLB; each process distinct mapping otherwise identical virtual page numbers. .Region. user, supervisor, kernel) used match vAddr63.62 Fill .Reserved. Returns zero when read, ignored writes. .Reserved. Must written zeroes, returns zeroes when read. Figure Fields PageMask EntryHi Registers
EntryLo0 EntryLo1 Registers
64-bit 64-bit
.Page frame number; upper bits physical address. C.Specifies page coherency attribute; Table 5.1. D.Dirty. this set, page marked dirty and, therefore, writable. This actually write-protect that software prevent alteration data. .Valid. this set, indicates that entry valid; otherwise, TLBL TLBS miss occurs. .Global. this both Lo1, then processor ignores ASID during lookup. .Reserved. Must written zeroes, returns zeroes when read.
Figure Fields EntryLo0 EntryLo1 Registers
page coherency attribute bits specify whether references page should cached; cached, algorithm selects between several coherency attributes. Table shows coherency attributes selected bits.
C(5:3) Value
Page Coherency Attribute Cacheable, noncoherent, write-through, write allocate Cacheable, noncoherent, write-through, write allocate Uncached Cacheable, noncoherent, write-back Reserved Table Page Coherency Values
following sections describe registers (shown Figure page 5.1) that assigned specifically software interface with memory management (each register followed register number parentheses). Index register (CP0 register number Random register EntryLo0 EntryLo1 registers PageMask register Wired register EntryHi register (10) PRId register (15) Config register (16) LLAddr register (17) TagLo (28) TagHi (29) registers
Index register 32-bit, read/write register containing bits index entry TLB. high-order register shows success failure Probe (TLBP) instruction. Index register also specifies entry affected Read (TLBR) Write Index (TLBWI) instructions. Figure shows format Index register. Table 5.2, which follows figure, describes Index register fields. Index Register
Figure Index Register
Index
Field Index
Description Probe failure. when previous TLBProbe (TLBP) instruction unsuccessful. Index entry affected TLBRead TLBWrite instructions Reserved. Must written zeroes, returns zeroes when read.
Table Index Register Field Descriptions
Random Register Random register read-only register which bits index entry TLB. This register decrements each instruction executes, values range between upper lower bound, follows: lower bound number entries reserved exclusive operating system (the contents Wired register). upper bound total number entries. Thus upper bound (The entries number from 47). RISCore4000 counts only valid instructions. Random register specifies entry that affected Write Random instruction. register does need read this purpose; however, register readable verify proper operation processor. simplify testing, Random register value upper bound upon system reset. This register also upper bound when Wired register written. Figure shows format Random register; Table page describes Random register fields. Random Register
Figure Random Register
Random
Field Random Description random index
Reserved. Must written zeroes, returns zeroes when read.
Table Random Register Field Descriptions
EntryLo register consists registers that have identical formats: EntryLo0 used even virtual pages. EntryLo1 used virtual pages. EntryLo0 EntryLo1 registers read/write registers. They hold physical page frame number (PFN) entry even pages, respectively, when performing read write operations. Figure page shows format these registers.
PageMask register read/write register used reading from writing TLB. This register holds comparison mask that sets variable page size each entry, shown Table 5.4. read write operations this register either source destination; when virtual addresses presented translation into physical address, corresponding bits identify which virtual address bits among bits 24:13 used comparison. When Mask field values shown operation undefined. Page Size Kbytes Kbytes Kbytes Kbytes Mbyte Mbytes Mbytes
Table Mask Field Values Page Sizes
Wired register read/write register that specifies boundary between wired random entries TLB, shown Figure 5.7. Wired entries nonreplaceable entries, which cannot overwritten write random operation. Random entries overwritten.
Range Random entries Wired Register Range Wired entries
Figure Wired Register Boundary
Wired register upon system reset. Writing this register also sets Random register value upper bound (see Random register, above). Figure shows format Wired register; Table 5.5, which follows figure, describes register fields. Wired Register
Figure Wired Register
Wired
Field Wired
Description Wired boundary (the number wired entries) Reserved. Must written zeroes, returns zeroes when read.
Table Wired Register Field Descriptions
EntryHi register holds high-order bits entry read write operations accessed Probe, Write Random, Write Indexed, Read Indexed instructions. Figure shows format this register. When either refill, invalid, modified exception occurs, EntryHi register loaded with virtual page number (VPN2) ASID virtual address that have matching entry. (See Chapter more information about these exceptions.)
32-bit, read-only Processor Revision Identifier (PRId) register contains information identifying implementation revision level CP0. Figure shows format PRId register; Table describes PRId register fields.
PRId Register
Figure Processor Revision Identifier Register Format
Field
Description Implementation number Revision number RC64474/RC64475 0x30 0X00
Reserved. Must written zeroes, returns zeroes when read.
Table PRId Register Fields
low-order byte (bits 7:0) PRId register interpreted revision number, highorder byte (bits 15:8) interpreted implementation number. implementation number Rc64474/RC64475 processors 0x30. content high-order halfword (bits 31:16) register reserved. revision number stored value form y.x, where major revision number bits minor revision number bits 3:0. revision number distinguish some chip revisions, however there guarantee that changes chip will necessarily reflected PRId register, that changes revision number necessarily reflect real chip changes. this reason, these values listed software should rely revision number PRId register characterize chip. Certain attributes, such cache size, independent implementation number.
Config register specifies various configuration options selected RISCore4000 processors; Table lists these options. Some configuration options, defined Config bits 31:3, hardware during reset included Config register read-only status bits software access. field only read/write field indicated Config register bits 2:0) controlled software; reset these fields undefined. Figure 5.10 shows format Config register; Table 5.7, which follows figure, describes Config register fields.
Figure 5.10 Config Register Format
Field Description
System clock ratio: processor clock frequency divided processor clock frequency divided processor clock frequency divided processor clock frequency divided processor clock frequency divided processor clock frequency divided processor clock frequency divided Reserved Writeback data rate: DDDD DDxDDx DDxxDDxx DxDxDxDx DDxxxDDxxx DDxxxxDDxxxx DxxDxxDxxDxx DDxxxxxDDxxxxx DxxxDxxxDxxxDxxx System size selection SysAd bits SysAD bits BigEndianMem Little endian endian Primary I-cache Size (I-cache size 212+IC bytes). RC64474/475 processor, this Kbytes 010) Primary D-cache Size (D-cache size 212+DC bytes). RC64474/475 processor, this Kbytes 010) Primary I-cache line size bytes Words) Primary D-cache line size bytes Words) kseg0 coherency algorithm (see EntryLo0 EntryLo1 registers) Reserved. Returns indicated values when read.
Table Config Register Fields
Doubleword every cycle Doublewords every cycles Doublewords every cycles Doublewords every cycles Doublewords every cycles Doublewords every cycles Doublewords every cycles Doublewords every cycles Doublewords every cycles Reserved
Others
read/write Load Linked Address (LLAddr) register contains physical address read most recent Load Linked instruction. This register diagnostic purposes only, serves function during normal operation.
Figure 5.11 shows format LLAddr register; PAddr represents bits physical address, PA(35:4) LLAddr Register
PAddr(35:4)
Figure 5.11 LLAddr Register Format
Cache Registers [TagLo (28) TagHi (29)] TagLo TagHi registers 32-bit read/write registers that hold primary cache parity during cache initialization, cache diagnostics, cache error processing. registers written CACHE MTC0 instructions. field these registers ignored Index Store operations. Parity computed store operation. Figure 5.12 shows format these registers primary cache operations. Table lists field definitions TagLo TagHi registers.
TagLo
PTagLo
PState
TagHi
Figure 5.1
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