Version December 1997 2975 Stender Way, Santa Clara, California 9

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IDT79RV4700RISC Processor Hardware User's Manual
Version December 1997
2975 Stender Way, Santa Clara, California 95054 Telephone: (800) 345-7015 TWX: 910-338-2070 FAX: (408) 492-8674 Printed U.S.A. ©1996
Integrated Device Technology, Inc. reserves right make changes products specifications time, without notice, order improve design performance supply best possible product. does assume responsibility circuitry described other than circuitry embodied product. Company makes representations that circuitry described herein free from patent infringement other rights third parties which result from use. license granted implication otherwise under patent, patent rights other rights,
LIFE SUPPORT POLICY Integrated Device Technology's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between manufacturer officer IDT. Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component components life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
logo registered trademark, BiCameral, BurstRAM, BUSMUX, CacheRAM, DECnet, Double-Density, FASTX, Four-Port, FLEXI-CACHE, Flexi-PAK, Flow-thruEDC, IDT/c, IDTenvY, IDT/sae, IDT/sim, IDT/ux, MacStation, MICROSLICE, PalatteDAC, REAL8, R3041, R3051, R3052, R3071, R3081, R36100, R3721, R4650, RV4700, R5000, RISController, RISCore, RISC Subsystem, RISC Windows, SARAM, SmartLogic, SyncFIFO, SyncBiFIFO, SPC, TargetSystem WideBus trademarks Integrated Device Technology, Inc. MIPS registered trademark, RISCompiler, RISComponent, RISComputer, RISCware, RISC/os, R3000, R3010 trademarks MIPS Computer Systems, Inc. Postscript registered trademark Adobe Systems, Inc. AppleTalk, LocalTalk, Macintosh registered trademarks Apple Computer, Inc. Centronics registered trademark Genicom, Inc. Ethernet registered trademark Digital Equipment Corp. registered trademark Corp.
Table Contents Table Contents
Overview Chapter Introduction Features. Device Overview. Pipeline Overview. Register Overview Instruction Overview Data Formats Addressing 1-11 Coprocessors (CP0-CP2) 1-13 System Control Coprocessor, 1-13 Floating-Point Co-Processor, CP1. 1-16 Floating-Point Units 1-16 Virtual-to-Physical Address Mapping 1-17 Joint 1-17 Instruction 1-18 Data 1-18 Cache Memory 1-18 Instruction Cache 1-18 Data Cache. 1-18 Write buffer 1-19 RV4700 Clocks. 1-19 System Interface. 1-20 Instruction Summary Chapter Introduction Instruction Formats. Load Store Instructions. Scheduling Load Delay Slot. Defining Access Types. Computational Instructions 64-bit Virtual Address Operations with 32-bit operands. Cycle Timing Multiply Divide Instructions Jump Branch Instructions. Overview Jump Instructions Overview Branch Instructions Special Instructions. Exception Instructions Coprocessor Instructions Pipeline Chapter Introduction Pipeline Operation Pipeline Stages Instruction Fetch, Phase Instruction Fetch, Phase Register Fetch, Phase one. Register Fetch, Phase two. Execution, Phase Execution, Phase Data Fetch, Phase Data Fetch, Phase Write Back, Phase
Table Contents
Table Contents
Write Back, Phase Branch Delay. Load Delay Interlock Exception Handling. Exception Conditions. Stall Conditions Slip Conditions RV4700 Write Buffer Memory Management Chapter Translation Lookaside Buffer (TLB) Hits Misses Multiple Matches Address Spaces Virtual Address Space Physical Address Space Virtual-to-Physical Address Translation. 32-bit Virtual Address Translation 64-bit Virtual Address Translation Operating Modes User Mode Operations 32-bit User Mode (useg) 64-bit User Mode (xuseg) Supervisor Mode Operations 32-bit Supervisor Mode, User Space (suseg) 32-bit Supervisor Mode, Supervisor Space (sseg). 64-bit Supervisor Mode, User Space (xsuseg) 64-bit Supervisor Mode, Current Supervisor Space (xsseg) 64-bit Supervisor Mode, Separate Supervisor Space (csseg). Kernel Mode Operations 32-bit Kernel Mode, User Space (kuseg) 4-10 32-bit Kernel Mode, Kernel Space (kseg0). 4-10 32-bit Kernel Mode, Kernel Space (kseg1). 4-10 32-bit Kernel Mode, Supervisor Space (ksseg) 4-10 32-bit Kernel Mode, Kernel Space (kseg3). 4-11 64-bit Kernel Mode, User Space (xkuseg). 4-11 64-bit Kernel Mode, Current Supervisor Space (xksseg). 4-11 64-bit Kernel Mode, Physical Spaces (xkphys) 4-12 64-bit Kernel Mode, Kernel Space (xkseg) 4-12 64-bit Kernel Mode, Compatibility Spaces (ckseg1:0, cksseg, ckseg3). 4-12 System Control Coprocessor 4-12 Format Entry 4-13 Registers 4-15 Index Register 4-16 Random Register 4-16 EntryLo0 (2), EntryLo1 Registers. 4-17 PageMask Register 4-17 Wired Register 4-18 EntryHi Register (CP0 Register 4-18 Processor Revision Identifier (PRId) Register (15) 4-19 Config Register (16). 4-19 Load Linked Address (LLAddr) Register (17) 4-20 Cache Registers [TagLo (28) TagHi (29)] 4-21 Virtual-to-Physical Address Translation Process 4-22 Misses 4-23 Instructions. 4-23
Table Contents
Table Contents
Exception Processing Chapter Exception Processing Works Exception Processing Registers Context Register Virtual Address Register (BadVAddr) Count Register (9). Compare Register (11). Status Register (12) Status Register Format Status Register Modes Access States Status Register Reset Cause Register (13) Exception Program Counter (EPC) Register (14) XContext Register (20) Error Checking Correcting (ECC) Register (26) Cache Error (CacheErr) Register (27) 5-10 Error Exception Program Counter (Error EPC) Register (30) 5-11 Processor Exceptions. 5-11 Exception Types 5-11 Reset Exception Process 5-12 Cache Error Exception Process 5-12 Soft Reset Exception Process 5-12 General Exception Process. 5-13 Exception Vector Locations 5-13 Priority Exceptions. 5-14 Reset Exception 5-14 Cause 5-14 Processing 5-14 Servicing 5-15 Soft Reset Exception. 5-15 Cause 5-15 Processing 5-15 Servicing 5-15 Nonmaskable Interrupt (NMI) Exception 5-15 Cause 5-15 Processing 5-15 Servicing 5-16 Address Error Exception. 5-16 Cause 5-16 Processing 5-16 Servicing 5-16 Exceptions 5-17 Refill Exception 5-17 Cause 5-17 Processing 5-17 Servicing. 5-17 Invalid Exception 5-18 Cause 5-18 Processing 5-18 Servicing 5-18 Modified Exception 5-18 Cause 5-18 Processing 5-18 Servicing 5-19 Cache Error Exception 5-19 Cause 5-19 Processing 5-19
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Table Contents
Servicing 5-19 Error Exception 5-19 Cause 5-19 Processing 5-19 Servicing 5-20 Integer Overflow Exception 5-20 Cause 5-20 Processing 5-20 Servicing 5-20 Trap Exception 5-20 Cause 5-20 Processing 5-20 Servicing 5-21 System Call Exception 5-21 Cause 5-21 Processing 5-21 Servicing 5-21 Breakpoint Exception 5-21 Cause 5-21 Processing 5-21 Servicing 5-21 Reserved Instruction Exception 5-22 Cause 5-22 Processing 5-22 Servicing 5-22 Coprocessor Unusable Exception. 5-22 Cause 5-22 Processing 5-22 Servicing 5-23 Floating-Point Exception 5-23 Cause 5-23 Processing 5-23 Servicing 5-23 Interrupt Exception 5-23 Cause 5-23 Processing 5-23 Servicing 5-24 Exception Handling Servicing Flowcharts 5-24 Floating-Point Unit Chapter Overview RV4700 Floating-Point Coprocessor Features Programming Model Floating-Point General Registers (FGRs) Floating-Point Registers. Floating-Point Control Registers Implementation Revision Register, (FCR0). Control/Status Register (FCR31) Accessing Control/Status Register IEEE Standard Control/Status Register Control/Status Register Condition Control/Status Register Cause, Flag, Enable Fields Cause Bits Enable Bits. Flag Bits
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Table Contents
Control/Status Register Rounding Mode Control Bits Floating-Point Formats Binary Fixed-Point Format Floating-Point Instruction Overview 6-10 Floating-Point Load, Store, Move Instructions 6-11 Transfers Between Memory. 6-11 Transfers Between 6-11 Load Delay Hardware Interlocks. 6-12 Data Alignment 6-12 Endianness 6-12 Floating-Point Conversion Instructions 6-12 Floating-Point Computational Instructions 6-12 Branch Condition Instructions 6-12 Floating-Point Compare Operations 6-12 Instruction Pipeline Overview 6-13 Instruction Execution 6-13 Instruction Execution Cycle Time 6-14 Instruction Scheduling Constraints 6-14 Multiplier Constraints 6-15 Adder Constraints 6-15 Resource Scheduling Rules 6-15 Floating-Point Exceptions. Chapter Exception Types Exception Trap Processing. Flags Exceptions Inexact Exception Invalid Operation Exception (V). Division-by-Zero Exception Overflow Exception Underflow Exception Unimplemented Instruction Exception (E). Saving Restoring State. Trap Handlers IEEE Standard Exceptions Processor Signal Descriptions Chapter Introduction System Interface Signals Clock/Control Interface Signals. Interrupt Interface Signals. JTAG Interface Signals Initialization Interface Signals Initialization Interface Chapter Introduction Functional Overview Reset Initialization Signal Descriptions Power-on Reset Cold Reset Warm Reset Initialization Sequence Boot-Mode Settings Clock Interface Chapter Introduction 10-1
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Table Contents
Signal Terminology 10-1 Basic System Clocks 10-1 MasterClock 10-1 MasterOut 10-2 SyncIn/SyncOut 10-2 PClock. 10-2 SClock 10-2 TClock. 10-2 RClock 10-2 System Timing Parameters 10-3 Alignment SClock 10-3 Alignment MasterClock 10-3 Phase-Locked Loop (PLL) 10-3 Components Operation 10-4 Passive Components 10-4 Connecting Clocks Phase-Locked System. 10-5 Connecting Clocks System without Phase Locking 10-6 Connecting Gate-Array Device 10-6 Connecting CMOS Logic System 10-8 Cache Organization, Operation Coherency Chapter Introduction 11-1 Memory Organization 11-1 Overview Cache Operations 11-2 RV4700 Cache Description 11-2 Cache Line Size 11-2 Cache Organization Accessibility. 11-2 Organization Primary Instruction Cache (I-Cache). 11-3 Organization Primary Data Cache (D-Cache) 11-3 Accessing Primary Caches 11-5 Cache States 11-5 Primary Cache States 11-6 Cache Line Ownership. 11-6 Cache Write Policy. 11-6 Cache State Transition Diagrams 11-7 Cache Coherency Overview. 11-7 Cache Coherency Attributes 11-7 Uncached 11-8 Noncoherent 11-8 Cache Operation Modes 11-8 RV4700 Processor Synchronization Support 11-8 Test-and-Set 11-8 Counter 11-9 Load Linked (LL) Store Conditional (SC) 11-10 Examples Using 11-11 System Interface Chapter Introduction 12-1 Terminology 12-1 System Interface Description 12-1 Interface Buses. 12-2 Address Data Cycles 12-2 Issue Cycles 12-3 Handshake Signals 12-4 System Interface Protocols. 12-4 Master Slave States 12-5 Moving from Master Slave State 12-5
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External Arbitration. 12-5 Uncompelled Change Slave State 12-5 Processor External Requests. 12-6 Rules Processor Requests 12-6 Processor Requests 12-7 Processor Read Request 12-8 Processor Write Request 12-8 External Requests 12-9 External Read Request 12-10 External Write Request 12-10 Read Response 12-10 Handling Requests 12-11 Load Miss 12-11 No-Secondary-Cache Mode Load Miss. 12-12 Store Miss 12-12 No-Secondary-Cache Mode Store Miss 12-12 Store Hit. 12-13 No-Secondary-Cache Mode Store 12-13 Uncached Loads Stores 12-13 CACHE Operations 12-13 Load Linked/Store Conditional Operation 12-14 Processor External Request Protocols 12-14 Processor Request Protocols 12-14 Processor Read Request Protocol Steps. 12-15 External Instruction Read Response Time. 12-16 Instruction Read Latency Steps System Clock. 12-17 Example Instruction Block Read With Zero Wait-State 12-17 External Data Read Response Time 12-17 Data Read Latency Steps System Clock 12-18 Example Data Single Read With Zero Wait-State 12-18 External Cycles Read Latency 12-18 Processor Write Request Protocol. 12-19 Processor Request Flow Control 12-22 External Request Protocols 12-23 External Arbitration Protocol 12-24 External Read Request Protocol 12-24 External Null Request Protocol 12-25 External Write Request Protocol. 12-26 Read Response Protocol. 12-27 Data Rate Control. 12-29 Read Data Pattern 12-29 Write Data Transfer Patterns 12-30 Independent Transmissions SysAD 12-31 System Interface Endianness 12-31 System Interface Cycle Time 12-31 Release Latency. 12-32 System Interface Commands Data Identifiers. 12-32 Command Data Identifier Syntax 12-32 System Interface Command Syntax. 12-33 Read Requests 12-33 Write Requests 12-34 Null Requests 12-36 System Interface Data Identifier Syntax 12-36 Noncoherent Data. 12-36 Data Identifier Definitions 12-37 System Interface Addresses 12-38 Addressing Conventions 12-38
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Subblock Ordering 12-38 Example Sequential Ordering. 12-39 Example Subblock Ordering. 12-39 Processor Internal Address 12-42 RV4700 Processor Interrupts Chapter Introduction 13-1 Hardware Interrupts. 13-1 Nonmaskable Interrupt (NMI) 13-1 Asserting Interrupts 13-1 RV4700 Error Checking Chapter Introduction 14-1 Error Checking Processor 14-1 Types Error Checking 14-1 Parity Error Detection. 14-1 Error Checking Operation. 14-2 System Interface. 14-2 System Interface Command 14-2 Summary Error Checking Operations 14-3 Instruction Details Appendix Introduction Instruction Classes. Instruction Formats Instruction Notation Conventions Load Store Instructions Jump Branch Instructions. Coprocessor Instructions. System Control Coprocessor (CP0) Instructions Instruction Opcode Encoding A-151 Instruction Details Appendix Introduction Instruction Formats .B-1 Floating-Point Loads, Stores, Moves. Floating-Point Operations. Instruction Notation Conventions Instruction Notation Examples Load Store Instructions .B-5 Computational Instructions. Instruction Opcode Encoding. B-45 Cache Operations Timing. Appendix Introduction Caveats About Cache Operations. Cache Operations Tables Details Fill_I Equation Standby Mode Operation. Appendix Entering Standby Mode Coprocessor Hazards. Appendix
viii
List Tables
Table Table Table Table Table Table Table Table Table Table
Table Title
Page
Table 1.10 Table 1.11 Table 1.12 Table 1.13 Table 1.14 Table 1.15 Table 1.16 Table 1.17 Table 1.18 Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1.19 4.10 4.11 4.12
Instruction Set: Load Store Instructions Instruction Set: Arithmetic Instructions (ALU Immediate). Instruction Set: Arithmetic (3-Operand, R-Type). Instruction Set: Multiply Divide Instructions Instruction Set: Jump Branch Instruction. Instruction Set: Shift Instructions Instruction Set: Coprocessor Instructions Instruction Set: Special Instructions MIPS 2/MIPS Additional: Load Store Instructions. MIPS 2/MIPS Additional: Arithmetic Instructions (ALU Immediate). MIPS 2/MIPS Additional: Multiply Divide Instructions MIPS 2/MIPS Additional: Branch Instructions. MIPS 2/MIPS Additional: Arithmetic Instructions (3-operand, R-type) MIPS 2/MIPS Additional: Shift Instructions. MIPS 2/MIPS Additional: Exception Instructions. 1-10 MIPS 2/MIPS Additional: Coprocessor Instructions 1-10 Instructions. 1-10 System Control Coprocessor (CP0) Register Definitions. 1-15 RV4700 Floating-Point Latency Cycles 1-16 Byte Access within Doubleword. Multiply/Divide Instruction Cycle Timing. Pipeline Exceptions. Pipeline Interlocks 32-bit 64-bit User Mode Segments 32-bit 64-bit Supervisor Mode Segments 32-bit Kernel Mode Segments 4-10 64-bit Kernel Mode Segments 4-11 Cacheability Coherency Attributes 4-12 Page Coherency Values 4-15 Index Register Field Descriptions 4-16 Random Register Field Descriptions 4-17 Mask Field Values Page Sizes 4-17 Wired Register Field Descriptions. 4-18 PRId Register Fields 4-19 Config Register Fields 4-20
List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 4.13 4.14 5.10 5.11 5.12
List Tables Cache Register Fields 4-21 Instructions. 4-23 Exception Processing Registers Context Register Fields Status Register Fields Cause Register Fields. Cause Register ExcCode Field XContext Register Fields Register Fields CacheErr Register Fields. 5-10 Exception Vector Base Addresses 5-13 Exception Vector Offsets 5-13 Exception Priority Order 5-14 List Exception Flowcharts 5-24 Floating-Point Control Register Assignments. FCR0 Fields Control/Status Register Fields. Rounding Mode Decoding. Equations Calculating Values Single Double-Precision Floating-Point Format Floating-Point Format Parameter Values Minimum Maximum Floating-Point Values. Binary Fixed-Point Format Fields. Instruction Summary: Load, Move Store Instructions 6-10 Instruction Summary: Conversion Instructions. 6-10 Instruction Summary: Computational Instructions 6-11 Instruction Summary: Compare Branch Instructions 6-11 Mnemonics Definitions Compare Instruction Conditions 6-13 Floating-Point Operation Latencies 6-14 Default Exception Actions Exception-Causing Conditions. System Interface Signals. Clock/Control Interface Signals Interrupt Interface Signals JTAG Interface Signals Initialization Interface Signals. RV4700 Processor Signal Summary RV4700 Processor Signal Summary Boot-Mode Settings. Cache States 11-6 Coherency Attributes Processor Behavior 11-8 Load Miss Primary Cache. 12-11 Store Miss Primary Cache 12-12 System Interface Requests 12-14 Transmit Data Rates Patterns 12-30 Release Latency External Requests 12-32 Encoding SysCmd(7:5) System Interface Commands. 12-33 Encoding SysCmd(4:3) Read Requests 12-34 Encoding SysCmd(2:0) Block Read Request 12-34
Table 6.10 Table 6.11 Table 6.12 Table 6.13 Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 6.14 11.1 11.2 12.1 12.2 12.3 12.4 12.5 12.6
Table 12.7 Table 12.8
List Tables Table 12.9 Table 12.10 Table 12.11 Table 12.12 Table 12.13 Table 12.14 Table 12.15 Table 12.16 Table 12.17 Table 12.18 Table 12.19 Table 14.1 Table 14.2 Table Table Table Table Table Table Table Table Table Table Table Table
List Tables Doubleword, Word, Partial-word Read Request Data Size Encoding SysCmd(2:0) 12-34 Write Request Encoding SysCmd(4:3). 12-35 Block Write Request Encoding SysCmd(2:0) 12-35 Doubleword, Word, Partial-word Write Request Data Size Encoding SysCmd(2:0) 12-35 External Null Request Encoding SysCmd(4:3) 12-36 Processor Data Identifier Encoding SysCmd(7:3) 12-37 External Data Identifier Encoding SysCmd(7:3) 12-38 Sequence Doublewords Transferred Using Subblock Ordering: Address 12-40 Sequence Doublewords Transferred Using Subblock Ordering: Address 12-40 Sequence Doublewords Transferred Using Subblock Ordering: Address 012. 12-40 Partial Word Transfer Byte Lane Usage 12-41 Error Checking Correcting Summary Internal Transactions 14-3 Error Checking Correcting Summary External Transactions 14-3 Instruction Operation Notations Load Store Common Functions Access Type Specifications Loads/Stores Instruction Encoding A-152 Valid Instruction Formats. Logical Negation Predicates Condition True/False Load Store Common Functions Format Field Decoding. Floating-Point Instructions Operations Primary Data Cache Operations.C-2 Primary Instruction Cache Operations Coprocessor Hazards
List Tables
List Tables
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1.10 1.11 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19
Figure Title
Page
RV4700 Block Diagram. RV4700 Registers. Instruction Formats Big-Endian Byte Ordering 1-11 Little-Endian Byte Ordering 1-11 Little-Endian Data Doubleword 1-12 Big-Endian Data Doubleword. 1-12 Big-Endian Misaligned Word Addressing 1-13 Little-Endian Misaligned Word Addressing 1-13 RV4700 Registers 1-14 Typical System Block Diagram 1-20 Instruction Formats Instruction Pipeline Stages Pipeline Activities Pipeline Branch Delay Pipeline Load Delay Correspondence Pipeline Stage Interlock Condition. Exception Detection Data Cache Miss. Instruction cache miss. Overview Virtual-to-Physical Address Translation 32-bit Virtual Address Translation 64-bit Virtual Address Translation User Mode Virtual Address Space Supervisor Mode Virtual Address Space Kernel Mode Address Space Registers TLB. 4-13 Format Entry 4-14 Fields PageMask EntryHi Registers. 4-14 Fields EntryLo0 EntryLo1 Registers 4-15 Index Register. 4-16 Random Register 4-16 Wired Register Boundary 4-18 Wired Register 4-18 Processor Revision Identifier Register Format. 4-19 Config Register Format 4-19 LLAddr Register Format 4-21 TagLo TagHi Register (P-cache) Formats. 4-21 Address Translation 4-22 Context Register Format BadVAddr Register Format. Count Register Format. Compare Register Format Status Register Cause Register Format Register Format XContext Register Format Register Format
xiii
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20
List Figures CacheErr Register Format. 5-10 ErrorEPC Register Format 5-11 Reset Exception Processing. 5-12 Cache Error Exception Processing 5-12 Soft Reset Exception Processing. 5-12 General Exception Processing (Except Reset, Soft Reset, NMI, Cache Error) 5-13 General Exception Handler (HW). 5-25 General Exception Servicing Guidelines (SW) 5-26 TLB/XTLB Miss Exception Handler (HW) 5-27 TLB/XTLB Exception Servicing Guidelines (SW). 5-28 Cache Error Exception Handling (HW) Servicing Guidelines (SW). 5-29 Reset, Soft Reset Exception Handling (HW) Servicing Guidelines (SW) 5-30 Functional Block Diagram Registers Implementation/Revision Register Control/Status Register Assignments Control/Status Register Cause, Flag, Enable Fields Single-Precision Floating-Point Format Double-Precision Floating-Point Format. Binary Fixed-Point Format. Instruction Pipeline 6-13 Control/Status Register Exception/Flag/Trap/Enable Bits RV4700 Processor Signals Power-on Reset. Cold Reset Warm Reset Signal Transitions 10-1 Clock-to-Q Delay 10-1 Processor Clocks, PClock-to-SClock Division 10-3 Passive Components 10-4 RV4700 Network 10-5 RV4700 Processor Phase-Locked System 10-6 Gate-Array System Without Phase Lock, Using RV4700 Processor 10-7 Gate Array CMOS System Without Phase Lock, Using RV4700 Processor. 10-9 Logical Hierarchy Memory. 11-1 Cache Support RV4700. 11-2 RV4700 Primary I-Cache Line Format. 11-3 RV4700 8-Word Primary Data Cache Line Format. 11-4 Primary Cache Data Organization. 11-5 Primary Data Cache State Diagram. 11-7 Synchronization with Test-and-Set 11-9 Synchronization Using Counter. 11-10 Test-and-Set using 11-11 Counter Using 11-12 System Interface Buses 12-2 State RdRdy* Signal Read Requests 12-3 State WrRdy* Signal Write Requests 12-3 System Interface Register-to-Register Operation 12-4
Figure 5.21 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 10.1 10.2 10.3 10.4 10.5 10.6 10.7
Figure 10.8 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 12.1 12.2 12.3 12.4
List Figures Figure 12.5 Figure 12.6 Figure Figure Figure Figure Figure Figure Figure Figure Figure 12.7 12.8 12.9 12.10 12.11 12.12 12.13 12.14 12.15
List Figures Requests System Events 12-6 Back-to-Back Write Cycle Timing (R4000 compatible mode) 12-7 Processor Requests 12-7 Processor Request 12-8 External Requests 12-9 External Request 12-9 Read Response 12-11 Processor Read Request Protocol 12-16 Uncached Read-External Cycles. 12-18 Processor Read Cycle 12-19 Processor Noncoherent Word Write Request Protocol 12-20 Write re-issue 12-20 Pipelined Writes 12-21 Processor Noncoherent Block Write Request Protocol 12-22 Processor Write Requests, Second Write Delayed Assertion WrRdy* 12-23 Arbitration Protocol External Requests 12-24 External Read Request, System Interface Master State 12-25 System Interface Release External Null Request 12-26 External Write Request, with System Interface initially Master State. 12-27 12-28 Block Read Response With Zero Wait-State 12-28 Block Read Transaction With Wait-State. 12-29 Read Response, Reduced Data Rate, System Interface Slave State. 12-30 System Interface Command Syntax Definition 12-33 Read Request SysCmd Definition 12-33 Write Request SysCmd Definition 12-34 Null Request SysCmd Definition. 12-36 Data Identifier SysCmd Definition 12-36 Retrieving Data Block Sequential Order 12-39 Retrieving Data Subblock Order. 12-39 Interrupt Register Bits Enables 13-1 RV4700 Interrupt Signals 13-2 RV4700 Nonmaskable Interrupt Signal 13-2 Masking RV4700 Interrupts 13-3 Instruction Formats Load Store Instruction Format Computational Instruction Format. Encoding Instructions. B-45
Figure 12.16 Figure 12.17 Figure 12.18 Figure 12.19 Figure 12.20 Figure 12.21 Figure 12.22 Figure 12.23 Figure 12.24 Figure 12.25 Figure 12.26 Figure 12.27 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 12.28 12.29 12.30 12.31 12.32 12.33 12.34 13.1 13.2 13.3 13.4
List Figures
List Figures
Overview
Chapter
IDT79RV4700 (R47001) supports wide variety processor-based applications. Because power consumption-coupled with high performance-the RV4700 well suited wide variety embedded applications that include laser printers, X-terminals, internetworking equipment, imaging equipment, high-end video games. RV4700 also well-suited high-performance desktop applications such WindowsNT desktop notebook systems, workstations.
Introduction
FEATURES
True 64-bit microprocessor 64-bit integer operations 64-bit floating-point operations 64-bit registers 64-bit virtual address space High-performance microprocessor Dhrystone MIPS 200MHz peak MFLOP/s 200MHz Two-way associative caches Simple 5-stage pipeline High level integration 64-bit, integer 64-bit floating-point unit 16KB instruction cache 16KB data cache Flexible with large, fully associative Low-power operation 3.3V power supply Dynamic power management Standby mode reduces internal power Fully software pin-compatible with 40XX Processor Family Available 179-pin 208-pin MQUAD Available 100-200MHz, with mode dependent output clock frequencies 64GB physical address space Processor family wide variety embedded applications switches Routers Color printers
Device Overview
RV4700 brings high-level integration designed highperformance high-bandwidth computing. elements RV4700 briefly described below. overview these blocks found here, with more detailed information each block presented subsequent chapters.
R4700 implies part, available RV4700 implies 3.3V part. majority design activity-and such part reference throughout this manual-is centered high speed 3.3V parts.
Overview
Chapter
Figure shows block level representation functional units within RV4700.
Data Data DTLB Physical Store Buffer SysAD Instruction Select Write Buffer Read Buffer Data Instruction DBus IBus Control Floating-point Register File Floating-point Control Unpacker/Packer AuxTag Load Aligner Integer Register File Integer/Address Adder Data Virtual Shifter/Store Aligner Logic Unit Incrementer System/Memory Control Branch Adder Instruction Virtual Program Counter Integer Control Joint Address Buffer Instruction ITLB Physical Instruction Instruction Register Data Instruction
Floating-point Add/Sub/Cvt/Div/Sqrt Integer Divide
Coprocessor
Floating-point/Integer Multiply Phase Lock Loop, Clocks
Figure RV4700 Block Diagram
Pipeline Overview
RV4700 uses 5-stage pipeline similar IDT79R3000. simplicity this pipeline allows RV4700 lower-cost lowerpower than super-scalar super-pipelined processors. Unlike R3000, however, RV4700 does virtual-to-physical translation parallel with cache access. This allows RV4700 operate over twice frequency R3000 support larger address translation. Compared 8-stage R4000 pipeline, RV4700 more efficient (requires fewer stalls). This because branch load latency RV4700 shorter than R4000 (both cycles RV4700 cycles respectively R4000). internal pipeline RV4700 processor operates twice frequency master clock, discussed Chapter processor achieves high throughput pipelining cache accesses, shortening register access times, implementing virtual-indexed primary caches, allowing latency certain functional units span more than pipeline clock cycles. Refer Chapter detailed discussion pipeline operation, including descriptions delay instructions, interruptions pipeline flow caused interlocks exceptions, RV4700 implementation store buffer. Refer Chapter detailed discussion pipeline.
Overview
Chapter
Register Overview
RV4700 thirty-two general purpose registers. These registers used scalar integer operations address calculation. register file consists read ports write port, fully bypassed minimize operation latency pipeline. Figure shows RV4700 registers.
General Purpose Registers Multiply Divide Registers
Program Counter
Figure RV4700 Registers
general purpose registers have assigned functions: hardwired value zero, used target register instruction whose result discarded. also used source when zero value needed. used implicit return destination address register series instructions. three special purpose registers: Program Counter register Multiply Divide register higher result Multiply Divide register lower result Multiply Divide registers (HI, store: product integer multiply operations, quotient remainder integer divide operations. RV4700 processor Program Status Word (PSW) register such; this covered Status Cause registers incorporated within System Control Coprocessor (CP0). registers described later this chapter.
Overview
Chapter
Instruction Overview
Each instruction bits long. shown Figure 1.3, there three instruction formats: immediate (I-type) jump (J-type) register (R-type)
I-Type (Immediate)
target
immediate
J-Type (Jump)
R-Type (Register)
funct
Figure Instruction Formats
Each format contains number different instructions, which described further this chapter. Fields instruction formats described Chapter Instruction decoding simplified limiting number formats these three. This limitation means that more complicated (and less frequently used) operations addressing modes synthesized compiler, using sequences these same simple instructions. instruction further divided into following groupings: Load Store instructions move data between memory general registers. They immediate (I-type) instructions, since only addressing mode supported base register plus 16-bit, signed immediate offset. Computational instructions perform arithmetic, logical, shift, multiply, divide operations values registers. They include register (R-type, which both operands result stored registers) immediate (I-type, which operand 16-bit immediate value) formats. Jump Branch instructions change control flow program. Jumps always made paged, absolute address formed combining 26-bit target address with high-order bits Program Counter (J-type format) register address (R-type format). Branches have 16-bit offsets relative program counter (I-type). Jump Link instructions save their return address register Coprocessor instructions perform operations coprocessors. Coprocessor load store instructions I-type. Coprocessor (system coprocessor) instructions perform operations registers control memory management exception handling facilities processor standby mode power management. These listed Table 1.17. Special instructions perform system calls breakpoint operations. These instructions always R-type. Exception instructions cause branch general exception-handling vector based upon result comparison. These instructions occur both R-type (both operands result registers) I-type (one operand 16-bit immediate value) formats.
Overview
Chapter
Chapter provides more detail about these instructions, Appendix gives complete description each. Table through Table 1.16 list instructions common MIPS R-Series processors, along with level which they first appeared. last column each table refers MIPS level which instruction first appeared. Table 1.17 lists instructions.
OpCode Description Load Byte Load Byte Unsigned Load Halfword Load Halfword Unsigned Load Word Load Word Left Load Word Right Store Byte Store Halfword Store Word Store Word Left Store Word Right
instruction first appeared. Table Instruction Set: Load Store Instructions
MIPS Level1
Note: 1For Tables through 1.17 this column refers level which
OpCode ADDI ADDIU SLTI SLTIU ANDI XORI
Description Immediate Immediate Unsigned Less Than Immediate Less Than Immediate Unsigned Immediate Immediate Exclusive Immediate Load Upper Immediate
MIPS Level
Table Instruction Set: Arithmetic Instructions (ALU Immediate)
Overview
Chapter
OpCode ADDU SUBU SLTU
Description Unsigned Subtract Subtract Unsigned Less Than Less Than Unsigned Exclusive
MIPS Level
Table Instruction Set: Arithmetic (3-Operand, R-Type)
OpCode MULT MULTU DIVU MFHI MTHI MFLO MTLO
Description Multiply Multiply Unsigned Divide Divide Unsigned Move From Move Move From Move
MIPS Level
Table Instruction Set: Multiply Divide Instructions
OpCode JALR BLEZ BGTZ BLTZ BGEZ BLTZAL BGEZAL
Description Jump Jump Link Jump Register Jump Link Register Branch Equal Branch Equal Branch Less Than Equal Zero Branch Greater Than Zero Branch Less Than Zero Branch Greater Than Equal Zero Branch Less Than Zero Link Branch Greater Than Equal Zero Link
MIPS Level
Table Instruction Set: Jump Branch Instruction
Overview
Chapter
OpCode SLLV SRLV SRAV
Description Shift Left Logical Shift Right Logical Shift Right Arithmetic Shift Left Logical Variable Shift Right Logical Variable Shift Right Arithmetic Variable
MIPS Level
Table Instruction Set: Shift Instructions
OpCode LWCz SWCz MTCz MFCz CTCz CFCz COPz BCzT BCzF
Description Load Word Coprocessor Store Word from Coprocessor Move Coprocessor Move From Coprocessor Move Control Coprocessor Move Control From Coprocessor Coprocessor Operation Branch Coprocessor True Branch Coprocessor False
MIPS Level
Table Instruction Set: Coprocessor Instructions
OpCode SYSCALL BREAK
Description System Call Break
MIPS Level
Table Instruction Set: Special Instructions
OpCode
Description Load Doubleword Load Doubleword Left
MIPS Level
Table MIPS 2/MIPS Additional: Load Store Instructions
Overview OpCode SYNC Description Load Doubleword Right Load Linked Load Linked Doubleword Load Word Unsigned Store Conditional Store Conditional Doubleword Store Doubleword Store Doubleword Left Store Doubleword Right Sync
Chapter MIPS Level
Table MIPS 2/MIPS Additional: Load Store Instructions
OpCode DADDI DADDIU
Description Doubleword Immediate Doubleword Immediate Unsigned
MIPS Level
Table 1.10 MIPS 2/MIPS Additional: Arithmetic Instructions (ALU Immediate)
OpCode DMULT DMULTU DDIV DDIVU
Description Doubleword Multiply Doubleword Multiply Unsigned Doubleword Divide Doubleword Divide Unsigned
MIPS Level
Table 1.11 MIPS 2/MIPS Additional: Multiply Divide Instructions
Overview
Chapter
OpCode BEQL BNEL BLEZL BGTZL BLTZL BGEZL BLTZALL
Description Branch Equal Likely Branch Equal Likely Branch Less Than Equal Zero Likely Branch Greater Than Zero Likely Branch Less Than Zero Likely Branch Greater Than Equal Zero Likely Branch Less Than Zero Link Likely
MIPS Level
BGEZALL Branch Greater Than Equal Zero Link Likely BCzTL BCzFL Branch Coprocessor True Likely Branch Coprocessor False Likely
Table 1.12 MIPS 2/MIPS Additional: Branch Instructions
OpCode DADD DADDU DSUB DSUBU
Description Doubleword Doubleword Unsigned Doubleword Subtract Doubleword Subtract Unsigned
MIPS Level
Table 1.13 MIPS 2/MIPS Additional: Arithmetic Instructions (3-operand, R-type)
OpCode DSLL DSRL DSRA DSLLV DSRLV DSRAV DSLL32 DSRL32 DSRA32
Description Doubleword Shift Left Logical Doubleword Shift Right Logical Doubleword Shift Right Arithmetic Doubleword Shift Left Logical Variable Doubleword Shift Right Logical Variable Doubleword Shift Right Arithmetic Variable Doubleword Shift Left Logical Doubleword Shift Right Logical Doubleword Shift Right Arithmetic
MIPS Level
Table 1.14 MIPS 2/MIPS Additional: Shift Instructions
Overview
Chapter
OpCode TGEU TLTU TGEI TGEIU TLTI TLTIU TEQI TNEI
Description Trap Greater Than Equal Trap Greater Than Equal Unsigned Trap Less Than Trap Less Than Unsigned Trap Equal Trap Equal Trap Greater Than Equal Immediate Trap Greater Than Equal Immediate Unsigned Trap Less Than Immediate Trap Less Than Immediate Unsigned Trap Equal Immediate Trap Equal Immediate
MIPS Level
Table 1.15 MIPS 2/MIPS Additional: Exception Instructions
OpCode DMFCz DMTCz LDCz SDCz
Description Doubleword Move From Coprocessor Doubleword Move Coprocessor Load Double Coprocessor Store Double Coprocessor
MIPS Level
Table 1.16 MIPS 2/MIPS Additional: Coprocessor Instructions
OpCode DMFC0 DMTC0 MTC0 MFC0 TLBR TLBWI TLBWR TLBP CACHE ERET WAIT
Description Doubleword Move From Doubleword Move Move Move from Read Indexed Entry Write Indexed Entry Write Random Entry Probe Matching Entry Cache Operation Exception Return Enter Standby mode
Table 1.17 Instructions
MIPS Level R4xxx only R4xxx only
Overview
Chapter
Data Formats Addressing RV4700 processor uses four data formats: 64-bit doubleword, 32-bit word, 16-bit halfword, 8-bit byte. Byte ordering within each larger data formats-halfword, word, doubleword-can configured either big-endian little-endian order. Endianness refers location byte within multi-byte data structure. Figures show ordering bytes within words ordering words within multiple-word structures big-endian little-endian conventions. When R4000 processor configured big-endian system, byte most-significant (leftmost) byte, thereby providing compatibility with 68000 conventions. Figure shows this configuration.
Higher Word Address Address Lower Address
Figure Big-Endian Byte Ordering
When configured little-endian system, byte always least, significant (rightmost) byte, which compatible with iAPX conventions. Figure shows this configuration.
Higher Word Address Address Lower Address
Figure Little-Endian Byte Ordering
this text, always least-significant (rightmost) bit; thus, designations always little-endian (although instructions explicitly designate positions within words).
Overview
Chapter
Figures show little-endian big-endian byte ordering doublewords.
Most-significant byte
Least-significant byte Word
Byte Halfword Byte
Bits Byte
Figure Little-Endian Data Doubleword
Most-significant byte
Least-significant byte Word
Byte Halfword Byte Bits Byte
Figure Big-Endian Data Doubleword
uses byte addressing halfword, word, doubleword accesses with following alignment constraints: Halfword accesses must aligned even byte boundary 4.). Word accesses must aligned byte boundary divisible four 8.). Doubleword accesses must aligned byte boundary divisible eight 16.). following special instructions load store words that aligned 4-byte (word) 8-word (doubleword) boundaries:
These instructions used pairs provide addressing misaligned words. Addressing misaligned data incurs additional instruction cycle over that required addressing aligned data. This extra cycle because extra instruction "pair" (e.g., form pair). Also note that moves unaligned data same rate hardware mechanism.
Overview
Chapter
Figures show access misaligned word that byte address
Higher Address
Lower Address
Figure Big-Endian Misaligned Word Addressing
Higher Address Lower Address
Figure Little-Endian Misaligned Word Addressing
Coprocessors (CP0-CP2)
MIPS (MIPS III) RV4700 (and R4000/R4400) defines three coprocessors (designated through CP2): Coprocessor (CP0) incorporated chip supports virtual memory system exception handling. also referred System Control Coprocessor. Coprocessor (CP1) incorporated RV4700, implements MIPS floating-point instruction set. Coprocessor (CP2) reserved future use. described sections that follow. System Control Coprocessor, translates virtual addresses into physical addresses manages exceptions transitions between kernel, supervisor, user states. also controls cache subsystem, well providing diagnostic control error recovery facilities. also used control power management RV4700. This standby mode used reduce power consumption internal core CPU. standby mode entered executing WAIT instruction with SysAD idle exited interrupt. This feature discussed Appendix
Overview
Chapter
registers shown Figure 1.10 described Table 1.18 page 1.15 manipulate memory management exception handling capabilities CPU. Note: Access reserved undefined register results undefined. exception result.
Register Name Index Random EntryLo0 EntryLo1 Context PageMask Wired
Reg.
Register Name Config LLAddr
Reg.
XContext
BadVAddr Count EntryHi Compare Cause PRId
CacheErr TagLo TagHi ErrorEPC
Exception Processing
Memory Management
Reserved
Figure 1.10 RV4700 Registers
Overview
Chapter
Number Register 21-25 Index Random EntryLo0 EntryLo1 Context PageMask Wired BadVAddr Count EntryHi Compare Cause PRId Config LLAddr XContext CacheErr TagLo TagHi ErrorEPC
Description Programmable pointer into array Pseudorandom pointer into array (read only) half entry even virtual page (VPN) half entry virtual page (VPN) Pointer kernel virtual page table entry 32bit address spaces Page Mask Number wired entries Reserved virtual address Timer Count High half entry Timer Compare Status register Cause last exception Exception Program Counter Processor Revision Identifier Configuration register Load Linked Address Reserved Pointer kernel virtual table 64-bit address spaces Reserved Secondary-cache error checking correcting (ECC) Primary parity Cache Error Status register Cache register Cache register Error Exception Program Counter Reserved
Table 1.18 System Control Coprocessor (CP0) Register Definitions
Overview
Chapter
Floating-Point Co-Processor, RV4700 incorporates entire floating-point co-processor chip, including floating-point register file execution units. floatingpoint co-processor forms "seamless" interface with integer unit, decoding executing instructions parallel with integer unit. RV4700 implements enhanced operations, resulting improved peak MFLOP rate. Floating-Point Units RV4700 floating-point execution units supports single double precision arithmetic, specified IEEE Standard 754. execution unit broken into separate multiply unit combined add/convert/ divide/square root unit. Overlap multiplies add/subtract supported. multiplier partially pipelined, allowing multiply begin every cycles. R3010 R4000, RV4700 maintains fully precise floatingpoint exceptions while allowing both overlapped pipelined operations. Precise exceptions extremely important mission-critical environments, such ADA, highly desirable debugging environment. floating-point unit's operation includes floating-point add, subtract, multiply, divide, square root, conversion between fixed-point floating-point format, conversion among floating-point formats, floating-point compare. These operations comply with IEEE Standard 754. Table 1.19 shows latencies some floating-point instructions internal processor cycles. pipelining, repeat rates higher. Also note that many operations autonomous parallel.
Operation SQRT FLOAT LWC1, LDC1 SWC1, SDC1
Table 1.19
Single Precision
Double Precision
RV4700 Floating-Point Latency Cycles
Overview
Chapter
Virtual-to-Physical Address Mapping
RV4700 provides three modes operation: user mode supervisor mode kernel mode This mechanism available system software provide secure environment user processes. Bits status register determine mode operation. user mode, RV4700 provides single, uniform virtual address space 256GB (2GB when Status.UX When operating kernel mode, four distinct virtual address spaces, totalling 1024GB (4GB when Status.KX simultaneously available differentiated high-order bits virtual address. RV4700 processors also support supervisor mode which virtual address space 256.5GB (2.5GB when Stauts.SX divided into three regions based high-order bits virtual address. When RV4700 uses 64-bit virtual addresses, address space layouts upward compatible extension 32-bit virtual address space layout. detailed description addressing given Chapter Joint fast virtual-to-physical address decoding, RV4700 uses large, fully associative which maps Virtual pages their corresponding physical addresses. organized pairs even-odd entries, maps virtual address address space identifier into large, 64GB physical address space. mechanisms provided assist controlling amount mapped space, replacement characteristics various memory regions. First, page size configured, per-entry basis, page size 16MB multiples register loaded with page size mapping, that size entered into when entry written. Thus, operating systems provide special purpose maps; example, typical frame buffer memory mapped using only entry. second mechanism controls replacement algorithm when miss occurs. RV4700 provides random replacement algorithm select entry written with mapping; however, processor provides mechanism whereby system specific number mappings locked into TLB, thus avoid being randomly replaced. This facilitates design real-time systems, allowing deterministic access critical software. joint also contains information control cache coherency protocol each page. Specifically, each page attribute bits determine whether coherency algorithm uncached, non-coherent write-back, non-coherent write-through write-allocate, non-coherent write-through write-allocate, sharable, exclusive, update. Noncoherent write-back typically used both code data RV4700; write-through modes support more efficient frame buffer accesses than R4000 family. coherent modes supported R4000 compatibility generate different transaction types system interface; cache coherency supported however.
Overview
Chapter
Instruction RV4700 also incorporates 2-entry instruction TLB. Each entry maps page. instruction improves performance allowing instruction address translation occur parallel with data address translation. When miss occurs instruction address translation, least-recently used ITLB entry filled from JTLB. operation ITLB invisible user. Data RV4700 also incorporates 4-entry data TLB. Each entry maps page. data improves performance allowing data address translation occur parallel with data address translation. When miss occurs data address translation, DTLB filled from JTLB. DTLB refill pseudo-LRU: least recently used entry least recently used half filled. operation DTLB invisible user.
Cache Memory
order keep RV4700's high-performance pipeline full operating efficiently, RV4700 incorporates on-chip instruction data caches that accessed single processor cycle. Each cache 64-bit data path accessed parallel. cache subsystem provides integer floating-point units with aggregate bandwidth 1.6GB second system clock frequency 50MHz. Furthermore, large, Two-way associative caches increase emulation performance Windows applications when running under Windows Instruction Cache RV4700 incorporates two-way associative on-chip instruction cache. This virtually indexed, physically tagged cache 16KB size protected with word parity. Because cache virtually indexed, virtual-to-physical address translation occurs parallel with cache access, thus further increasing performance allowing these operations occur simultaneously. holds 24-bit physical address valid bit, parity protected. instruction cache 64-bits wide, refilled accessed single processor cycle. Instruction fetches require only bits cycle, peak instruction bandwidth MB/sec 175MHz. Sequential accesses take advantage 64-bit fetch reduce power dissipation, cache miss refill writes bits cycle minimize cache miss penalty. line size eight instructions bytes) maximize performance. Data Cache fast, single cycle data access, RV4700 includes 16KB on-chip data cache that two-way associative with fixed 32-byte (eight words) line size. Both D-cache I-cache accessed each pipeline cycle; thus, data bandwidth 1400 MB/sec MHz, addition MB/sec instruction bandwidth. data cache protected with byte parity protected with single parity bit. virtually indexed physically tagged allow simultaneous address translation data cache access normal write policy writeback, which means that store cache line does immediately cause memory updated. This increases system performance reducing traffic eliminating bottleneck waiting each store operation finish before issuing subsequent memory operation. Software however select write-through perpage basis when appropriate, such frame buffers.
Overview
Chapter
Associated with Data Cache store buffer. When RV4700 executes Store instruction, this single-entry buffer gets written with store data while comparison performed. matches, then data written into Data Cache next cycle that Data Cache accessed (the next non-load cycle). store buffer allows RV4700 execute store every processor cycle perform back-toback stores without penalty. Write buffer Writes external memory, whether cache miss writebacks stores uncached write-through addresses, on-chip write buffer. write buffer holds four 64-bit address data pairs cache line written back. entire buffer used data cache writeback allows processor proceed parallel with memory update. uncached write-through stores, write buffer significantly increases performance over R4000 family processors. RV4700 Clocks RV4700 number clocks user. First, there pipeline clock, PClock. This clock used pipeline pipeline related functions internal RV4700. times MasterClock frequency. next clock system interface clock, SClock. This also internal clock used sample data system interface clock data into processor system interface output registers. SClock divided version PClock. divisor selected boot time. There three external clocks. (Some outputs replicated minimize loading.) MasterOut same frequency MasterClock used clock certain external logic. other clocks used external agent. These TClock, Transmit clock, RClock, Receive clock. TClock used clock output registers (signals transmitted RV4700) external agent same frequency SClock. RClock used clock input register (signals received from RV4700) external agent. also same frequency SClock phase leads SClock TClock 25%. RV4700 implements on-chip eliminate effects clock skew.
Overview
Chapter
System Interface
RV4700 supports 64-bit system interface that compatible with R4000PC system interface. This interface operates from clocks provided RV4700, TClock[1:0] RClock[1:0], division pipeline clock. interface consists 64-bit Address/Data with check bits 9-bit command bus. addition, there handshake signals interrupt inputs. interface simple timing specification capable transferring data between processor memory peak rate 400MB/sec 50MHz. Figure 1.11 shows typical system using RV4700. this example there DRAM, boot EPROM optional secondary cache.
Address Boot DRAM (80ns) Cache
(Optional) Control
SCSI
ENET
Memory Controller
RV4700
Figure 1.11 Typical System Block Diagram
Instruction Summary
Chapter
Introduction
This chapter provides overview central processing unit (CPU) instruction set. more detailed descriptions individual instructions, refer Appendix this manual. overview floating-point unit (FPU) instruction Chapter refer Appendix detailed descriptions individual instructions.
Instruction Formats
Each instruction consists single 32-bit word, aligned word boundary. There three instruction formats-immediate (I-type), jump (J-type), register (R-type)-as shown Figure 2.1. small number instruction formats simplifies instruction decoding (thus higher frequency operations) allowing compiler synthesize more complicated (and less frequently used) operations addressing modes from these three formats needed.
I-Type (Immediate)
J-Type (Jump)
immediate
R-Type (Register)
target
funct
Figure Legend: 6-bit operation code 5-bit source register specifier 5-bit target (source/destination) register branch condition immediate 16-bit immediate value, branch displacement address displacement target 26-bit jump target address 5-bit destination register specifier 5-bit shift amount funct 6-bit function field
Figure Instruction Formats
MIPS architecture, coprocessor instructions implementationdependent; refer Appendix details individual Coprocessor instructions.
Instruction Summary
Chapter
Load Store Instructions
Load store immediate (I-type) instructions that move data between memory general registers. only addressing mode that load store instructions directly support base register plus 16-bit signed immediate offset. Scheduling Load Delay Slot load instruction that does allow result used instruction immediately following called delayed load instruction. instruction slot immediately following this delayed load instruction referred load delay slot. RV4700 processor, instruction immediately following load instruction request contents loaded register, however, such cases, hardware interlocks insert additional real cycles. Consequently, scheduling load delay slots desirable, both performance R-Series (e.g., R3051) processor compatibility. However, scheduling load delay slots absolutely required. Defining Access Types Access type indicates size RV4700 processor data item loaded stored, load store instruction opcode. Access types defined Appendix Regardless access type byte ordering (endianness), address given specifies low-order byte addressed field. big-endian configuration, low-order byte most-significant byte; littleendian configuration, low-order byte least-significant byte. access type, together with three low-order bits address, define bytes accessed within addressed doubleword, which shown Table page 2-3.
Instruction Summary
Chapter
Only combinations shown Table permissible. other combinations cause address error exceptions. Appendix individual descriptions load store instructions.
Access Type Mnemonic (Value) Order Bytes Accessed Address Bits endian (63-31-0) Byte Sextibyte Quintibyte Word Triplebyte Halfword Byte
Little endian (63-31-0) Byte
Doubleword Septibyte
Table Byte Access within Doubleword
Instruction Summary
Chapter
Computational Instructions
Computational instructions either: register (R-type) format, which both operands registers, immediate (I-type) format, which operand 16-bit immediate. Computational instructions perform following operations register values: arithmetic logical shift multiply divide These operations following four categories computational instructions: Immediate instructions three-Operand Register-Type instructions shift instructions multiply divide instructions 64-bit Virtual Address Operations with 32-bit operands Operands 32-bit operand opcodes must sign-extended form. 32bit operand opcodes include non-doubleword operations, such ADD, ADDU, SUB, SUBU, ADDI, SLL, SRL, SRA, SLLV, etc. result operations that incorrect sign-extended 32-bit values unpredictable. Cycle Timing Multiply Divide Instructions MFHI MFLO instructions (described Appendix interlocked that attempt read them before prior multiply divide instructions complete delays execution these instructions until prior instructions finish. Table gives number processor cycles (PCycles) required resolve interlock stall between various multiply divide instructions, subsequent MFHI MFLO instruction.
Instruction MULT MULTU DIVU DMULT DMULTU DDIV DDIVU RV4700
Table Multiply/Divide Instruction Cycle Timing
more information about computational instructions, refer individual instruction described Appendix
Instruction Summary
Chapter
Jump Branch Instructions
Jump branch instructions change control flow program. jump branch instructions occur with delay instruction: that instruction immediately following jump branch (this known instruction delay slot) always executes while target instruction being fetched from storage. Overview Jump Instructions Subroutine calls high-level languages usually implemented with Jump Jump Link instructions, both which J-type instructions. J-type format, 26-bit target address shifts left bits combines with high-order bits current program counter form absolute address. Returns, dispatches, large cross-page jumps usually implemented with Jump Register Jump Link Register instructions. Both R-type instructions that take 32-bit 64-bit byte address contained general purpose registers. more information about jump instructions, refer individual instruction described Appendix Overview Branch Instructions branch instruction target addresses computed adding address instruction delay slot 16-bit offset (shifts left bits sign-extended bits). branches occur with delay instruction. conditional branch likely taken, instruction delay slot nullified. regular conditional branches, delay slot always executed. more information about branch instructions, refer individual instruction described Appendix
Special Instructions
Special instructions allow software initiate traps; they always R-type. more information about special instructions, refer individual instruction described Appendix
Exception Instructions
Exception instructions extensions MIPS ISA. more information about exception instructions, refer individual instruction described Appendix
Coprocessor Instructions
Coprocessor instructions perform operations their respective coprocessors. Coprocessor loads stores I-type, coprocessor computational instructions have coprocessor-dependent formats. Individual coprocessor instructions described Appendices (for CP0) (for FPU, CP1). instructions perform operations specifically System Control Coprocessor registers manipulate memory management exception handling facilities processor. Appendix contains details instructions.
Instruction Summary
Chapter
Pipeline
Chapter
Introduction
This chapter describes basic operation pipeline, which includes descriptions delay instructions (instructions that follow branch load instruction pipeline), interruptions pipeline flow caused interlocks exceptions, RV4700 implementation uncached store buffer. pipeline described later chapter.
Pipeline Operation
RV4700 uses 5-stage pipeline, similar R3000. simplicity this pipeline allows RV4700 lower cost lower power than super-scalar super-pipelined processors. Unlike R3000, RV4700 does virtual-to-physical translation parallel with cache access. This allows RV4700 operate over twice frequency R3000 support larger address translation. Compared 8-stage R4000 pipeline, RV4700 requires fewer stalls therefore more efficient. Once pipeline been filled, five instructions executed simultaneously. Figure shows five stages instruction pipeline; next section describes pipeline stages.
cycle
Figure Legend 1I-1R 2A-2D 1D-2D Instruction cache access Instruction virtual-to-physical address translation ITLB Data cache access load align Data virtual-to-physical address translation DTLB virtual-to-physical address translation JTLB Register file read Bypass calculation 1A-2A Instruction decode Integer add, logical, shift Data virtual address calculation Store align Branch decision Register file write
Figure Instruction Pipeline Stages
Pipeline
Chapter
Pipeline Stages
This section describes each phases five pipeline stages. Each stage phases: Instruction Fetch, Phase Instruction Fetch, Phase Register Fetch, Phase Register Fetch, Phase Execution, Phase Execution, Phase Data Fetch, Phase Data Fetch, Phase Write Back, Phase Write Back, Phase Instruction Fetch, Phase During phase instruction address translation begins ITLB. Instruction Fetch, Phase During phase, instruction cache fetch begins instruction address translation ITLB continues. Register Fetch, Phase During phase, following occurs: instruction cache fetch finishes. instruction cache checked against page frame number obtained from ITLB. Register Fetch, Phase During phase, following occurs: instruction decoder decodes instruction. required operands fetched from register file. Make decision either issue slip (for interlock condition). branch, branch address calculated. Execution, Phase During phase, following occurs: result from stages bypassed. arithmetic logic unit (ALU) starts integer arithmetic, logical shift operation. calculates data virtual address load store instructions. determines whether branch condition true. Execution, Phase During phase, following occurs: integer arithmetic, logical shift operation will complete. data cache access will start. Store data shifted specified byte position(s). data virtual-to-physical address translation DTLB will start. Data Fetch, Phase During phase, following occurs: data cache access will continue. data address translation DTLB completes. virtual-to-physical address translation JTLB will start.
Pipeline
Chapter
Data Fetch, Phase During phase, following occurs: data cache access will finish data shifted down extended. virtual-to-physical address translation JTLB will finish. data cache checked against from DTLB JTLB data cache access. Write Back, Phase This phase used internally processor resolve exceptions, preparation register file write. Write Back, Phase register-to-register load instructions, result written back register file during stage. Branch instructions perform operation during this stage. Figure shows activities occurring during each pipeline stage, load, store, branch instructions.
Clock
Stage
IFetch Decode
ITLBM
ITLBR
IDEC DCAD DCAA JTLB1 DTLBM DTLBR DCLA JTLB2
Load/Store
Branch
ITLBM IDEC DCAA JTLB1 DTLBM
Instruction cache address decode Instruction address translation match Instruction check Instruction decode Operation stage Data virtual address calculation Data cache array access Address translation JTLB stage Data address translation match Data check Data cache write
ITLBR DCAD DCLA JTLB2 DTLMR
Instruction cache array access Instrustion address translation read Register operand fetch Operation stage Write back register file Data cache address decode Data cache load align Address translation JTLB stage Data address translation read Store align Branch address calculation
Figure Pipeline Activities
Pipeline
Chapter
Branch Delay
pipeline branch delay cycle load delay cycle. one-cycle branch delay result branch decision logic operating during pipeline phase branch instruction. This allows branch target address calculated previous phase used instruction access following phase. pipeline will begin fetch branch path well fall-through path cycle following delay slot. After branch decision made, processor will continue with fetch either branch path (for taken branch) fall-through path (for non-taken branch). Figure illustrates branch delay.
Cycle
Cycle
Cycle
Cycle
Cycle
Branch Delay
*Branch fall-through address calculated **Address selection made
Figure Pipeline Branch Delay
Load Delay
completion load pipeline phase produces operand that available pipeline phase instruction following load delay slot. Figure shows load delay pipeline cycle.
Cycle
Cycle
Cycle
Cycle
Cycle
Load Delay
Figure Pipeline Load Delay
Interlock Exception Handling
Smooth pipeline flow interrupted when cache misses exceptions occur, when data dependencies detected. Interruptions handled using hardware, such cache misses, referred interlocks, while those that handled using software called exceptions.
Pipeline
Chapter
There types interlocks: stalls, which resolved halting pipeline slips, which require back pipeline advance while front pipeline held static each cycle, exception interlock conditions checked active instructions. Because each exception interlock condition corresponds particular pipeline stage, condition traced back particular instruction exception/interlock stage, shown Figure 3.5. instance, Reserved Instruction (RI) exception raised execution stage.
Pipeline Stage State Stall Slip MDSt FCBsy Exceptions ITLB IPErr DTLB TLBMod Intr
Figure Correspondence Pipeline Stage Interlock Condition
Reset DPErr Trap
description pipeline interlocks exceptions listed Figure 3.5, refer Table Table 3.2, which follow.
Pipeline
Chapter
Table Table describe pipeline interlocks exceptions listed Figure 3.5.
Exception ITLB Intr IPErr ExTrap DTLB TLBMod DPErr Reset Description Instruction Translation Address Exception External Interrupt Instruction Error Reserved Instruction Breakpoint System Call Coprocessor Unusable Instruction Parity Error Integer Overflow Interrupt Stage Traps Data Translation Address Exception Modified Data Error Data Parity Error Non-maskable Interrupt Soft Reset) Reset
Table Pipeline Exceptions
Interlock IICM MDSt FCBsy
Description Instruction Miss Instruction Cache Miss Coprocessor Possible Exception Data Cache Miss Load Interlock Multiply/Divide Start Coprocessor Busy
Table Pipeline Interlocks
Exception Conditions When exception condition occurs, relevant instruction those that follow pipeline cancelled. Accordingly, stall conditions later exception conditions that have referenced this instruction inhibited; there benefit servicing stalls cancelled instruction.
Pipeline
Chapter
When exceptional condition detected instruction, RV4700 will kill following instructions. When this instruction reaches stage, exception flag causes write various registers with exception state, change current appropriate exception vector address clear exception bits earlier pipeline stages. This implementation allows preceding instructions complete execution prevents subsequent instructions from completing. Thus value sufficient restart execution. also ensures that exceptions taken order execution; instruction taking exception itself killed instruction further down pipeline that takes exception later cycle. Figure shows exception detection procedure (e.g., reserved instruction exception).
Kill
Exception Vector
Exception Vector Address
Figure Exception Detection
Stall Conditions Stalls used stop pipeline conditions detected after pipe-stage. When stall occurs, processor will resolve condition then pipeline will continue.
Pipeline
Chapter
Figure shows data cache miss stall.
Detect Cache Miss Start moving dirty cache line data write buffer first doubleword into cache restart pipeline Load remainder cache line into cache
Figure Data Cache Miss
data cache miss detected pipe stage. cache line replaced dirty data moved internal write buffer next cycle. first doubleword data returned cache pipeline will then restart. remainder cache line returned subsequent cycles. data written back will returned memory some time after entire cache line returned. Slip Conditions During pipe-stages, internal logic will determine whether possible start current instruction this cycle. source operands available (either from register file internal bypass logic) hardware resources necessary complete instruction will available necessary time(s), then instruction "issues"; otherwise, instruction will "slip". Slipped instructions retried subsequent cycles until they issue. backend pipeline (stages will advance normally during slips attempt resolve conflict. "NOPS" will inserted into bubble pipeline. Instructions killed branch likely instructions, ERET exceptions will cause slips.
Pipeline
Chapter
Figure shows instruction cache miss.
CYCLE Issue Issue Previous Instructions
Slip
Slip
Slip
Slip Issue Issue Issue
*NOP *NOP *NOP *NOP
Detect Cache Miss entire cache line into cache Continue pipeline *NOP Inserted instructions
Figure Instruction cache miss
Instruction cache misses detected shown Figure pipeline slips stage. There never writeback required instruction cache miss since dirty data never exist cache. Writes allowed cache. Note that early restart employed instruction cache misses, requested cache line will loaded into cache entirety and, after that, pipeline will restart.
RV4700 Write Buffer
RV4700 contains write buffer improve performance writes external memory. Writes external memory, whether cache miss writebacks stores uncached write-through addresses, this on-chip write buffer. write buffer holds four 64-bit address data pairs. cache miss write-back, entire buffer used write-back data allows processor proceed parallel with memory update. uncached write-through stores, write buffer uncouples from write memory allowing increased performance over R4000 family processors. write buffer full, additional stores will stall until there room them write buffer.
Pipeline
Chapter
Memory Management
Chapter
RV4700 processor provides full-featured memory management unit (MMU) which uses on-chip Translation Lookaside Buffer (TLB) translate virtual addresses into physical addresses. This chapter describes processor virtual physical address spaces, virtual-to-physical address translation, operation making these translations, those System Control Coprocessor (CP0) registers that provide software interface TLB.
Translation Lookaside Buffer (TLB)
Mapped virtual addresses translated into physical addresses using on-chip TLB.1 fully associative memory that holds entries, which provide mapping odd/even page pairs pages). When address mapping indicated, each entry checked simultaneously match with virtual address that extended with ASID stored EntryHi register. address mapped page ranges size from 4Kbytes 16Mbytes, multiples 4-that 16K, 64K, 256K, 16M. Hits Misses there virtual address match, hit, TLB, physical page number extracted from concatenated with offset form physical address (see Figure 4.1). match occurs (TLB miss), exception taken software refills from page table resident memory. Software write over selected entry hardware mechanism write into random entry. Multiple Matches RV4700 does provide detection shutdown mechanism multiple matches TLB. There damage possible from this condition. result undefined this condition. Software expected never allow this occur.
Address Spaces
This section describes virtual physical address spaces manner which virtual addresses converted "translated" into physical addresses TLB. Virtual Address Space processor virtual address either 64-bits wide, depending mode operation (user, supervisor kernel) setting corresponding extended address Status register (UX, KX). extended address addresses 32-bits wide. extended address addresses 64-bits wide. Both 32-bit 64-bit address wrap same way. example, 64-bit mode 0xffffffffffffffff will wrap 0x0000000000000000. While R4400 slipped shift >32-bit other shift variables, RV4700 does not.
There virtual-to-physical address translations that occur outside TLB. example, addresses kseg0 kseg1 spaces unmapped translations. these spaces physical address 0x0000 0000 VA[28:0]
Memory Management
Chapter
Figure shows translation virtual address into physical address. Virtual address
ASID
Virtual address (VA) represented virtual page number (VPN) compared with TLB.
Offset
there match, page frame number (PFN) representing upper bits physical address (PA) output from TLB.
ASID
Entry
Offset, which does pass through TLB, then concatenated PFN.
Offset Physical address
Figure Overview Virtual-to-Physical Address Translation
shown Figure Figure 4.3, virtual address extended with 8-bit address space identifier (ASID), which reduces frequency flushing when switching contexts. This 8-bit ASID EntryHi register, described later this chapter. Global EntryLo0 EntryLo1 registers, described later this chapter. Physical Address Space Using 36-bit address, processor physical address space encompasses 64Gigabytes. section following describes translation virtual address physical address. Virtual-to-Physical Address Translation Converting virtual address physical address begins comparing virtual address from processor with virtual address TLB; there match when virtual page number (VPN) address same field entry, either: Global entry set, ASID field virtual address same ASID field entry. This match referred hit. there match, Miss exception taken processor software allowed refill from page table virtual/physical addresses memory. there virtual address match TLB, physical address output from concatenated with Offset, which represents address within page frame space. Offset does pass through TLB. Virtual-to-physical translation described greater detail throughout remainder this chapter; Figure 4.19 page flow diagram process. next sections describe 32-bit 64-bit address translations.
Memory Management
Chapter
32-bit Virtual Address Translation Figure shows virtual-to-physical-address translation 32-bit virtual address. portion Figure shows virtual address with 12-bit, 4Kbyte, page size, labelled Offset. remaining bits address represent VPN, index 1M-entry page table. bottom portion Figure shows virtual address with 24bit, 16Mbyte, page size, labelled Offset. remaining bits address represent VPN, index 256-entry page table.
Virtual Address with (220 4-Kbyte pages
bits pages
ASID
Virtual-to-physical translation
Offset
Offset passed unchanged physical memory
Bits virtual address select user, supervisor, kernel address spaces.
36-bit Physical Address
Virtual-to-physical translation
Offset
Offset passed unchanged physical memory
ASID
bits pages
Offset
Virtual Address with (28)16-Mbyte pages Figure 32-bit Virtual Address Translation
64-bit Virtual Address Translation Figure page shows virtual-to-physical-address translation 64-bit virtual address. This figure illustrates extremes range possible page sizes: 4Kbyte page bits) 16Mbyte page bits). portion Figure shows virtual address with 12-bit, 4Kbyte, page size, labelled Offset. remaining bits address represent VPN, index 256M-entry page table. bottom portion Figure shows virtual address with 24bit, 16Mbyte, page size, labelled Offset. remaining bits address represent VPN, index 64K-entry page table.
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Virtual Address with 256M (228) 4-Kbyte pages
bits 256M pages
ASID
Virtual-to-physical translation
Offset
Offset passed unchanged physical memory
36-bit Physical Address
Bits virtual address select user, supervisor, kernel address spaces.
Virtual-to-physical translation
Offset
Offset passed unchanged physical memory
Virtual Address with (216)16-Mbyte pages
ASID
bits pages
Offset
Figure 64-bit Virtual Address Translation
Operating Modes processor three operating modes that function both 64-bit operations: User mode Supervisor mode Kernel mode These modes described next three sections. User Mode Operations User mode, single, uniform virtual address space-labelled User segment-is available; size Gbytes (231 bytes) Status.UX (useg) Tbyte (240 bytes) Status.UX (xuseg)
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Figure shows User mode virtual address space.
32-bit*
FFFF FFFF FFFF FFFF FFFF FFFF
64-bit
Address Error
8000 0000 0000 0100 0000
Address Error
Mapped
0000 0000
useg
0000 0000 0000 0000
Mapped
xuseg
Note: *For 32-bit virtual addresses, sign-extended through bits 63:32. Failure (i.e., results Address Error exception.
Figure
User Mode Virtual Address Space
User segment starts address current active user process resides either useg (32-bit virtual addressing) xuseg 64bit virtual addressing). identically maps references useg/ xuseg from modes, controls cache accessibility. processor operates User mode when Status register contains following bit-values: bits conjunction with these bits, Status register selects between 64-bit User virtual addressing follows: when 32-bit useg space selected when 64-bit xuseg space selected Table lists characteristics user mode segments, useg xuseg.
Address Values Status Register Values 32-bit A(31) 64-bit A(63:40) useg 0x0000 0000 through 0x7FFF FFFF Gbyte (231 bytes) Segment Name Address Range Segment Size
xuseg
0x0000 0000 0000 0000 Tbyte (240 bytes) through 0x0000 00FF FFFF FFFF
Table 32-bit 64-bit User Mode Segments
32-bit User Mode (useg) User mode, when Status.UX User mode virtual addressing compatible with 32-bit addressing model shown Figure 4.4, 2Gbyte user address space available, labelled useg.
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valid User mode virtual addresses have their most-significant cleared attempt reference address with most-significant while User mode causes Address Error exception. 32-bit User mode virtual addressing, refill exception vector used misses. system maps references useg through TLB, settings within entry page determine cacheability reference. 64-bit User Mode (xuseg) User mode, when Status.UX User mode virtual addressing extended 64-bit model shown Figure 4.4, 1-Tbyte user address space available, labelled xuseg. valid User mode virtual addresses have bits 63:40 equal attempt reference address with bits 63:40 equal causes Address Error exception. extended addressing refill exception vector used misses. Supervisor Mode Operations Supervisor mode designed layered operating systems which true kernel runs RV4700 Kernel mode, rest operating system runs Supervisor mode. processor operates Supervisor mode when Status register contains following bit-values: conjunction with these bits, Status register selects between 64-bit Supervisor mode virtual addressing: when 32-bit supervisor space virtual addressing selected when 64-bit supervisor space virtual addressing selected Figure shows Supervisor mode address mapping. Table 4.2, which follows figure, lists characteristics supervisor mode segments; descriptions address spaces follow. 32-bit*
FFFF FFFF 0000 0000 0000 8000 0000
64-bit
FFFF FFFF FFFF FFFF FFFF FFFF 0000 sseg FFFF FFFF 0000 4000 0100 0000 0000
Address error Mapped Address error Address error
Address error Mapped Address error Mapped
csseg
xsseg
4000 0000 0000 0000
Mapped
0000 0000
suseg
0000 0100 0000 0000
Address error Mapped
xsuseg
0000 0000 0000 0000
Note:
32-bit virtual addressing, sign-extended through bits 63:32. Failure results Address Error exception. Figure Supervisor Mode Virtual Address Space
Memory Management
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Status Register Values Address Values 32-bit A(31) 32-bit A(31:29) 1102 64-bit A(63:62) 64-bit A(63:62) 64-bit A(63:62) Segment Name suseg Address Range 0x0000 0000 through 0x7FFF FFFF 0xC000 0000 through 0xDFFF FFFF 0x0000 0000 0000 0000 through 0x0000 00FF FFFF FFFF 0x4000 0000 0000 0000 through 0x4000 00FF FFFF FFFF Segment Size Gbytes (231 bytes) Mbytes (229 bytes) Tbyte (240 bytes) Tbyte (240 bytes)
sseg
xsuseg
xsseg
csseg
0xFFFF FFFF C000 0000 Mbytes (229 bytes) through 0xFFFF FFFF DFFF FFFF
Table 32-bit 64-bit Supervisor Mode Segments
32-bit Supervisor Mode, User Space (suseg) Supervisor mode, when Status.SX most-significant 32-bit virtual address suseg virtual address space selected; covers full bytes (2Gbytes) current user address space. virtual address extended with contents 8-bit ASID field form unique virtual address. This mapped space starts virtual address 0x0000 0000 runs through 0x7FFF FFFF. 32-bit Supervisor Mode, Supervisor Space (sseg) Supervisor mode, when Status.SX three most-significant bits 32-bit virtual address 1102, sseg virtual address space selected; covers 229-bytes (512Mbytes) current supervisor address space. virtual address extended with contents 8bit ASID field form unique virtual address. This mapped space begins virtual address 0xC000 0000 runs through 0xDFFF FFFF. 64-bit Supervisor Mode, User Space (xsuseg) Supervisor mode, when Status.SX bits 63:62 virtual address 002, xsuseg virtual address space selected; covers full bytes (1Tbyte) current user address space. virtual address extended with contents 8-bit ASID field form unique virtual address. This mapped space starts virtual address 0x0000 0000 0000 0000 runs through 0x0000 00FF FFFF FFFF. 64-bit Supervisor Mode, Current Supervisor Space (xsseg) Supervisor mode, when Status.SX bits 63:62 virtual address 012, xsseg current supervisor virtual address space selected. virtual address extended with contents 8-bit ASID field form unique virtual address. This mapped space begins virtual address 0x4000 0000 0000 0000 runs through 0x4000 00FF FFFF FFFF.
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64-bit Supervisor Mode, Separate Supervisor Space (csseg) Supervisor mode, when Status.SX bits 63:62 virtual address 112, csseg separate supervisor virtual address space selected. Addressing csseg compatible with addressing sseg 32-bit mode. virtual address extended with contents 8bit ASID field form unique virtual address. This mapped space begins virtual address 0xFFFF FFFF C000 0000 runs through 0xFFFF FFFF DFFF FFFF. Kernel Mode Operations processor operates Kernel mode when Status register contains following values: conjunction with these bits, Status register selects between 64-bit Kernel mode addressing: when 32-bit kernel space virtual addressing selected when 64-bit kernel space virtual addressing selected processor enters Kernel mode whenever exception detected remains Kernel mode until Exception Return (ERET) instruction executed. ERET instruction restores processor mode existing prior exception. Kernel mode virtual address space divided into regions differentiated high-order bits virtual address, shown Figure 4.6.
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32-bit*
FFFF FFFF FFFF FFFF FFFF FFFF
E000 0000
Mapped Mapped
kseg3
FFFF FFFF E000 0000 FFFF FFFF C000 0000
64-bit Mapped Mapped
Unmapped Uncached Unmapped Cached
ckseg3 cksseg ckseg1 ckseg0
ksseg
FFFF FFFF A000 0000
C000 0000
A000 0000
Unmapped Uncached Unmapped Cached
kseg1 FFFF FFFF 8000 0000
C000 00FF 8000 0000
Address error Mapped
xkseg xkphys
kseg0
C000 0000 0000 0000
8000 0000
Unmapped
8000 0000 0000 0000 4000 0100 0000 0000
Address error Mapped
xksseg
kuseg
Mapped
4000 0000 0000 0000 0000 0100 0000 0000
Address error Mapped
xkuseg
0000 0000
0000 0000 0000 0000
Note: 32-bit virtual addressing, sign-extended through bits 63:32. Failure results Address Error exception. Figure Kernel Mode Address Space
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Table lists characteristics 32-bit kernel mode segments, Table lists characteristics 64-bit kernel mode segments
Address Values Status Register These Values A(31) A(31:29) 1012 A(31:29) 1102 ksseg kseg1 kuseg 0x0000 0000 through 0x7FFF FFFF 0x8000 0000 through 0x9FFF FFFF 0xA000 0000 through 0xBFFF FFFF 0xC000 0000 through 0xDFFF FFFF 0xE000 0000 through 0xFFFF FFFF Gbytes (231 bytes) Mbytes (229 bytes) Mbytes (229 bytes) Mbytes (229 bytes) Mbytes (229 bytes) Segment Address Range Name Segment Size
A(31:29) 1002
kseg0
A(31:29) 1112
kseg3
Table 32-bit Kernel Mode Segments
32-bit Kernel Mode, User Space (kuseg) Kernel mode, when Status.KX most-significant virtual address, A31, cleared, 32-bit kuseg virtual address space selected; covers full bytes Gbytes) current user address space. virtual address extended with contents 8-bit ASID field form unique virtual address. 32-bit Kernel Mode, Kernel Space (kseg0) Kernel mode, when Status.KX most-significant three bits virtual address 1002, 32-bit kseg0 virtual address space selected; current 229-byte (512-Mbyte) kernel physical space. References kseg0 mapped through TLB; physical address selected defined subtracting 0x8000 0000 from virtual address (physical address 0x0000 0000 VA[28:0]). field Config register, described this chapter, controls cacheability coherency. 32-bit Kernel Mode, Kernel Space (kseg1) Kernel mode, when Status.KX most-significant three bits 32-bit virtual address 1012, 32-bit kseg1 virtual address space selected; current 229-byte (512Mbyte) kernel physical space. References kseg1 mapped through TLB; physical address selected defined subtracting 0xA000 0000 from virtual address (physical address 0x0000 0000 VA[28:0]). Caches disabled accesses these addresses, physical memory memory-mapped device registers) accessed directly. 32-bit Kernel Mode, Supervisor Space (ksseg) Kernel mode, when Status.KX most-significant three bits 32-bit virtual address 1102, ksseg virtual address space selected; current 229-byte (512Mbyte) supervisor virtual space. virtual address extended with contents 8-bit ASID field form unique virtual address.
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32-bit Kernel Mode, Kernel Space (kseg3) Kernel mode, when Status.KX most-significant three bits 32-bit virtual address 1112, kseg3 virtual address space selected; current 229-byte (512Mbyte) kernel virtual space. virtual address extended with contents 8-bit ASID field form unique virtual address.
Address Values Status Register These Values A(63:62) xkuseg 0x0000 0000 0000 0000 through 0x0000 00FF FFFF FFFF 0x4000 0000 0000 0000 through 0x4000 00FF FFFF FFFF Tbyte (240 bytes) Tbyte (240 bytes) Segment Name Address Range Segment Size
A(63:62)
xksseg
A(63:62)
xkphys
0x8000 0000 0000 0000 236-byte through spaces 0xBFFF FFFF FFFF FFFF 0xC000 0000 0000 0000 through 0xC000 00FF 7FFF FFFF 0xFFFF FFFF 8000 0000 through 0xFFFF FFFF 9FFF FFFF bytes
A(63:62)
xkseg
A(63:62) A(61:31) A(63:62) A(61:31) A(63:62) A(61:31) A(63:62) A(61:31)
ckseg0
Mbytes (229 bytes)
ckseg1
0xFFFF FFFF A000 0000 Mbytes through (229 bytes) 0xFFFF FFFF BFFF FFFF 0xFFFF FFFF C000 0000 Mbytes through (229 bytes) 0xFFFF FFFF DFFF FFFF 0xFFFF FFFF E000 0000 through 0xFFFF FFFF FFFF FFFF Mbytes (229 bytes)
cksseg
ckseg3
Table 64-bit Kernel Mode Segments
64-bit Kernel Mode, User Space (xkuseg) Kernel mode, when Status.KX bits 63:62 64-bit virtual address 002, xkuseg virtual address space selected; covers current user address space. virtual address extended with contents 8-bit ASID field form unique virtual address. special feature handler, Status register set, user address region becomes 231-byte unmapped, uncached space. This allows exception code operate uncached using base register. 64-bit Kernel Mode, Current Supervisor Space (xksseg) Kernel mode, when Status.KX bits 63:62 64-bit virtual address 012, xksseg virtual address space selected; current supervisor virtual space. virtual address extended with contents 8-bit ASID field form unique virtual address.
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64-bit Kernel Mode, Physical Spaces (xkphys) Kernel mode, when Status.KX bits 63:62 64-bit virtual address 102, xkphys virtual address space selected; eight 236-byte kernel physical spaces. Accesses with address bits 58:36 equal cause address error. References this space mapped; physical address selected taken from bits 35:0 virtual address. Bits 61:59 virtual address specify cacheability coherency attributes, shown Table 4.5.
Value (61:59 Cacheability Coherency Attributes Starting Address
Cacheable, noncoherent, write-through, write allocate Cacheable, noncoherent, write-through, write allocate Uncached Cacheable, noncoherent Reserved
0x8000 0000 0000 0000 0x8800 0000 0000 0000 0x9000 0000 0000 0000 0x9800 0000 0000 0000 0xA000 0000 0000 0000
Table Cacheability Coherency Attributes
64-bit Kernel Mode, Kernel Space (xkseg) Kernel mode, when Status.KX bits 63:62 64-bit virtual address 112, address space selected following: kernel virtual space, xkseg, current supervisor virtual space; virtual address extended with contents 8-bit ASID field form unique virtual address four 32-bit kernel compatibility spaces, described next section. 64-bit Kernel Mode, Compatibility Spaces (ckseg1:0, cksseg, ckseg3) Kernel mode, when Status.KX bits 63:62 64-bit virtual address 112, bits 61:31 virtual address equal "-1", lower bytes address, shown Figure 4.6, select following 512-Mbyte compatibility spaces. ckseg0. This 64-bit virtual address space unmapped region, compatible with 32-bit address model kseg0. field Config register, described this chapter, controls cacheability coherency. ckseg1. This 64-bit virtual address space unmapped uncached region, compatible with 32-bit address model kseg1. cksseg. This 64-bit virtual address space current supervisor virtual space, compatible with 32-bit address model ksseg. ckseg3. This 64-bit virtual address space kernel virtual space, compatible with 32-bit address model kseg3.
System Control Coprocessor
System Control Coprocessor (CP0) implemented integral part CPU, supports memory management, address translation, exception handling, other privileged operations. contains registers shown Figure plus 48-entry TLB. sections that follow describe processor uses each memory management-related registers.
Memory Management
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Each register unique number that identifies this number referred register number. instance, Page Mask register register number
EntryHi EntryHi
EntryLo0 EntryLo0 EntryLo1
Index
Context
Index
Random Random
BadVAddr
Count
Compare
Status
Cause
Page Mask Page Mask
XContext
Wired Wired
CacheErr
PRId
("Safe" entries) (See Random Register, contents Wired)
ErrorEPC
Config
TagHi
LLAddr
TagLo
Used with memory management system.
Used with exception processing. Chapter details.
Note: *Register number Figure Registers
Format Entry Figure shows entry formats both 64-bit virtual addressing. Each field entry corresponding field EntryHi, EntryLo0, EntryLo1, PageMask registers, shown Figure Figure 4.10; example Mask field entry also held PageMask register.
Memory Management
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64-bit Virtual Addressing
256-bit entry 64-bit virtual addressing
MASK
VPN2
ASID
Figure Format Entry
format EntryHi, EntryLo0, EntryLo1, PageMask registers nearly same entry. exception Global field bit), which used TLB, reserved EntryHi register. Figure Figure 4.10 describe entry fields that shown Figure 4.8.
PageMask Register MASK
Mask Page comparison mask. Reserved. Must written zeroes, returns zeroes when read.
EntryHi Register
64-bit
FILL
VPN2
ASID
VPN2 Virtual page number divided (maps pages). ASID Address space field. 8-bit field that lets multiple processes share TLB; each process distinct mapping otherwise identical virtual page numbers. Region. user, supervisor, kernel) used match vAddr63.62 Fill Reserved. Returns zero when read, ignored writes. Reserved. Must written zeroes, returns zeroes when read.
Figure Fields PageMask EntryHi Registers
Memory Management
Chapter
EntryLo0 EntryLo1 Registers
64-bit 64-bit
Page frame number; upper bits physical address. Specifies page coherency attribute; Table 4.6. Dirty. this set, page marked dirty and, therefore, writable. This actually write-protect that software prevent alteration data. Valid. this set, indicates that entry valid; otherwise, TLBL TLBS miss occurs. Global. this both Lo1, then processor ignores ASID during lookup. Reserved. Must written zeroes, returns zeroes when read.
Figure 4.10 Fields EntryLo0 EntryLo1 Registers
page coherency attribute bits specify whether references page should cached; cached, algorithm selects between several coherency attributes. Table shows coherency attributes selected bits.
C(5:3) Value Page Coherency Attribute Cacheable, noncoherent, write-through, write allocate Cacheable, noncoherent, write-through, write allocate Uncached Cacheable, noncoherent, write-back Reserved
Table Page Coherency Values
Registers following sections describe registers (shown Figure page that assigned specifically software interface with memory management (each register followed register number parentheses). Index register (CP0 register number Random register EntryLo0 EntryLo1 registers PageMask register Wired register EntryHi register (10) PRId register (15) Config register (16) LLAddr register (17) TagLo (28) TagHi (29) registers
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Index Register Index register 32-bit, read/write register containing bits index entry TLB. high-order register shows success failure Probe (TLBP) instruction. Index register also specifies entry affected Read (TLBR) Write Index (TLBWI) instructions. Figure 4.11 shows format Index register; Table 4.7, which follows figure, describes Index register fields. Index Register
Figure 4.11 Index Register
Index
Field Index
Description Probe failure. when previous TLBProbe (TLBP) instruction unsuccessful. Index entry affected TLBRead TLBWrite instructions Reserved. Must written zeroes, returns zeroes when read.
Table Index Register Field Descriptions
Random Register Random register read-only register which bits index entry TLB. This register decrements each instruction executes, values range between upper lower bound, follows: lower bound number entries reserved exclusive operating system (the contents Wired register). upper bound total number entries. Thus upper bound (The entries number from 47). RV4700 implements this register differently from R4000: R4000 counts both valid invalid instructions, while RV4700 counts only valid instructions. Random register specifies entry that affected Write Random instruction. register does need read this purpose; however, register readable verify proper operation processor. simplify testing, Random register value upper bound upon system reset. This register also upper bound when Wired register written. Figure 4.12 shows format Random register; Table page describes Random register fields. Random Register
Figure 4.12 Random Register
Random
Memory Management
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Field Random random index
Description
Reserved. Must written zeroes, returns zeroes when read.
Table Random Register Field Descriptions
EntryLo0 (2), EntryLo1 Registers EntryLo register consists registers that have identical formats: EntryLo0 used even virtual pages. EntryLo1 used virtual pages. EntryLo0 EntryLo1 registers read/write registers. They hold physical page frame number (PFN) entry even pages, respectively, when performing read write operations. Figure 4.10 page shows format these registers. PageMask Register PageMask register read/write register used reading from writing TLB; holds comparison mask that sets variable page size each entry, shown Table 4.9. read write operations this register either source destination; when virtual addresses presented translation into physical address, corresponding bits identify which virtual address bits among bits 24:13 used comparison. When Mask field values shown Table 4.9, operation undefined. Page Size Kbytes Kbytes Kbytes Kbytes Mbyte Mbytes Mbytes
Table Mask Field Values Page Sizes
Memory Management
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Wired Register Wired register read/write register that specifies boundary between wired random entries TLB, shown Figure 4.13. Wired entries nonreplaceable entries, which cannot overwritten write random operation. Random entries overwritten.
Range Random entries Wired Register Range Wired entries
Figure 4.13 Wired Register Boundary
Wired register upon system reset. Writing this register also sets Random register value upper bound (see Random register, above). Figure 4.14 shows format Wired register; Table 4.10, which follows figure, describes register fields. Wired Register
Figure 4.14 Wired Register
Wired
Field Wired
Description Wired boundary (the number wired entries) Reserved. Must written zeroes, returns zeroes when read.
Table 4.10 Wired Register Field Descriptions
EntryHi Register (CP0 Register EntryHi register holds high-order bits entry read write operations. EntryHi register accessed Probe, Write Random, Write Indexed, Read Indexed instructions. Figure shows format this register. When either refill, invalid, modified exception occurs, EntryHi register loaded with virtual page number (VPN2) ASID virtual address that have matching entry. (See Chapter more information about these exceptions.)
Memory Management
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Processor Revision Identifier (PRId) Register (15) 32-bit, read-only Processor Revision Identifier (PRId) register contains information identifying implementation revision level CP0. Figure 4.15 shows format PRId register; Table 4.11 describes PRId register fields. PRId Register
Figure 4.15 Processor Revision Identifier Register Format
Field
Description Implementation number Revision number Reserved. Must written zeroes, returns zeroes when read.
Table 4.11 PRId Register Fields
RV4700: 0x21
low-order byte (bits 7:0) PRId register interpreted revision number, high-order byte (bits 15:8) interpreted implementation number. implementation number RV4700 processor 0x20. content high-order halfword (bits 31:16) register reserved. revision number stored value form y.x, where major revision number bits minor revision number bits 3:0. revision number distinguish some chip revisions, however there guarantee that changes chip will necessarily reflected PRId register, that changes revision number necessarily reflect real chip changes. this reason, these values listed software should rely revision number PRId register characterize chip. Certain attributes, such cache size, independent implementation number. Config Register (16) Config register specifies various configuration options selected RV4700 processors; Table 4.12 lists these options. Some configuration options, defined Config bits 31:3, hardware during reset included Config register readonly status bits software access. field only read/ write field indicated Config register bits 2:0) controlled software; reset these fields undefined. Figure 4.16 shows format Config register; Table 4.12, which follows figure, describes Config register fields. Config Register
Figure 4.16 Config Register Format
Memory Management
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Field
Description System clock ratio: processor clock frequency divided processor clock frequency divided processor clock frequency divided processor clock frequency divided processor clock frequency divided processor clock frequency divided processor clock frequency divided Reserved Writeback data rate: DDDD DDxDDx DDxxDDxx DxDxDxDx DDxxxDDxxx DDxxxxDDxxxx DxxDxxDxxDxx DDxxxxxDDxxxxx DxxxDxxxDxxxDxxx BigEndianMem Little endian endian Primary I-cache Size (I-cache size 212+IC bytes). RV4700 processor, this Kbytes 010) Primary D-cache Size (D-cache size 212+DC bytes). RV4700 processor, this Kbytes 010) Primary I-cache line size bytes Words) Primary D-cache line size bytes Words) kseg0 coherency algorithm (see EntryLo0 EntryLo1 registers) Reserved. Returns indicated values when read.
Table 4.12 Config Register Fields
Doubleword every cycle Doublewords every cycles Doublewords every cycles Doublewords every cycles Doublewords every cycles Doublewords every cycles Doublewords every cycles Doublewords every cycles Doublewords every cycles Reserved
Others
Load Linked Address (LLAddr) Register (17) read/write Load Linked Address (LLAddr) register contains physical address read most recent Load Linked instruction. This register diagnostic purposes only, serves function during normal operation. Figure 4.17 shows format LLAddr register; PAddr represents bits physical address, PA(35:4).
Memory Management
Chapter
LLAddr Register
PAddr(35:4)
Figure 4.17 LLAddr Register Format
Cache Registers [TagLo (28) TagHi (29)] TagLo TagHi registers 32-bit read/write registers that hold primary cache parity during cache initialization, cache diagnostics, cache error processing. registers written CACHE MTC0 instructions. field these registers ignored Index Store operations. Parity computed store operation. Windows Operating System uses TagLo register save/ restore registers refill exception handler. Thus, bits must present, even though they have primary purpose TagLo. Figure 4.18 shows format these registers primary cache operations. Table 4.13 lists field definitions TagLo TagHi registers.
TagLo
PTagLo
PState
RWNT
TagHi
Figure 4.18 TagLo TagHi Register (P-cache) Formats
Field PTagLo PState RWNT
Description Specifies physical address bits 35:12 Specifies primary cache state Specifies primary even parity FIFO used implement FIFO refill cache Read/Write bits required Windows Reserved. Must written zeroes; returns zeroes when read
Table 4.13 Cache Register Fields
Memory Management
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Virtual-to-Physical Address Translation Process During virtual-to-physical address translation, compares 8-bit ASID Global bit, set) virtual address ASID entry there match. following comparison also made: 64-bit virtual addresses, highest 15-to-27 bits (depending upon page size) virtual address compared contents virtual page number. entry matches, physical address access control bits retrieved from matching entry. While entry must valid translation take place, involved determination matching entry. Figure 4.19 illustrates address translation process.
Virtual Address (Input) ASID Note: valid address space section this chapter that describes Operating Modes.
Address Error Exception
User Valid Address? Mode?
Mode?
Valid Address?
Address Error Exception
Unmapped Access
Valid Address?
Match? Global Write? Exception 010? Noncacheable Invalid Exception Refill XTLB Refill Dirty Valid ASID Match? 32-bit address?
Access Access Main Cache Memory Physical Address (Output)
Figure 4.19 Address Translation
Memory Management
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Misses there entry that matches virtual address, miss exception occurs. access control bits indicate that access valid, modification invalid exception occurs. bits equal 0102, physical address that retrieved accesses main memory, bypassing cache. Instructions Table 4.14 lists instructions that provides working with TLB. Appendix detailed description these instructions. Code TLBP TLBR TLBWI TLBWR Description Instruction Translation Lookaside Buffer Probe Translation Lookaside Buffer Read Translation Lookaside Buffer Write Index Translation Lookaside Buffer Write Random
Table 4.14 Instructions
Memory Management
Chapter
Exception Processing
Chapter
This chapter describes exception process includes exception register formats descriptions. chapter concludes with description each exception's cause manner which processes services these exceptions. detailed information Floating-Point Unit exceptions, Chapter
Exception Processing Works
processor receives exceptions from number sources, including translation lookaside buffer (TLB) misses, arithmetic overflows, interrupts, system calls. When detects these exceptions, normal sequence instruction execution suspended processor enters Kernel mode (see Chapter description system operating modes). processor then disables interrupts forces execution software exception processor (called handler) located fixed address. handler save context processor, including contents program counter, current operating mode (User Supervisor), status interrupts (enabled disabled). This context would saved restored when exception been serviced. When exception occurs, loads Exception Program Counter (EPC) register with location where execution restart after exception been serviced. restart location register address instruction that caused exception instruction executing branch delay slot, address branch instruction immediately preceding delay slot. registers described later chapter assist this exception processing retaining address, cause status information. description exception handling process, description individual exception contained this chapter, flowcharts this chapter.
Exception Processing Registers
This section describes registers that used exception processing. Table page lists these registers, along with their number-each register unique identification number that referred register number. instance, register register number remaining registers used memory management, described Chapter Software examines registers during exception processing determine cause exception state time exception occurred.
Exception Processing
Chapter
registers Table used exception processing, described sections that follow.
Register Name Context BadVAddr (Bad Virtual Address) Count Compare register Status Cause (Exception Program Counter) XContext CacheErr (Cache Error Status) ErrorEPC (Error Exception Program Counter)
Table Exception Processing Registers
Reg.
Context Register Context register read/write register containing pointer entry page table entry (PTE) array; this array operating system data structure that stores virtual-to-physical address translations. When there miss, loads with missing translation from array. Normally, operating system uses Context register address current page which resides kernel-mapped segment, kseg3. Context register duplicates some information provided BadVAddr register, information arranged form that more useful software exception handler. Figure shows format Context register; Table 5.2, which follows figure, describes Context register fields. Context Register
PTEBase
BadVPN2
Figure Context Register Format
Field BadVPN2
Description This field written hardware miss. contains virtual page number (VPN) most recent virtual address that have valid translation. This field read/write field operating system. normally written with value that allows operating system Context register pointer into current array memory.
Table Context Register Fields
PTEBase
Exception Processing
Chapter
19-bit BadVPN2 field contains bits 31:13 virtual address that caused miss; excluded because single entry maps even-odd page pair. 4-Kbyte page size, this format directly address pair-table 8-byte PTEs. other page sizes, shifting masking this value produces appropriate address. Virtual Address Register (BadVAddr) Virtual Address register (BadVAddr) read-only register that displays most recent virtual address that caused following exceptions: Address Error (e.g., unaligned access), Invalid, Modified, Refill, Virtual Coherency Data Access, Virtual Coherency Instruction Fetch. processor does write BadVAddr register when Status register Figure shows format BadVAddr register.
BadVAddr Register
Virtual Address
Figure BadVAddr Register Format
Note: BadVAddr register does save information errors, since errors addressing errors. Count Register Count register acts timer, incrementing constant rate-half maximum instruction issue rate-whether instruction executed, retired, forward progress made through pipeline. This register read written. written diagnostic purposes system initialization; example, synchronize processors. Figure shows format Count register. Count Register
Count
Figure Count Register Format
Compare Register (11) Compare register acts timer (see also Count register); maintains stable value that does change own. When value Count register equals value Compare register, interrupt IP(7) Cause register set. This causes interrupt soon interrupt enabled. Writing value Compare register, side effect, clears timer interrupt. diagnostic purposes, Compare register read/write register. normal however, Compare register write-only. Figure shows format Compare register.
Exception Processing
Chapter
Compare Register
Compare
Figure Compare Register Format
Status Register (12) Status register (SR) read/write register that contains operating mode, interrupt enabling, diagnostic states processor. following list describes more important Status register fields; Figure show format entire register, inclu

Version December 1997 2975 Stender Way, Santa Clara, California 9

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