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Version August 1998
2975 Stender Way, Santa Clara, California 95054 Telephone: (800) 345-7015 TWX: 910-338-2070 FAX: (408) 492-8674 Printed U.S.A. ©1996 Integrated Device Technology, Inc.
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This hardware user's manual presents hardware software overviews provides descriptions operation IDT79RC4640TM/IDT79RC4650RISC processor, member Orion processor family. Note: Throughout this manual, references IDT79RC4650 RC4650 also refer IDT79RC4640 RC4640. RC4640 device supports only 32-bit width; otherwise, RC4640 RC4650 identical.
Chapter "Overview," contains device, pipeline, register instruction overview RC4650 microprocessor includes detailed feature-by-feature comparison between RC4600/ RC4700 RC4650. Chapter "CPU Instruction Overview," contains overview instruction formats computational instructions. Individual instruction details found "IDT MIPS Microprocessor Family Software Reference Manual." Chapter "The Pipeline," describes basic operation RC4650's 5-stage pipeline, including delay instruction (instructions that follow branch load instruction pipeline) descriptions, interlock exception interruptions pipeline flow, RC4650 implementation uncached store buffer. Chapter "Memory Management," describes simple base-bounds mechanism used RC4650 virtual-to-physical address translation, operating modes, registers. Chapter "CPU Exception Processing," describes exception processing includes discussion format each exception register. Also provided description each exception's cause, together with methods which processes services these exceptions. Chapter "The Floating-Point Unit," describes RC4650 floating-point unit (FPU) features, including programming model, instruction sets formats, pipeline. Chapter "Floating-Point Exceptions," describes floating point unit (FPU) floating-point exceptions, including exception types, exception trap processing, exception flags, saving restoring state when handling exception, trap handlers IEEE Standard exceptions. Chapter "Processor Signal Descriptions," defines describes signals used conjunction with, RC4650 processor. These signals include System interface, Clock/Control interface, Interrupt interface, Initialization interface. processor signal summary table also provided. Chapter "The Initialization Interface," describes RC4650 Initialization Interface, including reset signal descriptions types, boot-mode initialization sequence, signals timing dependencies. Chapter "The Clock Interface," describes clock signals (clocks) used RC4650 processor, well information basic system clocks system timing parameters. Chapter "Cache Organization, Operation Coherency," describes on-chip cache memory, place RC4650 memory organization, individual operations primary cache. Chapter "System Interface Overview," explains system interface process from standpoint both processor external agent. Chapter "The Read Interface," discusses specifics read interface read operations. Request response timing diagrams also included. Chapter "The Write Interface," discusses Write protocol associated operations. Timing diagrams included.
Chapter "The External Request Interface," explains external read, write, null request protocols associated operations. section system interface commands data identifiers included. Chapter "RC4650 Processor Interrupts," describes hardware interrupts single nonmaskable interrupt. Chapter "RC4650 Error Checking," discusses Error Checking mechanism used RC4650 processor. Error checking correcting summary tables, both internal external transactions, included. Appendix "Cache Operations Timing," lists cycle operation counts caveats RC4650 cache operations timing. Appendix "Standby Mode Operation," describes Standby Mode operation. Appendix "Coprocessor Hazards," lists RC4650 Coprocessor hazards, which result from certain instruction event combinations. Appendix "Integer Multiply Scheduling," describes RC4650's enhanced integer multiply performance.
Details about RC4640 RC4650 electrical interface found product's data sheet. Data sheets also include packaging pin-out information. information about development tools, complementary support chips, this product various applications, refer IDT's on-line library data sheets, applications notes, software reference manuals, Advantage Program Guides. Your local sales representative help identify these resources.
Overview .Chapter Introduction.1-1 Performance.1-1 Upward Compatibility .1-1 Features .1-2 Device Overview.1-2 Pipeline Overview.1-3 Register Overview.1-3 Instruction Overview.1-4 Instruction Tables .1-5 Data Formats Addressing 1-11 Coprocessors (CP0-CP2).1-14 System Control Coprocessor, .1-14 Floating-Point Co-Processor .1-16 Floating-Point Units.1-16 Virtual-to-Physical Address Mapping.1-17 Base Bounds Registers .1-18 Cache Memory.1-19 Instruction Cache .1-19 Data Cache .1-19 Write buffer .1-19 RC4650 Clocks.1-20 System Interface.1-20 Comparison RC4650 RC4600/RC4700.1-21 Instruction Overview .Chapter Introduction.2-1 Instruction Formats .2-1 Load Store Instructions.2-2 Scheduling Load Delay Slot.2-2 Defining Access Types.2-2 Computational Instructions.2-4 Operations With 32-bit Operands .2-4 Cycle Timing Multiply Divide Instructions.2-4 Jump Branch Instructions.2-5 Overview Jump Instructions.2-5 Overview Branch Instructions .2-5 Special Instructions .2-5 Exception Instructions .2-5 Coprocessor Instructions.2-5 Pipeline .Chapter Introduction.3-1 Pipeline Operation .3-1 Pipeline Stages.3-2
Instruction Fetch, phase one. Instruction Fetch, phase Register Fetch, phase Register Fetch, phase two. Execution, phase Execution, phase two. Data Fetch, phase Data Fetch, phase two. Write Back, phase one. Write Back, phase Branch Delay Load Delay. Interlock Exception Handling. Exception Conditions. Stall Conditions Slip Conditions RC4650 Write Buffer. 3-10 Memory Management. Chapter Introduction Base Bounds Registers Address Spaces. Virtual Address Space. Physical Address Space. Virtual-to-Physical Address Translation. Virtual Address Base-Bounds Operating Modes. User Mode Operations Kernel Mode Operations 32-bit Kernel Mode, User Space kuseg) 32-bit Kernel Mode, Kernel Space kseg0) 32-bit Kernel Mode, Kernel Space kseg1) 32-bit Kernel Mode kseg2) System Control Coprocessor. Registers IBase Register IBound Register DBase Register (2). DBound Register (3). Processor Revision Identifier (PRId) Register (15) Config Register (16) 4-10 CAlg Register (17).4-11 Cache Registers [TagLo (28). 4-12 Virtual-to-Physical Address Translation Process. 4-13 Exception Processing Chapter Exception Processing Works. Exception Processing Registers. IWatch Register (18) DWatch Register (19) Virtual Address Register (BadVAddr) (8). Count Register Compare Register (11) Status Register (12).
Status Register Modes Access States Status Register Reset Cause Register (13). Exception Program Counter (EPC) Register (14). Error Checking Correcting (ECC) Register (26) Cache Error (CacheErr) Register (27) Error Exception Program Counter (Error EPC). 5-10 Processor Exceptions 5-10 Processor Exception Examples 5-10 Reset Exception Process Example .5-11 Cache Error Exception Process Example .5-11 Soft Reset Exception Process Example .5-11 Interrupt Exception Process Example 5-12 General Exception Process Example. 5-12 Processor Exception Vector Locations 5-12 Priority Exceptions 5-13 Processor Exception Descriptions 5-13 Reset Exception. 5-13 Cause 5-13 Processing. 5-14 Servicing. 5-14 Soft Reset Exception 5-14 Cause 5-14 Processing. 5-14 Servicing. 5-14 Nonmaskable Interrupt (NMI) Exception. 5-14 Cause 5-15 Processing. 5-15 Servicing. 5-15 Address Error Exception. 5-15 Cause 5-15 Processing. 5-15 Servicing. 5-16 Cache Error Exception. 5-16 Cause 5-16 Processing. 5-16 Servicing. 5-16 Error Exception. 5-16 Cause 5-16 Processing. 5-16 Servicing. 5-17 Integer Overflow Exception. 5-17 Cause 5-17 Processing. 5-17 Servicing. 5-17 Trap Exception. 5-17 Cause 5-17 Processing. 5-17 Servicing. 5-17 System Call Exception. 5-18 Cause 5-18
Processing. 5-18 Servicing. 5-18 Breakpoint Exception. 5-18 Cause 5-18 Processing. 5-18 Servicing. 5-18 Reserved Instruction Exception 5-18 Cause 5-19 Processing. 5-19 Servicing. 5-19 Coprocessor Unusable Exception 5-19 Cause 5-19 Processing. 5-19 Servicing. 5-20 Floating-Point Exception. 5-20 Cause 5-20 Processing. 5-20 Servicing. 5-20 Interrupt Exception. 5-20 Cause 5-20 Processing. 5-20 Servicing. 5-20 IWatch Exception 5-21 Cause 5-21 Processing. 5-21 Servicing. 5-21 DWatch Exception 5-21 Cause 5-21 Processing. 5-21 Servicing. 5-21 IBound Exception. 5-21 Cause 5-21 Processing. 5-21 Servicing. 5-21 DBound Exception 5-22 Cause 5-22 Processing. 5-22 Servicing. 5-22 Servicing Flowcharts. 5-22 Floating-Point Unit. Chapter Introduction RC4650 Floating-Point Coprocessor Features Programming Model Floating-Point General Registers (FGRs). Floating-Point Registers Floating-Point Control Registers. Implementation Revision Register, (FCR0) Control/Status Register (FCR31) Accessing Control/Status Register. IEEE Standard 754.
Control/Status Register Control/Status Register Condition Bit. Control/Status Register Cause, Flag, Enable Fields Cause Bits Enable Bits Flag Bits Control/Status Register Rounding Mode Control Bits Floating-Point Formats Binary Fixed-Point Format Instruction Overview. Formats Table through Table 6.12. 6-10 Floating-Point Load, Store, Move Instructions .6-11 Transfers Between Memory .6-11 Transfers Between .6-11 Load Delay Hardware Interlocks 6-12 Data Alignment. 6-12 Endianness. 6-12 Floating-Point Conversion Instructions. 6-12 Floating-Point Computational Instructions. 6-12 Branch Condition Instructions 6-12 Floating-Point Compare Operations. 6-12 Pipeline Overview. 6-13 Instruction Execution 6-13 Instruction Execution Cycle Time 6-14 Instruction Scheduling Constraints. 6-14 Multiplier Constraints. 6-14 Adder Constraints 6-15 Resource Scheduling Rules 6-15 Floating-Point Exceptions Chapter Introduction Exception Types Exception Trap Processing Flags Exceptions Inexact Exception Invalid Operation Exception Division-by-Zero Exception Overflow Exception (O). Underflow Exception (U). Unimplemented Instruction Exception Saving Restoring State Trap Handlers IEEE Standard Exceptions. Processor Signal Descriptions Chapter Introduction System Interface Signals Clock/Control Interface Signals Interrupt Interface Signals. Initialization Interface Signals Initialization Interface Chapter Introduction Functional Overview
Reset Initialization Signal Descriptions. Power-on Reset Cold Reset. Warm Reset Initialization Sequence. Boot-Mode Settings Clock Interface Chapter Introduction 10-1 Signal Terminology 10-1 Basic System Clocks 10-1 MasterClock 10-2 PClock 10-2 System Timing Parameters 10-2 Alignment MasterClock 10-2 Phase-Locked Loop (PLL). 10-3 Components Operation 10-3 Passive Components 10-3 Connecting External Agent 10-4 Cache Organization, Operation Coherency. Chapter Introduction .11-1 Memory Organization .11-1 Overview Cache Operations.11-2 RC4650 Cache Description .11-2 Cache Line Size .11-2 Cache Organization Accessibility .11-2 Organization Primary Instruction Cache (I-Cache).11-3 Organization Primary Data Cache (D-Cache) .11-3 Accessing Primary Caches .11-4 Cache States .11-5 Primary Cache States .11-6 Cache Line Ownership .11-6 Cache Write Policy .11-6 Transition Diagrams.11-7 Cache Coherency Overview .11-7 Cache Coherency Attributes .11-8 Uncached .11-8 Noncoherent.11-8 Cache Operation Modes .11-8 Cache Locking .11-8 When Cache Locking .11-9 Example Data Cache Locking .11-9 Example Instruction Cache Locking .11-10 Processor Synchronization Support .11-10 Test-and-Set .11-10 Counter. 11-11 Load Linked Store Conditional .11-12 Examples Using .11-13 System Interface Overview. Chapter Introduction 12-1 Terminology 12-1
System Interface Description. 12-1 Interface Buses 12-1 Address Data Cycles. 12-2 Issue Cycles 12-2 Handshake Signals 12-3 System Interface Protocols. 12-3 Master Slave States 12-4 Moving from Master Slave State 12-4 External Arbitration. 12-4 Uncompelled Change Slave State 12-5 Processor External Requests 12-5 Rules Processor Requests. 12-6 Processor Requests 12-6 Processor Read Request 12-7 Processor Write Request 12-7 External Requests 12-7 External Read Request 12-9 External Write Request 12-9 System Interface Endianness 12-9 System Interface Cycle Time. 12-9 Release Latency. 12-9 64-Bit System Interface Addresses 12-10 Addressing Conventions 64-Bit Wide Interface. 12-10 32-Bit System Interface Addresses 12-10 Addressing Conventions 32-Bit Wide Interface. 12-10 Read Interface Chapter Introduction 13-1 Read Response 13-1 Handling Requests 13-1 Load Miss 13-2 Store Miss 13-2 Store 13-3 Uncached Loads 13-3 CACHE Operations 13-4 Load Linked/Store Conditional Operation 13-4 Processor Read Protocols 13-4 Processor Read Request. 13-4 Processor Read Request Protocol Steps. 13-5 External Instruction Read Response Time 13-6 Instruction Read Latency Steps System Clock 13-6 Note that:. 13-6 Example Instruction Block Read With Zero Wait State 13-6 External Data Read Response Time 13-6 Data Read Latency Steps System Clock 13-7 Note following:. 13-7 Example Data Single Read With Zero Wait State 13-7 External Cycles Read Latency 13-7 Read Response Protocol. 13-8 Data Rate Control 13-10 Read Data Pattern. 13-10 64-Bit 32-Bit Modes .13-11
64-Bit Mode .13-11 64-Bit Mode Block Read Operation.13-11 64-Bit Mode Single (Uncached) Read Operation.13-11 32-Bit Mode 13-12 32-Bit Mode Block Read Operation. 13-12 32-Bit Mode Single (Uncached) Read Operation. 13-13 Subblock Ordering 13-13 Example Sequential Ordering 13-13 Examples Subblock Ordering. 13-14 Generating Subblock Order Words 13-16 Interface Commands Data Identifiers. 13-17 Command Data Identifier Syntax 13-17 System Interface Command Syntax. 13-17 Read Requests. 13-18 System Interface Data Identifier Syntax 13-19 Noncoherent Data 13-20 Data Identifier Definitions 13-20 Write Interface Chapter Introduction 14-1 Processor Write Protocols 14-1 Processor Write Request Protocol. 14-2 Processor Single Write Request. 14-2 RC4000-Compatible Write Mode 14-2 Write Reissue 14-3 Pipelined Write 14-4 Processor Block Write Request 14-4 Write Data Transfer Patterns. 14-5 Processor Request Flow Control 14-6 64-Bit 32-Bit Modes 14-6 64-Bit Mode 14-7 64-Bit Mode Block Write Operation 14-7 64-Bit Mode Single (Uncached) Write Operation 14-7 RC4000-Compatible Write Mode 14-7 Write Reissue 14-8 Pipelined Write 14-8 32-Bit Mode 14-9 32-Bit Mode Block Write Operation 14-9 32-Bit Mode Single (Uncached) Write Operation 14-10 RC4000-Compatible Write Mode 14-10 Write Reissue .14-11 Pipelined Write .14-11 Sequential Ordering. 14-12 Example Sequential Ordering 14-12 Interface Commands Data Identifiers. 14-15 Command Data Identifier Syntax 14-16 System Interface Command Syntax. 14-16 Write Requests 14-16 System Interface Data Identifier Syntax 14-17 Data Identifier Definitions 14-18 External Request Interface. Chapter Introduction 15-1
External Read Request 15-2 External Write Request 15-2 Read Response. 15-2 Processor External Request Protocols 15-3 External Request Protocols 15-3 External Arbitration Protocol. 15-4 External Read Request Protocol 15-4 External Null Request Protocol 15-5 External Write Request Protocol 15-6 Read Response Protocol. 15-7 Interface Commands Data Identifiers. 15-7 Command Data Identifier Syntax 15-7 System Interface Command Syntax. 15-7 Null Requests 15-8 System Interface Data Identifier Syntax 15-9 Noncoherent Data 15-9 Data Identifier Definitions 15-9 System Interface Addresses. 15-10 Addressing Conventions .15-11 Processor Internal Address .15-11 RC4650 Processor Interrupts. Chapter Introduction 16-1 Hardware Interrupts 16-1 Nonmaskable Interrupt (NMI) 16-1 Asserting Interrupts. 16-1 RC4650 Error Checking Chapter Introduction 17-1 Error Checking Processor. 17-1 Types Error Checking. 17-1 Parity Error Detection 17-1 Error Checking Operation. 17-2 System Interface 17-2 System Interface Command Bus. 17-2 Summary Error Checking Operations. 17-2 Cache Operations Timing.Appendix Introduction Caveats About Cache Operations. Cache Operations Tables Cache Operations Timing. Fill_I Equation Definitions.A-3 Standby Mode Operation.Appendix Entering Standby Mode Coprocessor Hazards .Appendix Introduction .C-1 List Hazards .C-1 Integer Multiply Scheduling .Appendix Integer Multiply Scheduling.D-1 Index Signals. Index-1
Table Table Table Table Table Table Table Table Table Table Table 1.10 Table 1.11 Table 1.12 Table 1.13 Table 1.14 Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 4.10 Table 4.11 Table Table Table Table Table Table Table Table Table Table 5.10 Table 5.11 Table 5.12 Table Table Table Title Page Instruction Set: MIPS /MIPS 2/MIPS Load Store Instructions .1-6 Instruction Set: MIPS /MIPS MIPS Arithmetic Instructions (ALU Immediate) .1-7 Instruction Set: Arithmetic (3-Operand, R-Type).1-7 Instruction Set: MIPS MIPS MIPS Multiply Divide Instructions .1-8 Instruction Set: Jump Branch Instruction .1-9 Instruction Set: Shift Instructions .1-9 Instruction Set: Coprocessor Instructions.1-10 Instruction Set: Special Instructions.1-10 MIPS 2/MIPS Exception Instructions.1-11 RC4650 Instructions.1-11 System Control Coprocessor (CPO) Register Definitions (Page .1-15 Floating-Point Operation .1-17 Mode Virtual Addressing (32-bit mode).1-18 System Interface Comparison Between RC4600/RC4700 RC4650 .1-21 Byte Access within Doubleword .2-3 RC4650 Integer Multiply Operation .2-4 Correspondence Pipeline Stage Interlock Condition.3-6 Pipeline Exceptions .3-7 Pipeline Interlocks .3-7 User Mode Addressing.4-4 u32-bit Kernel Mode Segments.4-6 Registers .4-7 IBase Register Field Descriptions .4-8 IBound Register Field Descriptions .4-8 DBase Register Field Descriptions.4-9 DBound Register Field Descriptions .4-9 PRId Register Fields .4-10 Config Register Fields .4-11 CAlg Register Field Descriptions.4-12 Cache Register Fields .4-13 Exception Processing Registers.5-2 IWatch Register Fields .5-2 DWatch Register Fields.5-3 Status Register Fields .5-5 Cause Register Fields .5-7 Cause Register ExcCode Field .5-7 Register Fields.5-8 CacheErr Register Fields .5-9 Exception Vector Base Addresses .5-12 Exception Vector Offsets .5-13 Exception Priority Order .5-13 List Exception Flowcharts.5-22 Floating-Point Control Register Assignments.6-4 FCRO Fields.6-4
Table Table Table Table Table Table Table Table 6.10 Table 6.11 Table 6.12 Table 6.13 Table 6.14 Table Table Table Table Table Table Table Table Table Table Table Table 11.1 Table 11.2 Table 12.1 Table 13.1 Table 13.2 Table 13.3 Table 13.4 Table 13.5 Table 13.6 Table 13.7 Table 13.8 Table 13.9 Table 13.10 Table 13.11 Table 13.12 Table 13.13 Table 13.14 Table 13.15 Table 13.16 Table 13.17 Table 13.18 Table 14.1 Table 14.2 Table 14.3 Table 14.4 Table 14.5
Control/Status Register Fields Rounding Mode Decoding. Equations Calculating Values Single-Precision Floating-Point Format Floating-Point Format Parameter Values Minimum Maximum Floating-Point Values. Binary Fixed-Point Format Fields Instruction Summary: Load, Move Store Instructions. 6-10 Instruction Summary: Conversion Instructions 6-10 Instruction Summary: Computational Instructions .6-11 Instruction Summary: Compare Branch Instructions .6-11 Mnemonics Definitions Compare Instruction Conditions 6-13 Floating-Point Operation Latencies 6-14 Default Exception Actions Exception-Causing Conditions System Interface Signals 64-Bit Mode. System Interface Signals 32-Bit System Interface Mode. Clock/Control Interface Signals Interrupt Interface Signals Initialization Interface Signals RC4650 Processor Signal Summary RC4650 Processor Signal Summary RC4650 Processor Signal Summary Boot-Mode Settings (Page Cache States .11-6 Coherency Attributes Processor Behavior.11-8 Release Latency External Requests 12-10 Load Miss Primary Cache 13-2 Store Miss Primary Cache 13-3 System Interface Requests 13-4 Steps Single Read With Zero Wait-State 13-6 Steps Data Block Read With Zero Wait-State 13-7 Sequence Doublewords Transferred Using Subblock Ordering: Address 102. 13-15 Sequence Doublewords Transferred Using Subblock Ordering: Address 112. 13-16 Sequence Doublewords Transferred Using Subblock Ordering: Address 012. 13-16 Sequence Words Transferred Using Subblock Ordering: Address 0102. 13-16 Sequence Words Transferred Using Subblock Ordering: Address 1102. 13-17 Encoding SysCmd (7:5) System Interface Commands 13-18 Encoding SysCmd (4:3) Read Requests. 13-18 Encoding SysCmd (2:0) Block Read Request. 13-19 Doubleword, Word, Partial-Word Read Request Data Size Encoding SysCmd (2:0). 13-19 Processor Data Identifier Encoding SysCmd (7:3) 13-20 External Data Identifier Encoding SysCmd (7:3) 13-21 Partial Word Transfer Byte Lane Usage-64-Bit Mode 13-22 Partial Word Transfer Byte Lane Usage-32-Bit Mode 13-23 System Interface Requests 14-1 Transmit Data Rates Patterns 64-Bit Mode 14-5 Transmit Data Rates Patterns 32-Bit Mode 14-6 Partial Word Transfer Byte Lane Usage 14-14 Partial Word Transfer Byte Lane Usage-32-Bit Mode 14-15
Table 14.6 Table 14.7 Table 14.8 Table 14.9 Table 14.10 Table 15.1 Table 15.2 Table 15.3 Table 15.4 Table 15.5 Table 17.1 Table 17.2 Table Table Table
Encoding SysCmd (7:5) System Interface Commands 14-16 Write Request Encoding SysCmd (4:3) 14-17 Block Write Request Encoding SysCmd (2:0) 14-17 Doubleword, Word, Partial-Word Write Request Data Size Encoding SysCmd (2:0). 14-17 Processor Data Identifier Encoding SysCmd(7) 14-18 System Interface Requests 15-3 Encoding SysCmd (7:5) System Interface Commands 15-8 External Null Request Encoding SysCmd (4:3). 15-8 Processor Data Identifier Encoding SysCmd (7:3) 15-10 External Data Identifier Encoding SysCmd (7:3) 15-10 Error Checking Correcting Summary Internal Transactions 17-3 Error Checking Correcting Summary External Transactions. 17-3 Primary Data Cache Operations. Primary Instruction Cache Operations.A-3 Integer Multiply Divide Performance.D-2
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1.10 Figure 1.11 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 4.10 Figure 4.11 Figure 4.12 Figure 4.13 Figure Figure Figure Figure Figure Figure Title Page RC4640/RC4650 Block Diagram.1-3 RC4650 Registers .1-4 Instruction Formats .1-5 Big-Endian Byte Ordering.1-12 Little-Endian Byte Ordering .1-12 Little-Endian Data Doubleword.1-12 Big-Endian Data Doubleword .1-13 Big-Endian Misaligned Word Addressing .1-13 Little-Endian Misaligned Word Addressing.1-14 RC4650 Registers .1-15 Typical System Block Diagram.1-20 Instruction Formats .2-1 Instruction Pipeline Stages.3-2 Pipeline Activities.3-4 Pipeline Branch Delay .3-5 Pipeline Load Delay.3-5 Exception Detection .3-8 Data Cache Miss .3-9 Instruction Cache Miss .3-10 Overview RC4650 Virtual-to-Physical Address Translation.4-2 32-bit Virtual Address Translation .4-3 User Mode Virtual Address Space .4-4 Kernel Mode Address Space.4-5 IBase Register.4-8 IBound Register.4-8 DBase Register .4-9 DBound Register .4-9 Processor Revision Identifier Register Format.4-9 Config Register Format .4-10 CAlg Register .4-12 TagLo Register (P-cache) Format .4-12 Base-Bounds Address Translation .4-13 IWatch Register Format .5-2 DWatch Register Format .5-3 BadVAddr Register Format .5-3 Count Register Format .5-4 Compare Register Format.5-4
Figure Figure Figure Figure Figure 5.10 Figure 5.11 Figure 5.12 Figure 5.13 Figure 5.14 Figure 5.15 Figure 5.16 Figure 5.17 Figure 5.18 Figure 5.19 Figure 5.20 Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 11.1 Figure 11.2 Figure 11.3 Figure 11.4 Figure 11.5 Figure 11.6 Figure 11.7 Figure 11.8
Status Register Cause Register Format Register Format Register Format CacheErr Register Format. ErrorEPC Register Format 5-10 Reset Exception Processing.5-11 Cache Error Exception Processing.5-11 Soft Reset Exception Processing.5-11 Interrupt Exception Processing. 5-12 General Exception Processing (Except Reset, Soft Reset, NMI, Cache Error) 5-12 General Exception Handler (HW) 5-23 General Exception Servicing Guidelines (SW) 5-24 Cache Error Exception Handling (HW) Servicing Guidelines (SW). 5-25 Reset, Soft Reset Exception Handling (HW) Servicing Guidelines (SW). 5-26 Functional Block Diagram Registers Implementation/Revision Register. Control/Status Register Assignments Control/Status Register Cause, Flag, Enable Fields Single-Precision Floating-Point Format Binary Fixed-Point Format. Instruction Pipeline 6-13 Control/Status Register Exception/Flag/Trap/Enable Bits RC4650 Processor Signals Power-on Reset. Cold Reset. Warm Reset. Signal Transitions 10-1 Clock-to-Q Delay 10-1 Processor Clocks, MasterClock- to-PClock Multiply 10-2 Passive Components 10-3 RC4650 Processor System 10-4 Logical Hierarchy Memory .11-1 Cache Support RC4650.11-2 RC4650 Primary I-Cache Line Format .11-3 RC4650 8-Word Primary Data Cache Line Format .11-4 Primary Cache Data Organization .11-5 Primary Data Cache State Diagram .11-7 Synchronization with Test-and-Set 11-11 Synchronization Using Counter .11-12
Figure 11.9 Figure 11.10 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 Figure 12.9 Figure 12.10 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Figure 13.9 Figure 13.10 Figure 13.11 Figure 13.12 Figure 13.13 Figure 13.14 Figure 13.15 Figure 13.16 Figure 13.17 Figure 13.18 Figure 13.19 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Figure 14.7 Figure 14.8
Test-and-Set using SC.11-13 Counter Using SC.11-14 System Interface Buses. 12-2 State RdRdy* Signal Read Requests 12-2 State WrRdy* Signal Write Requests 12-3 System Interface Register-to-Register Operation. 12-4 Requests System Events 12-5 Back-to-Back Write Cycle Timing (RC4000 compatible mode). 12-6 Processor Requests 12-6 Processor Request 12-7 External Requests 12-8 External Request 12-8 Read Response. 13-1 Processor Read Request Protocol 13-5 Uncached Read-External Cycles 13-7 Processor Read Cycle. 13-8 Processor Word Read Request Followed Word Read Response (64-bit interface). 13-9 Block Read Response With Zero Wait State (64-bit interface). 13-9 Block Read Transaction With Wait State (64-bit interface). 13-10 Read Response, Reduced Data Rate, System Interface Slave State (64-bit interface). 13-10 Block Read Transaction With Wait State .13-11 64-Bit Uncached Read-External Cycles. 13-12 Block Read Transaction With Wait State 13-12 32-Bit Mode Uncached Read Single Word 13-13 32-Bit Mode Uncached Read Double Word 13-13 Retrieving Data Block Sequential Order 13-14 Retrieving Data Subblock Order 13-14 Retrieving Data Subblock Order 13-15 System Interface Command Syntax Definition 13-17 Read Request SysCmd Definition. 13-18 Data Identifier SysCmd Definition 13-19 Processor Noncoherent Word Write Request Protocol 14-2 RC4000 Compatible Write Mode 14-3 Write Reissue 14-3 Pipelined Writes. 14-4 Processor Noncoherent Block Write Request Protocol 14-5 Processor Write Requests, Second Write Delayed Assertion WrRdy* 14-6 Processor Noncoherent Block Write Request Protocol 14-7 RC4000 Compatible Write Mode 14-8
Figure 14.9 Figure 14.10 Figure 14.11 Figure 14.12 Figure 14.13 Figure 14.14 Figure 14.15 Figure 14.16 Figure 14.17 Figure 14.18 Figure 14.19 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Figure 15.7 Figure 15.8 Figure 15.9 Figure 15.10 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure
Write Reissue 14-8 Pipelined Writes. 14-9 Processor Noncoherent Block Write Request Protocol 14-10 RC4000 Compatible Write Protocol. 14-10 Write Reissue .14-11 Pipelined Writes.14-11 Transferring Data Block Sequential Order 14-12 Transferring Data Subblock Order 14-13 System Interface Command Syntax Definition 14-16 Write Request SysCmd Definition 14-16 Data Identifier SysCmd Definition 14-18 External Requests 15-1 External Request 15-1 Read Response. 15-3 Arbitration Protocol External Requests 15-4 External Read Request, System Interface Master State 15-5 System Interface Release External Null Request. 15-6 External Write Request, with System Interface Initially Master State. 15-7 System Interface Command Syntax Definition 15-8 Null Request SysCmd Definition 15-8 Data Identifier SysCmd Definition 15-9 Interrupt Register Bits Enables 16-1 RC4650 Interrupt Signals 16-2 RC4650 Nonmaskable Interrupt Signal 16-2 Masking RC4650 Interrupts 16-3 Standby Mode Operation.
IDT79RC4640TM/IDT79RC4650is low-cost member Orion family that targeted variety performance-hungry embedded applications. RC4650 continues Orion tradition high-performance through high-speed pipelines, high-bandwidth caches interface, 64-bit architecture, careful attention efficient control. RC4650 reduces cost this performance- relative RC4600-by removing functional units frequently required many embedded applications, such double-precision floating point arithmetic Transition Lookaside Buffer (TLB). Note: Throughout this manual, references IDT79RC4650 RC4650 also refer IDT79RC4640 RC4640. RC4640 device that only supports 32-bit width; otherwise, RC4640 RC4650 identical. RC4650 adds features relative RC4600, reflective target applications. These features enable system cost reduction (e.g. optional 32-bit system interface) well higher performance certain types systems (such cache locking, improved real-time support, integer digital signal processing (DSP) capability). RC4650 supports wide variety embedded processor-based applications, such games systems, multi-media functions, internetworking/data communications equipment, office networking systems. Upwardly software-compatible with RC3000 RISController family upwardly software-compatible with Orion family, RC4650 will serve many same applications. addition, RC4650 will support applications that require functions.
RC4650 brings Orion performance levels lower cost systems. Orion performance preserved retaining large on-chip caches that two-way associative, streamlined high-speed pipeline, high-bandwidth, 64-bit execution, facilities such early restart data cache misses. These techniques combine allow system designer over 2GB/sec aggregate internal bandwidth, MB/sec bandwidth, Dhrystone MIPS, 44MFlops, 66.7 multiply-add/second (all MHz).
RC4650 provides complete upward application-software compatibility with IDT79RC3000family microprocessors, including 79RC3081TM, 79RC4600TM, 79RC4700families microprocessors. array tools facilitates rapid development RC4650-based systems, allowing wide variety customers take advantage processor's high-performance capabilities while maintaining short time-to-market goals. 64-bit computing capability RC4650 permits access performance levels that were previously limited lower bandwidth bit-manipulation rates inherent 32-bit architectures. example, RC4650 perform loads stores from cached memory rates 8-bytes every clock cycle, doubling bandwidth equivalent 32-bit processor. This ability-coupled with high clock rate RC4650 pipeline-obtains levels performance from embedded systems. summary features RC4650 follows. detailed feature-by-feature comparison between R4000 RC4650, refer Table 1.14.
High-performance embedded 64-bit microprocessor 64-bit integer operations 64-bit registers 80MHz, 100MHz, 133MHz operation frequency 3.3V versions High-performance capability 66.7 Million Integer Multiply-Accumulate Operations/sec MFlops floating point operations @133MHz High-performance microprocessor 66.7 Mul-Add/second 133MHz MFLOP/s 133MHz >300,000 dhrystone (2.1)/sec capability 133MHz (175 dhrystone MIPS) High level integration 64-bit, MIPS integer 44MFlops Single precision floating-point unit instruction cache; data cache Integer DSP/multiply unit with 66.7M Mul-Add/sec Low-power operation Less than peak internal power 100MHz Active power management powers-down inactive units Standby mode power consumption <200mW Upward software compatible with RISControllerFamily Large, efficient on-chip caches Separate Instruction Data caches Over 1500MB/sec bandwidth from internal caches 2-set associative Write-back write-through support Cache locking facilitate deterministic response compatible with RC4600/RC4700 Orion family System interfaces MHz, provides bandwidth MB/S Direct interface 32-bit wide 64-bit wide systems Synchronized external reference clock multi-master operation Improved real-time support Fast interrupt decode Optional cache locking
RC4650 level integration designed high-performance high-bandwidth computing. elements RC4650 illustrated below, with overview these features following. More detailed information will presented subsequent chapters.
Figure presents block level representation RC4650's functional units.
MIPS 64-bit Orion
Register file
System Control Coprocessor
Address Translation/ Cache Attribute Control
44MFLOPS Single-Precision
register file
Adder Load aligner Store Aligner Logic Unit High-Performance Integer Multiply/DSP Pipeline Control Exception Management Functions Pipeline Control
Pack/Unpack
Add/Sub/Cvt/ Div/Sqrt
Multiply
Control Data Instruction
Instruction Cache (Lockable) Instruction Cache 32-/64-bit Synchronized System Interface
Data Cache (Lockable) Data Cache
Figure RC4640/RC4650 Block Diagram
RC4650 implements 5-stage pipeline similar IDT79R3000 IDT79RC4600/ RC4700. simplicity this pipeline allows RC4650 lower cost, lower powered processor than super-scalar super-pipelined processors. Unlike superscalar processors, applications that have large data dependencies require great deal load/stores still achieve levels close peak performance processor. Refer Chapter detailed discussion pipeline operation, including descriptions instruction latencies, interruptions pipeline flow caused interlocks exceptions, RC4650 implementation store buffer. detailed discussion pipeline, refer Chapter
RC4650 thirty-two general-purpose 64-bit registers. These registers used scalar integer operations address calculation. register file consists read ports write port fully bypassed minimize operation latency pipeline. Figure shows RC4650 registers.
General Purpose Registers Multiply Divide Registers
Program Counter
Figure RC4650 Registers
general purpose registers have following assigned functions: hardwired value zero, used target register instruction whose result discarded. also used source when zero value needed. used implicit return destination address register series instructions. also these three special purpose registers: Program Counter register Multiply Divide register higher result Multiply Divide register lower result Also, Multiply Divide registers (HI, will store product integer multiply operations, quotient remainder integer divide operations. RC4650 processor does have Program Status Word (PSW) register such. function covered Status Cause registers incorporated within System Control Coprocessor (CP0). registers described later this chapter.
Each instruction bits long. shown Figure 1.3, there three instruction formats: immediate (I-type) jump (J-type) register (R-type)
I-Type (Immediate)
target
immediate
J-Type (Jump) R-Type (Register)
funct
Figure Instruction Formats
Each format contains number different instructions, which described further this chapter. Fields instruction formats described Chapter limiting number formats these three, instruction decoding simplified. Through this limitation, more complicated (and less frequently used) operations addressing modes synthesized compiler, using sequences these same simple instructions. instruction further divided into following groups: Load Store instructions move data between memory general registers. They immediate (I-type) instructions, since only addressing mode supported base register plus 16-bit, signed immediate offset. Computational instructions perform arithmetic, logical, shift, multiply, divide operations values registers. They include register (R-type, which both operands result stored registers) immediate (I-type, which operand 16-bit immediate value) formats. Jump Branch instructions change control flow program. Jumps always made paged, absolute address formed combining 26-bit target address with high-order bits Program Counter (J-type format) register address (R-type format). Branches have 16-bit offsets relative program counter (I-type). Jump Link instructions save their return address register Coprocessor instructions perform operations coprocessors. Coprocessor load store instructions I-type. Coprocessor (system coprocessor) instructions perform operations registers control memory management exception handling facilities processor standby mode power management. Special instructions perform system calls breakpoint operations. These instructions always R-type. Exception instructions cause branch general exception-handling vector based upon result comparison. These instructions occur both R-type (both operands result registers) I-type (one operand 16-bit immediate value) formats. Chapter provides more detailed information these instructions. complete description each located Appendix
Tables through 1.13 lists instructions common MIPS R-Series processors, along with level which they first appeared. last column each table refers MIPS level which instruction first appeared. Table 1.10 shows instructions.
SYNC
Note:
Load Byte Load Byte Unsigned Load Halfword Load Halfword Unsigned Load Word Load Word Left Load Word Right Store Byte Store Halfword Store Word Store Word Left Store Word Right Load Doubleword Load Doubleword Left Load Doubleword Right Load Linked Load Linked Doubleword Load Word Unsigned Store Conditional Store Conditional Doubleword Store Doubleword Store Doubleword Left Store Doubleword Right Sync
Tables through 1.17 this column refers level which instruction first appeared.
Table Instruction Set: MIPS /MIPS 2/MIPS Load Store Instructions
ADDI ADDIU SLTI SLTIU ANDI XORI DADDI DADDIU Immediate Immediate Unsigned Less Than Immediate Less Than Immediate Unsigned Immediate Immediate Exclusive Immediate Load Upper Immediate Doubleword Immediate Doubleword Immediate Unsigned
Table Instruction Set: MIPS /MIPS MIPS Arithmetic Instructions (ALU Immediate)
ADDU SUBU SLTU DADD DADDU DSUB DSUBU Unsigned Subtract
Subtract Unsigned Less Than Less Than Unsigned Exclusive Doubleword Doubleword Unsigned Doubleword Subtract Doubleword Subtract Unsigned
Table Instruction Set: Arithmetic (3-Operand, R-Type)
MADU MULT MULTU DIVU MFHI MTHI MFLO MTLO DMULT DMULTU DDIV DDIVU Multiply-Add Multiply-Add Unsigned 3-Operand Multiply Multiply (result HI/LO) Multiply Unsigned (result HI/LO) Divide Divide Unsigned Move From Move Move From Move Doubleword Multiply Doubleword Multiply Unsigned Doubleword Divide Doubleword Divide Unsigned
Note: These IDT-proprietary extensions MIPS instruction set. Table Instruction Set: MIPS MIPS MIPS Multiply Divide Instructions
JALR BLEZ BGTZ BLTZ BGEZ BLTZAL BGEZAL BEQL BNEL BLEZL BGTZL BLTZL BGEZL BLTZALL BGEZALL BCzTL BCzFL Jump Jump Link Jump Register
Jump Link Register Branch Equal Branch Equal Branch Less Than Equal Zero Branch Greater Than Zero Branch Less Than Zero Branch Greater Than Equal Zero Branch Less Than Zero Link Branch Greater Than Equal Zero Link Branch Equal Likely Branch Equal Likely Branch Less Than Equal Zero Likely Branch Greater Than Zero Likely Branch Less Than Zero Likely Branch Greater Than Equal Zero Likely Branch Less Than Zero Link Likely Branch Greater Than Equal Zero Link Likely Branch Coprocessor True Likely Branch Coprocessor False Likely
Table Instruction Set: Jump Branch Instruction
SLLV SRLV
Shift Left Logical Shift Right Logical Shift Right Arithmetic Shift Left Logical Variable Shift Right Logical Variable
Table Instruction Set: Shift Instructions
SRAV DSLL DSRL DSRA DSLLV DSRLV DSRAV DSLL32 DSRL32 DSRA32
Shift Right Arithmetic Variable Doubleword Shift Left Logical Doubleword Shift Right Logical Doubleword Shift Right Arithmetic Doubleword Shift Left Logical Variable Doubleword Shift Right Logical Variable Doubleword Shift Right Arithmetic Variable Doubleword Shift Left Logical Doubleword Shift Right Logical Doubleword Shift Right Arithmetic
Table Instruction Set: Shift Instructions
LWCz SWCz MTCz MFCz CTCz CFCz COPz BCzT BCzF DMFCz DMTCz LDCz SDCz
Load Word Coprocessor Store Word from Coprocessor Move Coprocessor Move From Coprocessor Move Control Coprocessor Move Control From Coprocessor Coprocessor Operation Branch Coprocessor True Branch Coprocessor False Doubleword Move From Coprocessor Doubleword Move Coprocessor Load Double Coprocessor Store Double Coprocessor
Table Instruction Set: Coprocessor Instructions
SYSCALL BREAK Break
System Call
Table Instruction Set: Special Instructions
TGEU TLTU TGEI TGEIU TLTI TLTIU TEQI TNEI
Trap Greater Than Equal Trap Greater Than Equal Unsigned Trap Less Than Trap Less Than Unsigned Trap Equal Trap Equal Trap Greater Than Equal Immediate Trap Greater Than Equal Immediate Unsigned Trap Less Than Immediate Trap Less Than Immediate Unsigned Trap Equal Immediate Trap Equal Immediate Table MIPS 2/MIPS Exception Instructions
DMFC0 DMTC0 MTC0 MFC0 TLBR TLBWI TLBWR TLBP CACHE ERET WAIT
Doubleword Move From Doubleword Move Move Move from Read Indexed Entry Write Indexed Entry Write Random Entry Probe Matching Entry Cache Operation Exception Return Enter Standby mode Table 1.10 RC4650 Instructions
RC4000only RC4000 only Orion family
RC4650 processor uses four data formats: 64-bit doubleword, 32-bit word, 16-bit halfword, 8-bit byte. Byte ordering within each larger data formats-halfword, word, doubleword-can configured either big-endian little-endian order. Endianness refers location byte within multi-byte data structure. Figures show ordering bytes within words ordering words within multiple-word structures big-endian little-endian conventions. When RC4650 processor configured big-endian system, byte most-significant (leftmost) byte, thereby providing compatibility with 68000 conventions. Figure illustrates this configuration.
Higher Address
Word Address
Lower Address
Figure Big-Endian Byte Ordering
When configured little-endian system, byte always least-significant (rightmost) byte, which compatible with iAPX conventions. Figure illustrates this configuration.
Higher Address
Word Address
Lower Address
Figure Little-Endian Byte Ordering
this text, always least-significant (rightmost) bit; thus, designations always little-endian (although instructions explicitly designate positions within words). Figures show little-endian big-endian byte ordering doublewords.
Most-significant byte
Least-significant byte Word
Byte Halfword
Byte
Bits Byte
Figure Little-Endian Data Doubleword
Most-significant byte Least-significant byte Word Byte Halfword Byte Bits Byte
Figure Big-Endian Data Doubleword
uses byte addressing halfword, word, doubleword accesses with following alignment constraints: Halfword accesses must aligned even byte boundary 4.). Word accesses must aligned byte boundary divisible four 8.). Doubleword accesses must aligned byte boundary divisible eight 16.). following special instructions load store words that aligned 4-byte (word) 8word (doubleword) boundaries:
These instructions used pairs provide addressing misaligned words. Addressing misaligned data incurs additional instruction cycle over that required addressing aligned data. This extra cycle because extra instruction "pair" (e.g., form pair). Also note that moves unaligned data same rate hardware mechanism. Figures show access misaligned word that byte address
Higher Address
Lower Address
Figure Big-Endian Misaligned Word Addressing
Higher Address Lower Address
Figure Little-Endian Misaligned Word Addressing
MIPS (MIPS Instruction with extensions) RC4650 defines three coprocessors, designated through CP2: Coprocessor (CP0) incorporated chip supports virtual memory system exception handling. also referred System Control Coprocessor. Coprocessor (CP1) incorporated RC4650, implements MIPS single-precision floating-point instruction set. Coprocessor (CP2) reserved future use. RC4650 described sections that follow.
translates virtual addresses into physical addresses manages exceptions transitions between kernel user states. also controls cache subsystem, well providing diagnostic control error recovery facilities. also used control power management RC4650. This standby mode used reduce power consumption internal core CPU. standby mode entered executing WAIT instruction with SysAD idle exited interrupt. This feature discussed Appendix registers shown Figure 1.10 described Table 1.11 manipulate memory management exception handling capabilities CPU. Note: Access reserved undefined register results undefined. exception result.
Register Name IBase IBound DBase DBound
Reg.
Register Name Config CAlg IWatch DWatch
BadVAddr Count Compare Cause PRId
CacheErr TagLo ErrorEPC
Reg.
Exception Processing
Memory Management Figure 1.10 RC4650 Registers
Reserved
,-IBase IBound DBase DBound BadVAddr Count Compare Cause PRId Config
Provides User Instruction address space Base Provides User Instruction address space Bound Provides User Data address space Base Provides User Data address space Bound Reserved Reserved Reserved Reserved virtual address Timer Count Reserved Timer Compare Status register Cause last exception Exception Program Counter Processor Revision Identifier Configuration register
Table 1.11 System Control Coprocessor (CPO) Register Definitions (Page
21-25
,-CAlg IWatch DWatch CacheErr TagLo ErrorEPC Cache attributes control
read/write register that specifies Instruction virtual address that causes Watch exception. read/write register that specifies Data virtual address that causes Watch exception. Reserved Reserved Secondary-cache error checking correcting (ECC) Primary parity Cache Error Status register Cache register Reserved Error Exception Program Counter Reserved
Table 1.11 System Control Coprocessor (CPO) Register Definitions (Page
RC4650 incorporates entire single-precision floating-point co-processor chip, including floating-point register file execution units. floating-point co-processor forms "seamless" interface with integer unit, decoding executing instructions parallel with integer unit.
RC4650 floating-point execution units perform single-precision arithmetic, specified IEEE Standard 754. execution unit broken into separate multiply unit combined add/ convert/divide/square root unit. Overlap multiplies add/subtract supported. multiplier partially pipelined, allowing multiply begin every cycles. IDT79RC4600, RC4650 maintains fully precise floating-point exceptions while allowing both overlapped pipelined operations. Precise exceptions extremely important mission-critical environments, highly desirable debugging environment. floating-point unit's operation includes floating-point add, subtract, multiply, divide, square root, conversion between fixed-point floating-point format, floating-point compare. These operations comply with IEEE Standard 754. Double-precision operations directly supported; attempts execute double-precision floating point operations, refer directly double-precision registers, result RC4650 signalling "trap" CPU, enabling emulation requested function. Table 1.12 gives latencies some floating-point instructions internal processor cycles
SQRT FLOAT LWC1 SWC1
Table 1.12 Floating-Point Operation
'The RC4650 provides modes operation: user mode kernel mode Kernel mode operation typically used exception handling operating system kernel functions, including management access devices. kernel mode, software access entire address space co-processor registers select whether enable coprocessor accesses. processor enters kernel mode reset, whenever exception recognized. User mode operation typically used applications programs. User mode accesses limited subset virtual address space, inhibited from accessing functions. address space, which shown Table 1.13, divided into addresses accessible either kernel user mode (kuseg), addresses only accessible kernel mode (kseg2:0).
0xFFFFFFFF Kernel virtual address space (kseg2) Unmapped, 0xC0000000 0xBFFFFFFF Uncached kernel physical address space (kseg1) Unmapped, 0.5GB 0xA0000000 0x9FFFFFFF Cached kernel physical address space (kseg0) Unmapped, 0.5GB 0x80000000 0x7FFFFFF
User virtual address space (useg) Mapped, 2.0GB
0x00000000 Table 1.13 Mode Virtual Addressing (32-bit mode)
Sharing common virtual addresses mapped separate physical addresses, RC4650 supports multiple user tasks. This facility implemented "base-bounds" registers contained CP0. When user virtual address asserted (load, store, instruction fetch), RC4650 compares virtual address with contents appropriate "bounds" register (instruction data). virtual address bounds," value corresponding "base" register added virtual address form physical address that reference. address within bounds, exception signalled. This facility enables multiple user processes single physical memory without TLB. This type operation further supported number development tools RC4650, including real-time operating systems "position independent" code. Kernel mode addresses base-bounds registers, rather undergo fixed virtual physical address translation. detailed explanation this addressing mechanism given Chapter
RC4650 implements simple mechanism support mapping virtual physical addresses. RC4650, structure found IDT79RC4600 been replaced base-bounds mechanism. When address translated, page number first compared against Bounds register. address range," base register added virtual address form physical address. RC4650 contains sets base-bounds registers, instruction address translation (IBase IBounds registers) data (DBase DBounds registers). operating system support task protection writing appropriate values these registers context switch time.
Finally, allow cache attributes single system, RC4650 also implements Cache Algorithm (CAlg) register CP0. This register allows operating system define cache management attributes different portions address space. using appropriate virtual addresses, memory treated uncached, write-back, write-through, with separate attributes each eight memory regions. conjunction with external system address decoder, software then alias same physical memory with different management algorithms, depending upon data program that running.
keep RC4650's high-performance pipeline full operating efficiently, RC4650 incorporates on-chip instruction data caches that accessed single processor cycle. Each cache 64-bit data path accessed parallel. cache subsystem provides integer floating-point units with aggregate bandwidth over 1.5GB second.
RC4650 incorporates two-way associative on-chip instruction cache. This virtually indexed, physically tagged cache size protected with word parity. Because cache virtually indexed, virtual-to-physical address translation occurs parallel with cache access, thus further increasing performance allowing these operations occur simultaneously. holds 24-bit physical address valid parity protected. instruction cache 64-bits wide refilled accessed single processor cycle. Instruction fetches require only bits cycle, peak instruction bandwidth MB/sec 133MHz. Sequential accesses take advantage 64-bit fetch reduce power dissipation, cache miss refill writes bits cycle minimize cache miss penalty. maximize performance, line size eight instructions bytes). addition, contents instruction cache (set "A") "locked" setting register. Locking prevents contents from being overwritten subsequent cache miss; refill occurs then only into "set This operation effectively "locks" time critical code into set, while allowing other service other instruction streams normal fashion. Thus, benefits cached performance achieved, while deterministic real-time response preserved.
fast, single cycle data access, RC4650 includes on-chip data cache that twoway associative with fixed 32-byte (eight word) line size. Both D-cache I-cache accessed each pipeline cycle; thus, data bandwidth over MB/sec MHz, addition MB/sec instruction bandwidth. data cache protected with byte parity protected with single parity bit. virtually indexed physically tagged allow simultaneous address translation data cache access D-cache allows write-back write-through operation functions address space individually controlled through field CAlg register. Once initialized, software need only assert desired virtual address desired effect. Associated with data cache store buffer. When RC4650 executes store instruction, this single-entry buffer gets written with store data while comparison performed. matches, then data written into data cache next cycle that data cache accessed (the next non-load cycle). store buffer allows RC4650 execute store every processor cycle perform back-to-back stores without penalty.
Writes external memory, whether cache miss write-backs stores uncached writethrough addresses on-chip write buffer. write buffer holds four 64-bit address data pairs cache line written back. entire buffer used data cache write-back allows processor proceed parallel with memory update. uncached write-through stores, write buffer significantly increased performance over other R4000-family processors.
RC4650 uses system interface clock input clock. pipeline speed derived from this clock using multiply input reference. assumed that system designer manages system clock distribution needs system. Thus, RC4650 does output system reference clock, rather operates synchronization with input clock. RC4650 does output frequency reference clock: Mode clock. This clock operates 1/256 rate input clock, used clock serial initialization stream during reset.
RC4650 supports 64-bit system interface that compatible with R4400PC system interface. This interface operates from input Reference clock. interface consists 64-bit address/data with check bits 9-bit command bus. There also handshake signals interrupt inputs. interface simple timing specification capable transferring data between processor memory peak rate 400MB/sec 50MHz. addition, RC4650 supports boot-time option system interface bits wide, using basically same protocols 64-bit system. This feature allows system designer reduce costs overall memory system without sacrificing computational performance. Figure 1.11 shows typical system using RC4650. this example there DRAM, boot EPROM, optional secondary cache.
Address Boot DRAM (80ns) Control
SCSI
ENET
RC4650
Control Control
Controller
Figure 1.11 Typical System Block Diagram
,&&4
*+.*/
Table 1.14 compares RC4650 features with those RC4600/RC4700. This list exhaustive.
I-Cache size D-Cache size Cacheability control Memory translation Floating point accelerator Integer multiply Integer multiply-add Clock interface
,&&4,#&&
16KB 16KB TLB, field Single- double-precision MIPS standard only cycles Input clock pipeline; System clock derived from pipeline clock multiple output reference clocks. 64-bit None CAlg Base-Bounds
Single-precision only MIPS standard operand (2-3 cycles) cycle repeat rate Input clock system clock; pipeline clock derived from there; system output clock 32-bit 64-bit I-Watch D-Watch (per set) (optional)
interface width Watch registers Cache locking Separate Interrupt vector
Table 1.14 System Interface Comparison Between RC4600/RC4700 RC4650
,&&4
This chapter overview central processing unit (CPU) instruction set. description individual instruction refer Appendix "CPU Instruction Details." overview floating-point unit (FPU) instruction refer Chapter "The Floating Point Unit." description individual instruction, refer the, "FPU Instruction Details" located MIPS Microprocessor Family Software Reference Manual.
Each instruction consists single 32-bit word, aligned word boundary. There three instruction formats, shown Figure 2.1: Immediate (I-type) Jump (J-type) Register (R-type) small number instruction formats simplifies instruction decoding (thus higher frequency operations) allowing compiler synthesize more complicated (and less frequently used) operations addressing modes from these three formats needed.
I-Type (Immediate)
J-Type (Jump)
immediate
R-Type (Register)
target
funct
Figure: immediate target funct
6-bit operation code 5-bit source register specifier 5-bit target (source/destination) register branch condition 16-bit immediate value, branch displacement address displacement 26-bit jump target address 5-bit destination register specifier 5-bit shift amount 6-bit function field
Figure Instruction Formats
MIPS architecture, coprocessor instructions implementation-dependent. Refer MIPS Microprocessor Family Software Reference Manual details individual Coprocessor instructions.
Load store immediate (I-type) instructions that move data between memory general registers. only addressing mode that load store instructions directly support base register plus 16-bit signed immediate offset.
load instruction that does allow result used instruction immediately following called delayed load instruction. instruction slot immediately following this delayed load instruction referred load delay slot. RC4650 processor, instruction immediately following load instruction request contents loaded register, however, such cases, hardware interlocks insert additional real cycles. Consequently, scheduling load delay slots desirable, both performance RSeries (e.g., RC3051) processor compatibility. However, scheduling load delay slots absolutely required.
Access type indicates size RC4650 processor data item loaded stored, load store instruction opcode. Access types defined Appendix MIPS Microprocessor Family Software Reference Manual. Regardless access type byte ordering (endianness), address given specifies loworder byte addressed field. big-endian configuration, low-order byte most-significant byte; little-endian configuration, low-order byte least-significant byte. access type, together with three low-order bits address, define bytes accessed within addressed doubleword, which shown Table 2.1. Only combinations shown this table permissible. Other combinations will cause address error exceptions.
Doubleword Septibyte
Sextibyte
Quintibyte
Word
Triplebyte
Halfword
Byte
Table Byte Access within Doubleword
Computational instructions either following formats: register (R-type) format, which both operands registers. immediate (I-type) format, which operand 16-bit immediate. Computational instructions perform following operations register values: arithmetic logical shift multiply divide These operations following four categories computational instructions: Immediate instructions three-Operand Register-Type instructions shift instructions multiply divide instructions
Operands 32-bit operand opcodes must sign-extended form. 32-bit operand opcodes include non-doubleword operations, such ADD, ADDU, SUB, SUBU, ADDI, SLL, SRL, SRA, SLLV, etc. result operations that incorrect sign-extended 32-bit values unpredictable.
RC4650 hardware interlocks necessary order allow complete execution multiply divide instructions. Latency number clock cycles until result available. Repeat number clock cycles until instruction repeated. Stall number clock cycles will automatically stall. MFHI MFLO instructions (more detail instruction sets located Appendix MIPS Microprocessor Family Software Reference Manual) interlocked that attempt read them before prior multiply divide instructions complete delays execution these instructions until prior instructions finish. Table gives number processor cycles (PCycles) required resolve interlock stall between various multiply divide instructions, subsequent MFHI MFLO instruction.
MULT/U, MAD/U
DMULT, DMULTU DIV, DIVU DDIV, DDIVU
RC4650 automatically detects operand size. Note: more information about these computational instructions, refer Appendix
Table RC4650 Integer Multiply Operation
Jump branch instructions change control flow program. jump branch instructions occur with delay instruction: that instruction immediately following jump branch (this known instruction delay slot) always executes while target instruction being fetched from storage.
Subroutine calls high-level languages usually implemented with Jump Jump Link instructions, both which J-type instructions. J-type format, 26-bit target address shifts left bits combines with high-order bits current program counter form absolute address. Returns, dispatches, large cross-page jumps usually implemented with Jump Register Jump Link Register instructions. Both R-type instructions that take 32-bit 64-bit byte address contained general purpose registers. more information about jump instructions, refer individual instruction described Appendix
branch instruction target addresses computed adding address instruction delay slot 16-bit offset (shifts left bits sign-extended bits). branches occur with delay instruction. conditional branch likely taken, instruction delay slot nullified. regular conditional branches, delay slot always executed. more information about branch instructions, refer instructions Appendix
Special instructions allow software initiate traps; they always R-type. more information about special instructions, refer individual instruction described Appendix
Exception instructions extensions MIPS ISA. more information about exception instructions, refer individual instruction described Appendix
Coprocessor instructions perform operations their respective coprocessors. Coprocessor loads stores I-type, coprocessor computational instructions have coprocessor-dependent formats. Individual coprocessor instructions described Appendices (for CP0) (for FPU, CP1). instructions perform operations specifically System Control Coprocessor registers manipulate memory management exception handling facilities processor. Appendix contains details instructions.
This chapter describes basic operation pipeline, including descriptions delay instructions (instructions that follow branch load instruction pipeline), interruptions pipeline flow caused interlocks exceptions, RC4650 implementation uncached store buffer. pipeline described later chapter.
RC4650 uses 5-stage pipeline similar RC3000. simplicity this pipeline allows RC4650 lower cost lower power than super-scalar super-pipelined processors. Unlike RC3000, RC4650 does virtual physical translation parallel with cache access. This allows RC4650 operate over twice frequency RC3000 support "base-bounds" register address translation. Compared 8-stage RC4000 pipeline, RC4650 more efficient because fewer stalls required. Once pipeline been filled, five instructions executed simultaneously. Figure shows five stages instruction pipeline; next section describes pipeline stages.
cycle
Figure:
1I-1R 1I-2I 2A-2D 1D-2D
Instruction cache access Instruction virtual physical address translation Data cache access load align Data virtual physical address translation
Register file read Bypass calculation
1A-2A
Instruction decode Integer add, logical, shift Data virtual address calculation Store align
Branch decision Register file write
Figure Instruction Pipeline Stages
This section describes each phases five pipeline stages. Each stage phases: Instruction Fetch, Phase Instruction Fetch, Phase Register Fetch, Phase Register Fetch, Phase Execution, Phase Execution, Phase Data Fetch, Phase Data Fetch, Phase Write Back, Phase Write Back, Phase
instruction address translation begins during phase.
During phase, instruction cache fetch begins instruction address translation continues.
During phase, following occurs: instruction cache fetch finishes. instruction cache checked against physical page frame number obtained from address translation.
During phase, following occurs: instruction decoder decodes instruction. required operands fetched from register file. Make decision either issue slip (for interlock condition). branch, branch address calculated.
During phase, following occurs: result from stages bypassed. arithmetic logic unit (ALU) starts integer arithmetic, logical shift operation. calculates data virtual address load store instructions. determines whether branch condition true.
During phase, following occurs: integer arithmetic, logical shift operation will complete. data cache access will start. Store data shifted specified byte position(s). data virtual physical address translation will start.
During phase, following occurs: data cache access will continue. data address translation completes.
During phase data cache access will finish data shifted down extended. data cache checked against physical address data cache access.
This phase used internally processor resolve exceptions, preparation register file write.
register-to-register load instructions, result written back register file during stage. Branch instructions perform operation during this stage. Figure shows activities occurring during each pipeline stage, load, store, branch instructions.
Clock Stage IFetch Decode Load/Store IDEC DCAD Branch DCAA DCLA
Figure: IITC IDEC DCAA
Instruction cache address decode Instruction translation match Instruction check Instruction decode Operation stage Data virtual address calculation Data cache array access Data check Data cache write
DCAD DCLA
Instruction cache array access Register operand fetch Operation stage Write back register file Data cache address decode Data cache load align Data translation match Store align Branch address calculation
Figure Pipeline Activities
pipeline branch delay cycle load delay cycle. one-cycle branch delay result branch decision logic operating during pipeline phase branch instruction. This allows branch target address calculated previous phase used instruction access following phase. pipeline will begin fetch branch path well fall-through path cycle following delay slot. After branch decision made, processor will continue with fetch either branch path (for taken branch) fallthrough path (for non-taken branch).
Figure illustrates branch delay.
Cycle
Cycle
Cycle
Cycle
Cycle
Branch Delay
Branch fall-through address calculated Address selection made
Figure Pipeline Branch Delay
completion load pipeline phase produces operand that available pipeline phase instruction following load delay slot. Figure shows load delay pipeline cycle.
Cycle
Cycle
Cycle
Cycle
Cycle
Load Delay
Figure Pipeline Load Delay
Smooth pipeline flow interrupted when cache misses exceptions occur, when data dependencies detected. Interruptions handled using hardware, such cache misses, referred interlocks, while those that handled using software called exceptions. There types interlocks: stalls, which resolved halting pipeline slips, which require back pipeline advance while front pipeline held static each cycle, exception interlock conditions checked active instructions. Because each exception interlock condition corresponds particular pipeline stage, condition traced back particular instruction exception/interlock stage, shown Table 3.1. instance, Reserved Instruction (RI) exception raised execution stage.
Stall
Slip MDSt
FCBsy
Exceptions IIWatch IPErr
DIntr DWatch
Reset
DPErr Trap
Table Correspondence Pipeline Stage Interlock Condition
description pipeline interlocks exceptions listed Table 3.1, refer Table Table 3.3.
IIntr IPErr
"#External Interrupt Instruction Error Reserved Instruction Breakpoint System Call Coprocessor Unusable Instruction Parity Error Integer Overflow Interrupt Stage Traps
Instruction Translation Bound/Address Exception
ExTrap DDBE DPErr Reset
Data Translation Bound/Address Exception Data Error Data Parity Error Non-maskable Interrupt Soft Reset) Reset Table Pipeline Exceptions
Table Table describe pipeline interlocks exceptions shown Table page
MDSt FCBsy Instruction Cache Miss
Coprocessor Possible Exception Data Cache Miss Load Interlock Multiply/Divide Start Coprocessor Busy Table Pipeline Interlocks
When exception condition occurs, relevant instruction those that follow into pipeline cancelled. Accordingly, stall conditions later exception conditions that have referenced this instruction inhibited; there benefit servicing stalls cancelled instruction. When exceptional condition detected instruction, RC4650 will kill following instructions. When this instruction reaches stage, exception flag causes write various registers with exception state, change current appropriate exception vector address clear exception bits earlier pipeline stages. This implementation allows preceding instructions complete execution prevents subsequent instructions from completing. Thus value sufficient restart execution. also ensures that exceptions taken order execution; instruction taking exception itself killed instruction further down pipeline that takes exception later cycle.
Figure shows exception detection procedure (e.g., reserved instruction exception).
Kill
Exception Vector
Exception Vector ddress
Figure Exception Detection
Stalls used stop pipeline conditions detected after pipe-stage. When stall occurs, processor will resolve condition then pipeline will continue. Figure shows data cache miss stall.
Detect Cache Miss Start moving dirty cache line data write buffer first doubleword into cache restart pipeline Load remainder cache line into cache
Figure Data Cache Miss
data cache miss detected pipe stage. cache line replaced dirty data moved internal write buffer next cycle. first doubleword data returned cache pipeline will then restart. remainder cache line returned subsequent cycles. data written back will returned memory some time after entire cache line returned.
During pipe-stages, internal logic will determine whether possible start current instruction this cycle. source operands available (either from register file internal bypass logic) hardware resources necessary complete instruction will available necessary time(s), then instruction "issues"; otherwise, instruction will "slip". Slipped instructions retried subsequent cycles until they issue. backend pipeline (stages will advance normally during slips attempt resolve conflict. "NOPS" will inserted into bubble pipeline. Instructions killed branch likely instructions, ERET exceptions will cause slips. Figure shows instruction cache miss.
CYCLE Issue Previous Instructions Detect Cache Miss entire cache line into cache Continue pipeline *NOP Inserted instructions Figure Instruction Cache Miss Issue Slip Slip Slip Slip Issue Issue Issue
*NOP *NOP *NOP *NOP
shown Figure 3.7, instruction cache misses detected pipeline slips stage. There never write-back required instruction cache miss since dirty data exist cache. Writes allowed cache. Note that early restart employed instruction cache misses, requested cache line will loaded into cache entirety and, after that, pipeline will restart.
"#$%
"#$%
RC4650 contains write buffer improve performance writes external memory. Writes external memory, whether cache miss write-backs stores uncached write-through addresses, this on-chip write buffer. write buffer holds four 64-bit address data pairs. cache miss write-back, entire buffer used write-back data allows processor proceed parallel with memory update. uncached write-through stores, write buffer uncouples from write memory allowing increased performance over RC4000 family processors. write buffer full, additional stores will stall until there room them write buffer.
RC4650 features simple base-bounds mechanism virtual-to-physical address translation. This mechanism supports multitasking without overhead Translation Lookaside Buffer (TLB) management. companion mechanism that implemented through Cache Algorithm register allows control over cache attributes areas address space.
RC4650 implements simple mechanism support mapping virtual physical addresses. Translation Lookaside Buffer (TLB) structure found IDT79RC4600 IDT79RC4700 replaced base-bounds mechanism. When address translated, page number first compared against Bounds register. address range," base register added virtual address form physical address. RC4650 contains sets base-bounds registers, instruction address translation (IBase IBounds registers) data (DBase DBounds registers). operating system support task protection writing appropriate values these registers context switch time. Finally, allow cache attributes single system, RC4650 also implements Cache Algorithm (CAlg) register CP0. This register allows operating system define cache management attributes different portions address space. merely using appropriate virtual addresses memory treated uncached, write-back, write-through, with separate attributes each eight memory regions. conjunction with external system address decoder, software then alias same physical memory with different management algorithms, depending upon data program that running.
This section describes virtual physical address spaces manner which virtual addresses converted "translated" into physical addresses base-bounds unit.
processor virtual address 32-bits wide. RC4650 truncates addresses bits, ignores upper bits 64-bit registers during address translation.
Figure illustrates RC4650 translates virtual address into physical address.
Virtual Address Space Kseg unmapped GBytes Kseg Uncached* Unmapped GBytes Kseg Unmapped, Cached* GBytes
Physical Address Space
GBytes
Useg Mapped, Cached GBytes
Through Base/Bound Conversion
GBytes
*Default values changed CAlg Register.
Figure Overview RC4650 Virtual-to-Physical Address Translation
Using 32-bit address, processor physical address space encompasses Gigabytes. section following describes translation virtual address physical address.
RC4650 converts virtual address physical address shown following steps. same procedure applies either IBase/IBound DBase/DBound, registers separate. bits 63:32 generated load/store base+offset addition, they discarded. VAddr(31) equals User mode, address error exception generated. However, Kernel mode, then upper bits VAddr (bits 31:29) removed replaced form physical address. kernel address (VAddr(31)=0), then VAddr(30:12) compared Bound(30:12). VAddr greater than Bound address, then Bound exception results. Otherwise, physical address equals (VAddr(31:12) Base(31:12)), concatenated with VAddr(11:0). This shown Figure 4.2. parallel with above operation, cache access rules obtained from CAlg register, using VAddr(31:29) select appropriate CAlg field.
Figure shows virtual-to-physical-address translation 32-bit virtual address.
32-Bit Virtual Address
Offset
(plus)
Base Register Value
Offset passed unchanged. physical
Offset
Offset passed unchanged physical
(equals)
Physical Address
Offset
Virtual Address with (28)16-Mbyte pages
Figure 32-bit Virtual Address Translation
processor operating modes: User mode Kernel mode These modes described following subsections.
User mode, single, uniform virtual address space-labelled User segment-is available; size Gigabytes. Figure shows User mode virtual address space.
FFFF FFFF
Address Error
8000 0000
Mapped
0000 0000
useg
Note: Failure (i.e., results Address Error exception.
Figure User Mode Virtual Address Space
User segment starts address current active user process resides useg. address translator identically maps references useg from both modes. CAlg register controls cache accessibility. processor operates User mode when Status register contains following bitvalues: Table lists characteristics user mode segment useg.
32-bit
useg
0x0000 0000 through 0x7FFF FFFF
Gbyte (231 bytes)
Table User Mode Addressing
valid User Mode virtual addresses have VAddr(31) cleared attempt reference address with VAddr(31) while User mode causes Address Error exception. system maps references useg through base-bound register, settings within CAlg register virtual address determine cacheability reference.
processor operates Kernel mode when Status register contains following values:
processor enters Kernel mode whenever exception detected remains Kernel mode until Exception Return (ERET) instruction executed. That ERET instruction restores processor mode existing prior exception. Kernel mode virtual address space divided into regions differentiated VAddr(31:29), shown Figure 4.4.
FFFF FFFF
Unmapped
kseg2
0000
A000 0000
Unmapped Uncached Unmapped Cached
kseg1
kseg0
8000 0000
kuseg
Mapped
0000 0000
Note:
Default value; changed CAlg register.
Figure Kernel Mode Address Space
Table lists characteristics 32-bit kernel mode segments.
A(31)
kuseg
0x0000 0000 through 0x7FFF FFFF 0x8000 0000 through 0x9FFF FFFF 0xA000 0000 through 0xBFFF FFFF 0xC000 0000 through 0xFFFF FFFF
Gbytes (231 bytes)
A(31:29) 1002 A(31:29) 1012 A(31:30)
kseg0 kseg2 kseg1
Mbytes (229 bytes) Mbytes (229 bytes) Gbyte (232 bytes)
Table u32-bit Kernel Mode Segments
Kernel mode, when most-significant virtual address, VAddr(31), cleared, 32bit kuseg virtual address space selected. covers full bytes Gbytes) current user address space. base-bounds mechanism will translate addresses this region, CAlg register controls cacheability.
Kernel mode, when most-significant three bits virtual address 1002, 32-bit kseg0 virtual address space selected; current 229-byte (512-Mbyte) kernel physical space. References kseg0 mapped through base-bounds registers. physical address selected defined subtracting 0x8000 0000 from virtual address (physical address VA[28:0]). CAlg register controls cacheability. Reset kseg0 cacheable kseg1 not.
Kernel mode, when most-significant three bits 32-bit virtual address 1012, 32-bit kseg1 virtual address space selected. current 229-byte (512Mbyte) kernel physical space. References kseg1 mapped through base-bounds register. physical address selected defined subtracting 0xA000 0000 from virtual address (physical address 000|| VA[28:0]). default, caches disabled accesses these addresses, physical memory memory-mapped device registers) accessed directly. However, CAlg allows this changed. Reset kseg0 cacheable kseg1 not.
Kernel mode, when most-significant bits 32-bit virtual address kseg2 virtual address space selected. corresponding physical address found replacing most significant address bits with (PAddr (31:0) 000|| VAddr (28:0)). CAlg register controls cacheability.
System Control Coprocessor (CP0) implemented integral part CPU, supports memory management, address translation, exception handling, other privileged operations. contains base-bounds address addition registers shown Table 4.3. following subsections describe processor uses memory management-related registers. Each register register number, which unique number that identifies
IBase IBound DBase DBound BadVAddr Count Compare Status Cause PRId Config CAlg IWatch DWatch CacheErr TagLo ErrorEPC Instruction address space base
-Instruction address space bound Data address space base Data address space bound used used used used Virtual address address exceptions Counts every other cycle used Generate interrupt when Count Compare Miscellaneous control/status Exception/Interrupt information Exception Processor Device configuration info Cache attributes 512MB regions virtual address space Instruction breakpoint virtual address Data breakpoint virtual address used used used used used used Error checking control Error diagnostic info Cache addressing used Cache Error exception used Table Registers
following sections describe registers (shown Figure 4.5) that assigned specifically software interface with memory management. register number appears parentheses after each register name following list: IBase (CP0 register IBound DBase DBound PRId (15) CAlg (17) TagLo (28)
IBase register provides User Instruction address space Base address. Figure shows format IBase register; Table 4.4, which follows figure, describes IBase register fields. IBase Register
UIBase
Figure IBase Register
UIBase
/Added vAddr31.12 user space physical address Reserved. Reads should written Table IBase Register Field Descriptions
IBound register provides User Instruction address space Bound address. Virtual addresses greater than this value cause address error exceptions. Figure shows format IBound register; Table 4.5, which follows figure, describes IBound register fields. IBound Register
UIBound
Figure IBound Register
UIBound
/Compared vAddr30.12 user space validate address Reserved. Reads should written Table IBound Register Field Descriptions
DBase register provides User Data address space Base address. Figure shows format DBase register; Table 4.6, which follows figure, describes DBase register fields. DBase Register
UDBase
Figure DBase Register
UDBase
/Added vAddr31.12 user space physical address Reserved. Reads should written Table DBase Register Field Descriptions
DBound register provides User Data address space Bound. Figure shows format DBound register; Table 4.7, which follows figure, describes DBound register fields. DBound Register
UDBound
Figure DBound Register
UDBound
/Compared vAddr31.12 user space validate address Reserved. Reads should written Table DBound Register Field Descriptions
32-bit, read-only Processor Revision Identifier (PRId) register contains information identifying implementation revision level CP0. Figure shows format PRId register; Table describes PRId register fields. PRId Register
Figure Processor Revision Identifier Register Format
Revision number Reserved. Returns zeroes when read. Table PRId Register Fields
/Implementation numberRC4650 0x22
low-order byte (bits 7:0) PRId register interpreted revision number, highorder byte (bits 15:8) interpreted implementation number. implementation number RC4650 processor 0x22. content high-order halfword (bits 31:16) register reserved. revision number stored value form y.x, where major revision number bits minor revision number bits 3:0. revision number distinguish some chip revisions, however there guarantee that changes chip will necessarily reflected PRId register, that changes revision number necessarily reflect real chip changes. this reason, these values listed software should rely revision number PRId register characterize chip. Certain attributes, such cache size, independent implementation number.
Config register specifies various configuration options selected RC4650 processors; Table lists these options. Some configuration options, defined Config bits 31:3, hardware during reset included Config register read-only status bits software access. Figure 4.10 shows format Config register; Table 4.9, which follows figure, describes Config register fields.
Config Register
Figure 4.10 Config Register Format
/Pipeline clock ratio: processor input clock frequency multiplied processor input clock frequency multiplied processor input clock frequency multiplied processor input clock frequency multiplied processor input clock frequency multiplied processor input clock frequency multiplied processor input clock frequency multiplied Reserved Write-back data rate: WWWWWWWW word every cycle WWxWWxWWxWW words every cycles WWxxWWxxWWxxWWxx words every cycles WxWxWxWxWxWxWxWx words every cycles WWxxxWWxxxWWxxxWWxxx words every cycles WWxxxxWWxxxxWWxxxxWWxxxx words every cycles WxxWxxWxxWxxWxxWxxWxxWxx words every cycles WWxxxxxWWxxxxxWWxxxxxWWxxxx words every cycles words every cycles Write-back data rate: DDDD double word every cycle DDxDDx double words every cycles DDxxDDxx double words every cycles DxDxDxDx double words every cycles DDxxxDDxxx double words every cycles DDxxxxDDxxxx double words every cycles DxxDxxDxxDxx double words every cycles DDxxxxxDDxxxx double words every cycles DxxxDxxxDxxxDxxx double words every cycles SysAD size; bits, bits (from serial mode bits) BigEndianMem Little Endian Endian Primary I-cache Size (I-cache size 12+IC bytes). RC4650 processor this Kbytes 001). Primary D-cache Size (D-cache size 12+DC bytes). RC4650 processor this Kbytes 001). Primary I-cache line size bytes Words) Primary D-cache line size bytes Words) Reserved. Returns indicated values when read. Table Config Register Fields
(EW=1)
(EW=0)
Others
CAlg register read-write register that specifies cache algorithm each 512MB region virtual address space. CAlg initialized 0x22233333 Reset. Bits implemented, reserved future use. They read zero ignored write. Figure 4.11 shows format CAlg register; Table 4.10, which follows figure, describes CAlg register fields.
CAlg Register
Figure 4.11 CAlg Register
Cache algorithms follows: Cached, non-coherent, write-through, write-allocate Cached, non-coherent, write-through, write-allocate Uncached Cached, non-coherent, write-back, write-allocate 4-15 Reserved
/Cache algorithm 0x00000000 0x1FFFFFFF (part useg/kuseg) Cache algorithm 0x20000000 0x3FFFFFFF (part useg/kuseg) Cache algorithm 0x40000000 0x5FFFFFFF (part useg/kuseg) Cache algorithm 0x60000000 0x7FFFFFFF (part useg/kuseg) Cache algorithm 0x80000000 0x9FFFFFFF seg0) Cache algorithm 0xA00000000 0xBFFFFFFF Cache algorithm 0xC0000000 0xDFFFFFFF (part kseg2) Cache algorithm 0xE0000000 0xFFFFFFFF (part kseg2) Table 4.10 CAlg Register Field Descriptions
TagLo register 32-bit read/write register that holds primary cache parity during cache initialization, cache diagnostics, cache error processing. register written CACHE MTC0 instructions. field ignored Index Store operations. Parity computed store operation. Figure 4.12 shows register format primary cache operations. Table 4.11 lists field definitions TagLo register.
TagLo
PTagLo
PState
Rsvd
Figure 4.12 TagLo Register (P-cache) Format
PTagLo PState Rsvd Specifies primary cache state Specifies primary even parity FIFO (used internally implement FIFO refill cache) Reserved. Must written zeroes. Reserved. Must written zeroes; returns zeroes when read Table 4.11 Cache Register Fields
/Specifies physical address bits 35:12
Figure 4.13 illustrates Base-Bounds address translation process.
Virtual Address (Input) VAddr
VAddr(31)
Exception
Kernel Mode
VPN> Bounds
Exception
PAddr=000 VAddr (28:0)
PAddr (VPN+Base) offset
Cacheability
CAlg (VAddr (31:29))
C=010
Cache
Main Memory
Figure 4.13 Base-Bounds Address Translation
This chapter describes exception processing, including discussion format each exception register. chapter concludes with description each exception's cause, together with manner which processes services these exceptions. information about Floating-Point Unit exceptions, refer Chapter
processor receives exceptions from number sources, including address translation errors, arithmetic overflows, interrupts, system calls. When detects these exceptions, normal sequence instruction execution suspended processor enters Kernel mode. Refer Chapter description system operating modes. processor then disables interrupts forces execution software exception processor (called handler) located fixed address. handler save context processor, including contents program counter, current operating mode (User Kernel), status interrupts (enabled disabled). This context would saved restored when exception been serviced. When exception occurs, loads Exception Program Counter (EPC) register with location where execution restart after exception been serviced. restart location register address instruction that caused exception instruction executing branch delay slot, address branch instruction immediately preceding delay slot. registers described later chapter assist this exception processing retaining address, cause status information. description exception handling process, refer flowcharts this chapter.
This section describes registers that used exception processing. Table page lists these registers, along with their number. Each register unique identification number called register number. example, register register number remaining registers used memory management, described Chapter
Software examines registers during exception processing determine cause exception state time exception occurred. Table lists register used exception processing. description each register follows table.
IWatch DWatch BadVAddr (Bad Virtual Address) Count Compare register Status Cause (Exception Program Counter) CacheErr (Cache Error Status) ErrorEPC (Error Exception Program Counter)
Table Exception Processing Registers
IWatch register read/write register that specifies Instruction virtual address that causes Watch exception. When VADDR31.2 instruction fetch matches IVAddr this register, set, Watch exception taken. Matches that occur when take exception immediately, instead postponed until both cleared. priority IWatch exceptions just below Instruction Address Error exceptions. Figure shows format IWatch register; Table 5.2, which follows figure, describes IWatch register fields. IWatch Register
IvAddr
Figure IWatch Register Format
IvAddr
Instruction virtual address that causes watch exception (bits 31:2). IWatch disabled, IWatch enabled. reserved future use.
Note: IWatch.I cleared Reset. Table IWatch Register Fields
DWatch read/write register that specifies Data virtual address that causes Watch exception. Data Watch exception taken when VAddr 31.3 load matches DVAddr this register set, when VAddr 31.3 store matches DvAddr this register set. Matches that occur when take exception immediately, instead postponed until both cleared. priority DWatch exceptions just below Data Address Error exceptions. DWatch exceptions occur CACHE ops. Figure shows format DWatch register; Table 5.3, which follows figure, describes DWatch register fields. DWatch Register
DvAddr
Figure DWatch Register Format
DvAddr
Data virtual address that causes watch exception. DWatch disabled loads, DWatch enabled loads. DWatch disabled stores, DWatch enabled stores. reserved future use.
Note: DWatch.R DWatch.W cleared Reset. Table DWatch Register Fields
Virtual Address register (BadVAddr) read-only register that displays most recent virtual address that caused exceptions following list. processor does write BadVAddr register when Status register Address Error (e.g., unaligned access) Bounds Virtual Coherency Data Access Virtual Coherency Instruction Fetch Figure shows format BadVAddr register. BadVAddr register does save information errors, since errors addressing errors. BadVAddr Register
Virtual Address
Figure BadVAddr Register Format
Count register acts timer, incrementing constant rate-half maximum instruction issue rate-whether instruction executed, retired, forward progress made through pipeline. This register read written. written diagnostic purposes system initialization; example, synchronize processors. Figure shows format Count register.
Count Register
Count
Figure Count Register Format
Compare register acts timer, (see also Count register) maintains stable value that does change own. When value Count register equals value Compare register, interrupt IP(7) Cause register set. timer interrupt enabled boot time, interrupt will occur soon interrupt enabled. Writing value Compare register, side effect, clears timer interrupt. diagnostic purposes, Compare register read/write register. However, normal Compare register write-only. Figure shows format Compare register.
Compare Register
Compare
Figure Compare Register Format
Status register (SR) read/write register that contains operating mode, interrupt enabling, diagnostic states processor. following list describes more important Status register fields. Figure shows format Status register. Table 5.4, which follows figure, describes Status register fields.
(Cu3:.Cu0)
Figure Status Register
Controls usability each four coprocessor unit numbers. always usable when Kernel mode, regardless setting bit. usable unusable Note: MIPS ISA, longer defined valid coprocessor unit. Enables additional floating-point registers registers registers Reverse-Endian bit, valid User mode. Data cache lock, RC4650. Does prevent refills into when invalid. Does inhibit update D-cache store operations. normal operation refill into disabled Instruction cache lock, RC4650. Does prevent refills into when invalid. normal operation refill into disabled Controls location exception vectors. normal bootstrap Indicates soft reset occurred. (tag match valid state) miss indication last CACHE Invalidate, Write Back Invalidate, Write Back, Virtual primary cache. miss Contents register modify check bits caches when description register. Specifies that cache parity errors cannot cause exceptions. parity remains enabled disables parity Reserved. Read ignored writes. Interrupt Mask: controls enabling each external, internal, software interrupts. interrupt taken interrupts enabled, corresponding bits both Interrupt Mask field Status register Interrupt Pending field Cause register. IM[7:2] correspond interrupts Int[5:0] IM[1:0] software interrupts. disabled enabled Controls whether 64-bit MIPS-3 instructions used user mode. 32-bit only 64-bit enabled User Mode bit, RC4650. User Kernel (Simplification KSU, remains subject ERL, R4xxx. Error Level normal error
Exception Level normal exception Note: When going from should disabled first. This would done when preparing return from exception handler, such before executing ERET instruction. Interrupt Enable disable interrupts enables interrupts
Table Status Register Fields
Fields Status register modes access states described sections that follow. Interrupt Enable: Interrupts enabled when following conditions true: these conditions met, settings bits identify interrupt. Note: Setting delayed cycles. performing nested interrupts, reenable first. Operating Modes: following Status register settings required User, Kernel, Supervisor modes (see Chapter more information about operating modes). processor User mode when these bits follows: processor Kernel mode when these bits follows: 32-bit Virtual Addressing: RC4650 only supports 32-bit virtual addresses. ignores bits 63:32 memory addresses. Kernel Address Space Accesses: Access kernel address space allowed when processor Kernel mode. User Address Space Accesses: Access user address space allowed either Kernel User mode.
contents Status register undefined reset, except bits BEV, which distinguishes between Reset Soft Reset (Nonmaskable Interrupt [NMI]).
32-bit read/write Cause register describes cause most recent exception. Figure shows fields this register; Table 5.5, which follows figure, describes Cause register fields. 5-bit exception code (ExcCode) indicates cause most recent exception, listed Table page bits Cause register, with exception IP(1:0) bits, read-only. IP(1:0) bits used software interrupts. Cause.IV zero Reset.
Cause Register
Code
Figure Cause Register Format
Indicates whether last exception taken occurred branch delay slot. delay slot normal Reserved. Currently read must written `0'. Coprocessor unit number referenced when Coprocessor Unusable exception taken. Watch exception, indicates that DWatch register matched. other exceptions this field undefined. Watch exception, indicates that IWatch register matched. other exceptions this field undefined. Enables dedicated interrupt vector. interrupts exception vector (200) interrupts common exception vector (180) Indicates interrupt pending. interrupt pending interrupt Exception code field (see Table page Table Cause Register Fields
ExcCode
16-22 24-31
IBound DBound AdEL AdES Watch Interrupt Reserved
Instruction bound exception (replaces exception load) Data bound exception (replaces exception store) Address error exception (load instruction fetch) Address error exception (store) error exception (instruction fetch) error exception (data reference: load store) Syscall exception Breakpoint exception Reserved instruction exception Coprocessor Unusable exception Arithmetic Overflow exception Trap exception Reserved Floating-Point exception Reserved Watch exception Reserved Table Cause Register ExcCode Field
Exception Program Counter (EPC) read/write register that contains address which processing resumes after exception been serviced. synchronous exceptions, register contains either: virtual address instruction that direct cause exception, virtual address immediately preceding branch jump instruction (which occurs when instruction branch delay slot, Branch Delay Cause register set). processor does write register when Status register Figure shows format register.
Register
Figure Register Format
8-bit Error Checking Correcting (ECC) register reads writes primary-cache data parity bits cache initialization, cache diagnostics, cache error processing. parity loaded from stored TagLo register. register loaded Index Load CACHE operation. Content register are: written into primary data cache store instructions (instead computed parity) when Status register set, substituted computed instruction parity CACHE operation Fill force cache parity value Status register. Figure shows format register; Table 5.7, which follows figure, describes register fields. Register
Figure Register Format
8-bit field specifying parity bits read from written primary cache. Reserved. Must written zeroes, returns zeroes when read. Table Register Fields
32-bit read-only CacheErr register processes parity errors primary cache. Parity errors cannot corrected. CacheErr register holds cache index status bits that indicate source nature error. loaded when Cache Error exception asserted. When read response returns with parity, this exception also asserted. Figure 5.10 shows format CacheErr register. Table 5.8, which follows figure, describes CacheErr register fields. CacheErr Register
SIdx PIdx
Figure 5.10 CacheErr Register Format
Type reference instruction data Cache level error primary reserved Indicates data field error occurred error error Indicates field error occurred error error
Indicates error occurred accessing processor-managed resources, response external request. internal reference external reference Since RC4650 doesn't have external events that would look cache (which only processor-managed resource), this would under normal operating conditions. error occurred SysAD bus. Taking cache error exception sets/clears this bit. data error occurred addition instruction error (indicated remainder bits). this requires flushing data cache after fixing instruction error. Physical address 21:3 reference that encountered error. Virtual address 13:12 double word error. used with SIdx construct virtual index primary caches. Only lower bits (bits vAddr; high (bit zero. Reserved. Must written zeroes, returns zeroes when read. Table CacheErr Register Fields
SIdx PIdx
ErrorEPC register similar register, except that ErrorEPC used parity error exceptions. also used store program counter (PC) Reset, Soft Reset, nonmaskable interrupt (NMI) exceptions. read/write ErrorEPC register contains virtual address which instruction processing resume after servicing error. This address either: virtual address instruction that caused exception virtual address immediately preceding branch jump instruction, when this address branch delay slot. There branch delay slot indication ErrorEPC register. Figure 5.11 shows format ErrorEPC register.
ErrorEPC Register
ErrorEPC
Figure 5.11 ErrorEPC Register Format
This section describes processor exceptions, their causes, processing hardware, servicing handler (software). Exception types described next section.
This section gives sample exception handler operations following exception types: reset soft reset nonmaskable interrupt (NMI) cache error interrupts remaining processor exceptions When Status register either User Supervisor operating mode specified bits Status register. When processor Kernel mode. When processor takes exception, which means system Kernel mode. After saving appropriate state, exception handler typically resets back When restoring state restarting, handler sets back Returning from exception also resets (see ERET instruction Appendix following sections show sample hardware processes various exceptions, together with servicing required handler (software).
Figure 5.12 shows Reset exception process. undefined Config 00000000 undefined3 ErrorEPC SR31:23 SR19:3 SR1:0 BFC0 0000
Figure 5.12 Reset Exception Processing
Figure 5.13 shows Cache Error exception process. ErrorEPC CacheErr SR31:3 ||SR1:0 SR22 then BFC0 0200 0x100 else A000 0000 0x100 endif
What setting access boot-PROM area access main memory area
Figure 5.13 Cache Error Exception Processing
Figure 5.14 shows Soft Reset exception process.
ErrorEPC 31:23 SR19:3 SR1:0 BFC0 0000
Figure 5.14 Soft Reset Exception Processing
Figure 5.15 shows process used exceptions other than Reset, Soft Reset, NMI, Cache Error. Cause Cause15:8 ExcCode then system User Supervisor mode with current exception endif SR31:2 Cause.IV then vector=200 else vector=180 SR22 then What setting BFC0 0200 vector access uncached space else 8000 0000 vector access cached space endif
Figure 5.15 Interrupt Exception Processing
Figure 5.16 shows process used exceptions other than Reset, Soft Reset, NMI, Cache Error. Cause Cause15:8 ExcCode then system User Supervisor mode with current exception endif SR31:2 SR22 then What setting BFC0 0200 vector access uncached space else 8000 0000 vector access cached space endif
Figure 5.16 General Exception Processing (Except Reset, Soft Reset, NMI, Cache Error)
Reset, Soft Reset, exceptions always vectored location 0xBFC00000 (virtual address), corresponding kseg0. Addresses other exceptions combination vector offset base address. base address determined Status register, shown Table 5.9.
8000 0000 BFC0 0200
A000 0000 BFC0 0200
Table Exception Vector Base Addresses
Table 5.10 shows vector offset that added base address create exception address.
shown Figure 5.13, when vector base Cache Error exception changes from kseg0 (0x80000000) kseg1 (0xA0000000). When BEV=1, vector base Cache Error exception 0xBFC00200. This uncached unmapped space, allowing exception bypass cache TLB.
Cache Error Interrupt Others
0x100 0x200 0x180
Note: cause .IV=1, otherwise interrupts general vector offset. Table 5.10 Exception Vector Offsets
remainder this chapter describes exceptions order their priority, shown Table 5.11. While more than exception occur single instruction, only exception with highest priority reported.
Reset (highest priority)
Integer overflow, Trap, System Call, Breakpoint, Reserved Instruction, Coprocessor Unusable, Floating-Point Exception Bound error Data access Address Error Data access Cache Error Data access Watch Data access error Data access Interrupt (lowest priority)
Soft Reset Nonmaskable Interrupt (NMI) Bound Instruction fetch Address Instruction fetch Watch Instruction fetch Cache error Instruction fetch error Instruction fetch
Table 5.11 Exception Priority Order
general, exceptions described following sections handled ("processed") hardware, then serviced software.
This section explains Reset exception.
Reset exception occurs when ColdReset* signal1 asserted then deasserted. This exception maskable.
sections (and throughout this manual) signal name followed asterisk, such Reset*, active.
following
provides special exception vector 0xBFC0 0000 this exception. Reset vector resides unmapped uncached address space, hardware does need initialize cache process this exception. addition, processor fetch execute instructions while caches virtual memory undefined state. contents registers undefined when this exception occurs, except follows: Status register, cleared other bits undefined. Some Config Register bits initialized from boot-time mode stream. Cause register 0x22233333 IWatch.I DWatch.R=0, DWatch.W Reset exception processing shown Figure 5.12 page
Reset exception serviced initializing processor registers, coprocessor registers, caches, memory system performing diagnostic tests bootstrapping operating system
This section explains Soft Reset exception.
Soft Reset exception occurs response Reset* input signal, execution begins Reset vector when Reset* deasserted. This exception maskable.
Reset exception vector used this exception, located within unmapped uncached address space that cache need initialized process this exception. When Soft Reset occurs, Status register distinguish this exception from Reset exception. primary purpose Soft Reset exception reinitialize processor after fatal error that occurs during normal operations. Unlike NMI, cache state machines reset this exception. Like Reset, used processor state; caches normal exception vectors need properly initialized. Soft Reset preserves state caches memory system, while resetting state cache state machine. When this exception occurs, contents registers preserved exceptas follows: ErrorEPC register, which contains restart Status register, which Status register, which Status register, which Because Soft Reset abort cache operations, cache memory state undefined when this exception occurs. Soft reset exception processing shown Figure 5.14.
Soft Reset exception serviced saving current processor state diagnostic purposes, reinitializing Reset exception.
This section explains Nonmaskable Interrupt exception.
Nonmaskable Interrupt (NMI) exception occurs response falling edge pin, external write Int*[6] Interrupt register. Unlike other interrupts, this interrupt maskable; occurs regardless settings EXL, ERL, bits Status register.
Reset exception vector used this exception. This vector located within unmapped uncached address space that cache does need initialized process i
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LTC2366 - LTC2366 LTC2366 Datasheet
LM20145 - LM20145 LM20145 Datasheet
LBN06603 - LBN06603 LBN06603 Datasheet
BCR523 - BCR523 BCR523 Datasheet
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