Version October 1999 2975 Stender Way, Santa Clara, California 95

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Version October 1999
2975 Stender Way, Santa Clara, California 95054 Telephone: (800) 345-7015 TWX: 910-338-2070 FAX: (408) 492-8674 Printed U.S.A. 1999 Integrated Device Technology, Inc.
Integrated Device Technology, Inc. reserves right make changes products specifications time, without notice, order improve design performance supply best possible product. does assume responsibility circuitry described other than circuitry embodied product. Company makes representations that circuitry described herein free from patent infringement other rights third parties which result from use. license granted implication otherwise under patent, patent rights other rights, Integrated Device Technology, Inc.
LIFE SUPPORT POLICY Integrated Device Technology's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between manufacturer officer IDT. Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component components life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
logo registered trademark, BiCameral, BurstRAM, BUSMUX, CacheRAM, DECnet, Double-Density, FASTX, Four-Port, FLEXI-CACHE, Flexi-PAK, Flow-thruEDC, IDT/ IDTenvY, IDT/sae, IDT/sim, IDT/ux, MacStation, MICROSLICE, PalatteDAC, REAL8, RC3041, RC3051, RC3052, RC3081, RC36100, RC4600, RC4640, RC4650, RC4700, RC5000, RISController, RISCore, RISC Subsystem, RISC Windows, SARAM, SmartLogic, SyncFIFO, SyncBiFIFO, SPC, TargetSystem WideBus trademarks Integrated Device Technology, Inc. MIPS registered trademark, RISCompiler, RISComponent, RISComputer, RISCware, RISC/os, R3000, R3010 trademarks MIPS Computer Systems, Inc. Postscript registered trademark Adobe Systems, Inc. AppleTalk, LocalTalk, Macintosh registered trademarks Apple Computer, Inc. Centronics registered trademark Genicom, Inc. Ethernet registered trademark Digital Equipment Corp. registered trademark Corp.
Description IDT79S134 Evaluation Board
Introduction .1-1 Revision History.1-1 Overview Features.1-2 Explanation Features.1-2 Specification Summary .1-2 Part Number .1-2 RISController.1-2 On-Board Memory Capacity.1-2 Debug Monitor Flash .1-3 Serial Ports.1-3 Interrupts .1-3 Physical Dimensions .1-3 Operating Temperature .1-3 Relative Humidity .1-3 Power Supply .1-3 Flash.1-3 DRAM.1-3 SRAM .1-3 Programmable (PIO) .1-3 Interface .1-3
Installation IDT79S134 Evaluation Board
79S134 Installation .2-1 Getting started quickly .2-1 Video Terminal Requirements .2-1 Power Connector Type.2-1 RC32134 Power Connector (J29) .2-2 (Debug Boot Connector) .2-2 Memory Blocks.2-3 (Jtag Connector).2-4 Default Jumper/Switch Settings.2-5 Power (Vcc) Jumper Settings .2-6 RC32134 Power (Vcc) Jumper Settings.2-6 Switch Settings.2-7 Switch Settings.2-7 Switch Settings.2-8 System Software IDT/sim .2-9 Serial Port Video Terminal Auxiliary Port .2-9 Initialization System Start-Up.2-10 Logic Analyzer Connections .2-10
ntdatalst1col Master page style ntdatalst1col.2-14 About ntdatalst Master page style ntdatalst .2-14
Theory Operation Design Notes
Introduction .3-1 Address Space Decoding .3-1 SRAM Selected, 16Mbyte DRAM DIMM.3-1 SRAM Selected, 64Mbyte DRAM DIMM.3-2 SRAM Selected, 16Mbyte DRAM DIMM .3-2 SRAM Selected, 64Mbyte DRAM DIMM .3-2 Register Address Maps Channels .3-4 Interrupts.3-6
Schematics
Schematics .4-1
EPLD Equation
Table Table Table Table Table Table Table Table Table Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.14 Table 2.15 Table 2.16 Table 2.17 Table 2.18 Table 2.19 Table 2.20 Table 2.21 Table 2.22 Table 2.23 Table 2.24 Table 2.25 Table 2.26 Table 2.27 Table Table Table Table Table Table Table Table Table Table 3.10 Table 3.11 Table 3.12 Table 3.13 Table 3.14 Table 3.15 Table 3.16
Power Connectors .2-2 Debug Boot Connector .2-3 RC32134 Evaluation Board Memory Block Connector Locations .2-4 Jtag Connector RC32134 Slots .2-4 Cache Test/Cache Write Mode Default Settings.2-5 Programmable Signal Special/General Settings.2-5 Programmable Signals (Page 2).2-5 Power Selection Table.2-6 RC32134 Power Selection Table .2-6 Switch Settings.2-7 Boot PROM Width Selections.2-7 Boot Mode Configuration settings (Page 2).2-7 Clock Multiplier Configurations .2-8 Endianness, PLL, Slew Rate Control Configurations .2-9 J1/J2 Connector Pins Signal Descriptions.2-9 J3/J4 Connector Pins Signal Descriptions.2-10 Analyzer Connector 2-11 Analyzer Connector 2-11 Analyzer Connector 2-11 Analyzer Connector J9.2-12 Analyzer Connector J10.2-12 Analyzer Connector J11.2-12 Analyzer Connector J13.2-13 Analyzer Connector J14.2-13 Analyzer Connector J15.2-13 Analyzer Connector J17.2-14 Analyzer Connector J18.2-14 Physical Address Mapping 79S341 Board Resources .3-1 SRAM/DRAM Address Mapping, 16Mbyte DRAM DIMM.3-1 SRAM/DRAM Address Range, 64Mbyte DRAM DIMM .3-2 DRAM Address Range, 16Myte DRAM DIMM SRAM Selected .3-2 DRAM Address Range, 64Myte DRAM DIMM SRAM Selected .3-2 Controller Address Mapping .3-2 Interface Address Ranges Definitions .3-3 Register .3-3 Channel Register Mapping .3-4 Channel Register Mapping .3-4 Channel Register Mapping .3-5 Channel Register Mapping .3-5 Expansion Interrupt Controller Address Mapping .3-5 Timer Controller Address Mapping .3-6 UART Controller Address .3-6 Interrupt Assignment S134 Board.3-6
Figure Figure Figure
79S134 Evaluation Board Block Diagram.1-1 Diagram 6-Pin Power Supply Connections S134 Evaluation Board.2-2 Initial Screen Display IDT/sim Debug Monitor .2-10
IDT79RC32134 high performance system controller chip that supports IDT's RISCore32300 family. RC32134 provides direct connection between IDT's RC32364 32-bit embedded microprocessor contains system logic boot memory, main memory, I/O, PCI. also includes onchip peripherals such channels, reset circuitry, interrupts, timers UARTs. Together, RC32364 RC32134 system controller form complete subsystem embedded designs. IDT79S134 Evaluation Board provides RC32134 evaluation tool well cost effective boards through interface. 79S134 working example typical embedded host/satellite system. This board highly configurable contains hardware options various memory configurations through RC32364 RISController CPU.
32364
Data Buffer
Data Buffer DRAM
Memory
_cs[5] _cs[1] _cs[0]
DRAM
SRAM
EPROM/ Flash
SRAM Controller RC32134
ontroller
Port
Slot Slot Slot
Port
UART
Satellite (Edge Connector)
EEPROM
Port Port
Figure 79S134 Evaluation Board Block Diagram
March 1999: Initial publication. October 1999: Version 1.1. Updated schematics Chapter
Major features 79S134 Evaluation Board include: Cost effective method adding boards through interface slots (Two 3.3V) adding peripheral controllers Edge connector EPROM 1Mbyte
SRAM Mbyte SDRAM Mbytes 85C30 Controller Serial EEPROM (Mircrowire NM93C46) on-chip serial ports (16550 Compatible UARTs) External 85C30 Serial Controller digit display
IDT's S134 Evaluation Board complete working RC32364/RC32134 system intended evaluation tool software development platform that uses high performance RC32364 RISController, which based IDT's proprietary RISCore32300 core. board requires simple video terminal emulator 5-volt power supply with least current. ±12-volt power supply also needed support requirements. board contains three slots adding peripheral controllers. board contains EPROM implemented with each, using sockets. on-board EPROM memory contains IDT's flexible System Integration Manager (IDT/sim), debugging monitor that supports code downloading from host system I/O. Execution control commands include single stepping instruction tracing, memory probing, register probing, line-based assembly disassembly code. Information using IDT/sim provided separate document that available from website (www.idt.com). S134 evaluation board constructed with both through-hole surface mount devices 7/8" rectangular form factor 8-layer laminated board with standoffs intended stand-alone bench device.
IDT79S134 Evaluation Board RC32364 RISController
RISController on-chip Instruction Cache 8KByte Data Cache 2KByte shipped DRAM 32MByte EPROM 1MByte Maximum DRAM 256MByte EPROM 4MB/Flash SRAM 1Mbyte
MByte higher density EPROM 27C080 support, containing IDT/sim Controlled 85C30 controller RS232 DB9P (9-pin male) connectors video terminal connects Software configurable features Default rate: 9600 Baud, bits, parity, stop unsynchronized Rectangular form factor: 7/8" 0-30°C
5.0V Amps typical 12.0V required Cached/non-cached, single access support Non-interleaved
Basic structure DIMM socketed (sockets board) DRAM required operation Configurations allowed Only DIMM allowed Stays page between transfers
Basic structure 64-pin SIMM socket (sockets board) 15ns SRAM Zero wait-state operation block read block write Input/Output/Interrupt source Individually programmable
Revision compliant clock frequency speed synchronizer from
Must protocol type.
This chapter discusses steps required install boot 79S134 Evaluation Board. primary installation steps follows: Connecting power source This involves connecting external power supply board through J29. Connecting video display terminal This involves connecting RS232-C serial cable from video terminal board through connector Configuring jumper/switch options This involves altering reset initialization mode vector changing memory configuration. board shipped with jumpers/switches their default configurations. Running Software additional software required. Booting IDT/sim When power board turned board's IDT/sim program boots displays startup message.
79S134 board shipped ready run. Before board shipped, jumpers switches configured default settings shown tables below, general, they require further modification setup. basic requirements board are: power supply with least current
±12V power supply support requirements
video terminal typical VT100 type/ANSI terminal emulator running with 9600 baud, data bits, parity, stop bit. Typically, video terminal will have male 25-pin connector. evaluation board, RS232-C connector uses male 9-pin connector (J1) which only pins necessary, shown Table 2.15. default stand-alone mode, power board provided using standard PC/AT power supply, available from wide variety computer equipment retailers.
power supply typical compatible power supply. connector board uses 12-pin power supply connector that mates with 6-pin power supply connectors standard power supply, shown Table 2.1.
,),-
&.)/'
+12V -12V Ground Ground Ground Ground (vcc) (vcc) (vcc)
Orange Yellow Blue Black Black Black Black White
Table Power Connectors
Figure Diagram 6-Pin Power Supply Connections S134 Evaluation Board
#+,Pin number signal definitions provided Table 2.2.
TRST* TDI/DINT*
TRST* active-low signal asynchronous reset debug unit, independent processor logic. rising edge Tclk, serial input data shifted into either Instruction Data register, depending controller state. During Real Mode, this input used interrupt line stop debug unit from Real Time mode return debug unit back Time Mode (standard JTAG). serial data shifted from instruction data register falling edge Tclk. When data shifted out, tri-stated. During Real Time Mode, this signal provides non-sequential program counter processor clock division processor clock. logic signal received input decoded controller control test operation. sampled rising edge TCLK. input test clock, used shift into Boundary-Scan register cells. Tclk independent system processor clock with nominal duty cycle. Debug Boot input used during reset forces core take debug exception reset sequence instead reset exception. This enables boot from probe without having external memory working. This input signal level sensitive latched internally. This signal will also JtagBrk JTAG_Control_Register[12].
TDO/TPC
TCLK
DBugBoot
Pullup PCST0 PCST1 PCST2 Trace Status Information (STL) Pipe line Stall (JMP) Branch/Jump forms with output (BRT) Branch/Jump forms with output (EXP) Exception generated with exception vector code output (SEQ) Sequential performance (TST) Trace outputted pipeline stall time (TSQ) Trace trigger output performance time (DBM) Debug Mode During power-on reset (cold reset), PCST(2:0) serves ModeBit(2:0). Trace Status Information. Reserved Pins future expansion. During power-on reset, PCST(4:3) serves ModeBit(4:3). Processor Clock. During Real Time Mode, this signal used capture address data from signal processor clock speed, division internal pipeline. DCLK will pipeline clock. Table Debug Boot Connector
even numbered pins Ground pins.
PCST3 PCST4 DClk
DRAM Controller space maximum Mbytes that populated time with either SDRAM DIMM connector slots shown Table 2.3. Each DRAM type sockets, both capable supporting DRAM DIMMs.
SRAM SIMM Slot SDRAM DIMM Slot-1 SDRAM DIMM Slot-2 DIMM Slot-1 DIMM Slot-2
Table RC32134 Evaluation Board Memory Block Connector Locations
Table lists JTAG connector pins signals 79RC32134 slots. more operational details, refer IDT79RC32134 datasheet specifications.
PCI_TRST1* PCI_TRST* PCI_TDI1 PCI_TDI PCI_TDO1 PCI_TDO PCI_TCK1 PCI_TCK* PCI_TMS1 PCI_TMS PCI_TRST2* 79RC32134 TRST_N PCI_TDI2 79RC32134 PCI_TDO2 79RC32134 PCI_TCK2 79RC32134 PCI_TMS2 79RC32134 PCI_TRST3* PCI_TDI3 PCI_TCK3 PCI_TDO3 PCI_TMS3 Table Jtag Connector RC32134 Slots
Cache Test/Write Mode
Closed Closed
Table Cache Test/Cache Write Mode Default Settings
Jumper Strip (25) Programmable Settings
J25_1 connect (Default) J25_1 SPI_DO/SE_MW_DO/PIO8 J25_2 connect (Default) J25_2 SPI_SK/SE_MW_SK/PIO10 J25_3 connect (Default) J25_3 SPI_CS/SE_MW_CS/PIO9 J25_4 connect (Default) J25_4 SPI_DI/SE_MW_DI/PIO11 J25_5 connect (Default) J25_5= UART_TX0/PIO6 J25_6 UART_RX0/PIO7 J25_6 connect (Default) J25_7 UART_TX1/PIO4 J25_7 connect (Default) J25_8 UART_RX1/PIO5 J25_8 connect (Default)
Table Programmable Signal Special/General Settings
Jumper Strip (26) Programmable Settings
J26_1 connect, J26_7 TMR_TCO_N/PIO3 J26_1 TMR_TC0_N/ display RST_N/PIO3 (Default), J26_7 connect J26_2 connect, J26_8 TMR_TC1_N/PIO2 J26_2 display SCLK/TMR_TC1_N/PIO2 (Default), J26_8 connect J26_3 DRQA_N/PIO1 J26_3 display DATA/PIO1 (Default)
Table Programmable Signals (Page
J26_4 DRQB_N/PIO0 J26_4 display LOAD_N/PIO0 (Default) J26_5 connect J26_6 connect
Table Programmable Signals (Page
Reserved 3.3V (default) Reserved 3.3V (default) Reserved 3.3V (default) Reserved 3.3V (default) Reserved 3.3V (default)
Table Power Selection Table
,),-
Reserved 3.3V (default) Reserved 3.3V (default) Reserved 3.3V (default) Reserved 3.3V (default) Reserved 3.3V (default)
Table RC32134 Power Selection Table
SCC_DTR_REQA RC32134 DRQ0 SCC_W_REQA RC32134 DRQ0 SCC_DTR_REQB RC32134 DRQ1 SCC_W_REQB RC32134 DRQ1 PULL (Default)
Clock divide
Clock divide (Default)
Table 2.10 Switch Settings
(BPROMW0) (BPROMW1) (BPROMW0) (BPROMW1) (BPROMW0) (BPROMW1) (BPROMW0) (BPROMW1)
closed closed open closed closed open open open Reserved 32-bit Boot PROM width 16-bit Boot PROM width 8-bit Boot PROM width (Default)
Table 2.11 Boot PROM Width Selections
(Reserved) Open (Flash Memory) (Unused) Closed (PCI_Host_mode) (BRHEA0) (BRHEA1) (BRHEA0) (BRHEA1) Open Closed Closed Open Closed Boot from PCI. EEPROM pre-load configuration registers. (Default) Boot from RC32134 memory controller. (Default) host mode. (Default) Satellite mode Closed Disable FLASH Enable EPROM. (Default) Enable FLASH Memory.
Table 2.12 Boot Mode Configuration settings (Page
(BRHEA0) (BRHEA1) (BRHEA0) (BRHEA1)
Closed Open Open Open Idle reset. RC32134 does supply boot-code control. (Default) Reserved (Default)
Table 2.12 Boot Mode Configuration settings (Page
These switch settings control Mode-bit features other miscellaneous user selectable features implemented during Power-on Cold reset stages. Switch 4-1, implement clock multiplier used generate pipe-line frequency multiplied input clock, Mclk.
(MCLKX0) (MCLKX1) (MCLKX2) (MCLKX0) (MCLKX1) (MCLKX2) (MCLKX0) (MCLKX1) (MCLKX2) (MCLKX0) (MCLKX1) (MCLKX2) (MCLKX0) (MCLKX1) (MCLKX2) (MCLKX0) (MCLKX1) (MCLKX2) (MCLKX0) (MCLKX1) (MCLKX2) (MCLKX0) (MCLKX1) (MCLKX2)
Closed Closed Closed Open Closed Closed Closed Open Closed Open Open Closed Closed Closed Open Open Closed Open Closed Open Open Open Open Open Table 2.13 Clock Multiplier Configurations Reserved Clock multiplier Clock multiplier Clock multiplier Clock multiplier Clock multiplier Clock multiplier Clock multiplier (Default)
Open Endianness Reserved Reserved Timer Interrupt Reserved Closes Closed Closed Closed Open Open
Endian (Default) Little Endian (Default) (Default) Enabled (Default) Disabled (Default)
Table 2.14 Endianness, PLL, Slew Rate Control Configurations
0)1.
EPROMs 79S134 contain IDT's System Integration Manager (IDT/sim). IDT/sim software boot PROM debug monitor that provides functions downloading software integrating hardware with software. Using IDT/sim, software downloaded onto board from SPARCstationor PC/AT personal computer. Drivers added easily using Cross Development Software IDT/kit, IDT/sim source code acquired support other devices change addresses their specific application: example, change from big-endian little-endian addressing. S134 board's default configuration big-endian addressing. copy IDT/sim obtained through your local sales representative.
79S134 system board four RS232 serial port connectors with assignments shown Table 2.15 Table 2.16. console port board DB9P connector designated J1/J31 must data rate 9600 baude with bits data, parity bit, stop bit. J2/J4 auxiliary port also DB9P connector used functions such down loading software from SPARCstationTM.
Signal connection (Output) (Input) connection Ground connection connection connection connection
Signal connection (Output) (Input) connection Ground connection connection connection connection
Table 2.15 J1/J2 Connector Pins Signal Descriptions
Based (for external/internal UART) console will either respectively.
Signal connection (Output) (Input) connection Ground connection connection connection connection
Signal connection (Output) (Input) connection Ground connection connection connection connection
Table 2.16 J3/J4 Connector Pins Signal Descriptions
System start-up performed turning power supply power board already been supplied, then pressing reset button will reinitialize board. board's three displays indicate that power been successfully applied indicates status reset, follows: indicates that power (Green)
indicates that Cold Reset active (Red) indicates that 3.3V power supply (Yellow)
Once started, IDT/ automatically boots sizes internal cache main memory. console connected serial port message indicating cache memory sizes-similar shown Figure 2.2-will appear along with first command line prompt. more information commands, refer IDT/ User/Developer's Manual. Note: Future upgrades will assigned different version number date. starting address free memory space differ slightly from example shown Figure 2.2.
System Integration Manager Ver. May, 1995 Copyright 1994, 1995 Integrated Device Technology, Inc. help enter Memory size: 1048576 (0x100000) bytes Icache size: 4096 (0x1000) bytes Dcache size: 1024 (0x400) bytes User Memory Space 0xa00082dc-0xa00ffffc CPU: RC32364 Default baud rate: 9600 Register: 32-bit ENDIAN: <IDT> Figure Initial Screen Display IDT/sim Debug Monitor
8#56, J17, used connect directly Logic Analyzer. numbers signal descriptions each connector listed following tables.
RHEA_ clk1 CPU_AD0 CPU_AD1 CPU_AD2 CPU_AD3 CPU_AD4 CPU_AD5 CPU_AD6
CPU_AD7 CPU_AD8 CPU_AD9 CPU_AD10 CPU_AD11 CPU_AD12 CPU_AD13 CPU_AD14 CPU_AD15
Table 2.17 Analyzer Connector
N.C. N.C. RHEA_clk2 CPU_AD16 CPU_AD17 CPU_AD18 CPU_AD19 CPU_AD20 CPU_AD21 CPU_AD22
CPU_AD23 CPU_AD24 CPU_AD25 CPU_AD26 CPU_AD27 CPU_AD28 CPU_AD29 CPU_AD30 CPU_AD31
Table 2.18 Analyzer Connector
N.C. N.C. RHEA_CLK3 CPU_ADDR2 CPU_ADDR3 CPU_ALE CPU_WR_N CPU_CIP_N CPU_ACK_N CPU_LAST
CPU_BE0 CPU_BE1 CPU_BE2 CPU_BE3 CPU_BERR_N CPU_CRST_N RH_RST_N CPU_BREQ_N CPU_BGNT_N
Table 2.19 Analyzer Connector
RH_INTR3_N R_RAS0 R_RAS1 R_RAS2 R_RAS3 R_CAS0 R_CAS1
R_CAS2 R_CAS3 R_245OE_N R_WE_N R_CKE R_SDCAS_N R_SDRAS_N RH_TC1_N RH_TC0_N
Table 2.20 Analyzer Connector
RH_DRQ1 RH_DRQ0 RH_RX0 RH_RX1 RH_TX0 RH_TX1 RH_TRST_N
RH_TDO RH_TDI RH_TMS RH_TCK R_MEM_WE0_N R_MEM_WE1_N R_MEM_WE2_N R_MEM_WE3_N R_MEM_OE_N
Table 2.21 Analyzer Connector
CPU_MCLK R_MEM_CS0_N R_MEM_CS1_N R_MEM_CS2_N R_MEM_CS3_N R_MEM_CS4_N R_MEM_CS5_N R_MEM_WAIT_N
R_MEM_245_OE_N CPU_DT/R_N RH_SE_DI RH_SE_DO RH_SE_CS RH_SE_SK
Table 2.22 Analyzer Connector
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6
PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15
Table 2.23 Analyzer Connector
PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22
PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
Table 2.24 Analyzer Connector
R_PCI_CLK PCI_C/BE3# PCI_C/BE2# PCI_C/BE1# PCI_C/BE0# PCI_REQ1# PCI_REQ2# PCI_REQ3#
PCI_GNT1# PCI_GNT2# PCI_GNT3# PCI_LOCK# PCI_PAR PCI_RST# PCI_TRDY# PCI_IRDY# PCI_STOP#
Table 2.25 Analyzer Connector
RH_ADS2 RH_ADS3 RH_ADS4 RH_ADS5 RH_ADS6 RH_ADS7 RH_ADS8
RH_ADS9 RH_ADS10 RH_ADS11 RH_ADS12 RH_ADS13 RH_ADS14 RH_ADS15 RH_ADS16 RH_ADS17
Table 2.26 Analyzer Connector
RH_ADS18 RH_ADS19 RH_ADS20 RH_ADS21 RH_ADS22 PCI_FRAME# PCI_PERR#
PCI_SERR# PCI_DEVSEL#
Table 2.27 Analyzer Connector
09#0
boot-time mode control interface initializes fundamental processor modes. boot-time mode control interface serial interface that operates very frequency (MasterClock divided 256).
09#0
columns same information bottom this page. Note: Make sure "for Tech Support:" information lower right corner this page appropriate particular data sheet creating.
This chapter provides information functional operation IDT79S134 evaluation board RC32134 system controller chip. detailed schematics refer Chapter detailed equations, refer Chapter
physical addresses S134 board's resources listed tables that follow. EPROM/FLASH, SRAM Serial Communication Controller subsystems accessed through selection Memory chipselects[0,1,5]. memory_I/O controller includes EPROM/FLASH subsystem, Serial SRAM subsystems. EPROM/FLASH module accessible through mem_chipselect[0] (see Table 3.16). Selection between EPROM FLASH memory space achieved through Switch shown Table 2.9. SRAM memory space Mbytes accessed through mem_chipselec[1] (see Table 3.16). 85C30 controller interfaces RS232 connectors located fixed address space listed Table 3.1, which selected through mem_chipselect[5].
Flash SRAM DRAM (EDO/SDRAM) Bank size Bank size (85C30) 79RC32134 Internal Registers
1FC0_0000 1FFF_FFFF 1FC0_0000 1FDF_FFFF 0000_0000 000F_FFFF
0080_0000 00FF_FFFF 0100_0000 017F_FFFF 1600_0000 17FF_FFFF 1800_0000 1BFF_FFFF
Table Physical Address Mapping 79S341 Board Resources
DRAM Controller space maximum Mbytes that populated time with either SDRAM DIMM. Each DRAM type sockets, both capable supporting DRAM DIMMs. When SRAM option selected, SRAM DRAM address locations ranges change shown Table 3.2, Table 3.3. When SRAM selected, address mappings shown Table Table 3.5.
From 0000_0000
000F_FFFF
From 0080_0000
027F_FFFF
Banks 0080_0000 0100_0000 0180_0000 0200_0000
Banks FF80_0000
Table SRAM/DRAM Address Mapping, 16Mbyte DRAM DIMM
0000_0000
000F_FFFF
0200_0000
09FF_FFFF
0200_0000 0400_0000 0600_0000 0800_0000
FE00_0000
Table SRAM/DRAM Address Range, 64Mbyte DRAM DIMM
0000_0000
01FF_FFFF
0000_0000 0080_0000 0100_0000 0180_0000
FF80_0000
Table DRAM Address Range, 16Myte DRAM DIMM SRAM Selected
0000_0000
007FF_FFFF
0000_0000 0200_0000 0400_0000 0600_0000
FE00_0000
Table DRAM Address Range, 64Myte DRAM DIMM SRAM Selected
Controller supports either 12-bit general purpose discrete specific peripheral functions. general purpose discrete pins, controller supports functions such 4-digit display micro wire serial EEPROM. Specific peripheral functions such on-chip UART data pins, SPI, timers also supported. Each these functions implemented through Jumpers shown Table 2.4. address controller shown Table 3.6.
From 1800_0600
1800_0608
Table Controller Address Mapping
interface resources include control core that provides master target controller that uses transmit receive FIFO sizes words. interface core provides arbitration selection, external request grant modes, internal RC32134 arbiter mode with fixed round robin priority selections, mailbox registers, software programmable endianness (selectable memory block). address mapping these registers shown Table 3.8. internal address interface shown Table 3.7.
1800_2000 1880_0000 18C0_0000 1FC0_0000 4000_0000 6000_0000
1800_2FFF 188F_FFFF 18FF_FFFF 1FFF_FFFF 5FFF_FFFF 7FFF_FFFF
Internal registers (4KB) Space (1MB) Memory space (4MB) (for non-pci boot reset option) Memory space (4MB) (for boot reset option) Memory Space (512MB) Memory Space (512MB)
Table Interface Address Ranges Definitions
1800_05B0 1800_05B4 1800_05B8
Controller Interrupt Pending Register Controller Interrupt Mask Register Controller Interrupt Clear Register
1800_05C0 1800_05C4 1800_05C8
Satellite Mode Mailbox Interrupt Pending Register Satellite Mode Mailbox Interrupt Mask Register Satellite Mode Mailbox Interrupt Clear Register
1800_05D0 1800_05D4 1800_05D8
Mailbox Interrupt Pending Register Mode Mailbox Interrupt Mask Register Mailbox Interrupt Clear Register
1800_20B0 1800_20B8 1800_20C0 1800_20C8 1800_20E0 1800_20E8 1800_2100 1800_2CF8 1800_2CFC
Memory Space Base Register Memory Space Base Register Memory Space Base Register Space Base Register Arbitration Register Host Memory Space Base Register Host space Base Register Configuration Address Register Configuration Data Register Table Register
Four general purpose channels1 move data between source destination resources such system memory, external devices (8-,16-,or 32-bit devices treated memory-mapped word-aligned devices). Using flexible, memory-based descriptor structure, four channels efficiently supports "scatter/gather" capability. RC32134 supports byte, half-word (16-bit), word, quad-word burst transfers that crossover quad-word boundaries automatically split into single-word transfers until quad-word boundary reached. controller also automatically prevents burst transfers from crossing page boundaries supports little- big-endian data conversions. restrictions include: When source destination address constant devices), must word aligned.
supported internal UART.
following transfers supported: Source incremented destination decremented
Source decremented destination incremented.
Additional information operations located RC32134 hardware user's manual.
1800_1400
Configuration Register Base Descriptor Register Current Address Register Status/Block Size Register Source Address Register Destination Address Register Nest Descriptor Address Register
Base Offset
Table Channel Register Mapping
1800_1400
Configuration Register Base Descriptor Register Current Address Register Status/Block Size Register Source Address Register Destination Address Register Nest Descriptor Address Register
Base Offset
Table 3.10 Channel Register Mapping
channels have DMA_RDY pins used perform transfers with slow devices.
1800_1900
Configuration Register Base Descriptor Register Current Address Register Status/Block Size Register Source Address Register Destination Address Register Nest Descriptor Address Register
Base Offset
Table 3.11 Channel Register Mapping
1800_1900
Configuration Register Base Descriptor Register Current Address Register Status/Block Size Register Source Address Register Destination Address Register Nest Descriptor Address Register
Base Offset
Table 3.12 Channel Register Mapping
Expansion Interrupt Controller extends CPU's interrupt control collating RC32134 generated interrupts into single interrupt. When general purpose interrupt received, Interrupt Service Routine (ISR) first saves registers, checks Cause Register then checks Pending Interrupt Register. pending interrupt from RC32134, then checks Expansion Interrupt Controller Pending Interrupt Register. After treating/noting interrupt condition, resets pending interrupt writing corresponding Expansion Interrupt Clear Register. then exit restoring register executing instruction. register address mapping Expansion Interrupt Controller shown Table 3.13.
From 1800_0500
1800_05e8
Table 3.13 Expansion Interrupt Controller Address Mapping
RC32134 eight on-chip Timers: Three general purpose timers five timers that optionally dedicated Watchdog, time-out, time-out, DRAM refresh, WarmReset. Beginning from zero, these eight system timers count each system clock, timing after reaching programmable compare value resetting zero automatically. Uses these timers include real-time clock, cascaded real-time clock time-slice clock. register address mapping Timer controller shown Table 3.14. Additional information functional aspects these timers located RC32134 hardware user's manual.
From 1800_0700
1800_0778
Table 3.14 Timer Controller Address Mapping
16550 UARTs enhanced version 16450 UART. Functionally same 16450 power-up, these UARTs into 16550 mode, which then relieves software overhead. This feature allows execution 16450 16550 compatible software. sets 16-byte buffers enabled during 16550 mode: receive data path transmit data path. read UART status time during operation. Status information includes type condition transfer operation, well error condition (parity, overrun, framing, break interrupt). baud rate generator included that divides down system clock 65K. baud rate generator provides clock driving transmitter receiver logic. UART controller provides fully programmable serial characteristics such 8-bit characters; even, parity generation detection; 1-1/2 stop generation. register address mapping UART Controller shown Table 3.15.
From 1800_0800
1800_083C
Table 3.15 UART Controller Address
Both on-board interface interrupts assigned shown Table 3.16.
INT0* INT1* INT2* INT3 INT4* INT5* NMI*
(85C30) INTR. INTA# INTB# 79RC32134 INTR. INTC# INTD# N.C. (Unused)
Table 3.16 Interrupt Assignment S134 Board
66MHZOSC CPU_DCLK
744-083-R330 CPU_PCST[4] CPU_PCST[3] CPU_PCST[2] CPU_PCST[1]
744-083-R220 OSC66MR VCC3.3 W40C949 DSELA DSELB DSELC DSELD TCLK_SEL TCLK0 TCLK1 PCLK PCLK# PCLK_SEL DSELA QA149 QB046 QC037 QC135 QD016 QD118 QD424 QD528 22-OHM 744-083-R220 RN14 22-OHM 1K(R8) RP21 SDCLK4 SDCLK5 SDCLK6 SDCLK7 CLKA0R CLKA1R CLKB0R CLKB1R CLKB2R CLKC0R 744-083-R220 CLKC1R CLKC2R CLKC3R CLKD0R CLKD1R CLKD2R CLKD3R CLKD4R CLKD5R CPU_MCLK EPLD_CLK RHEA_CLK RHEA_CLK1 RHEA_CLK2 RHEA_CLK3 SDCLK2 SDCLK3 VCC3.3
OSC66M SDCLK0 SDCLK1 CONN26
22-OHM
33-OHM 744-083-R330
CPU_PCST[0] CPU_TDI/DINT_N
RN10 33-OHM CPU_DBUGBOOT CPU_TCLK CPU_TMS CPU_TDO/TPC
DSELB DSELC DSELD MR/TRI
22-OHM 744-083-R220
LT1085CT-3.3 VOUT
RSTINIT
VCC3.3
4.7K
RESIN SENSE
RST_0 TL7705B
RST_1
PWRLEDPUP
Tantalum
Aluminum
10UF_50V
PCI_CLK0 PCI_CLK1 PCI_CLK2
PCI_CCLK
744-083-R220
10UF_50V
LED-GRN
0.1UF_50V
LED-ELO
66MHZOSC
22UF_20V
PCI_CLK3
22-OHM
PWR-CON12
VCC3.3 0.1UF_50V 0.1UF_50V 0.1UF_50V 22UF_10V 22UF_10V 22UF_10V 0.1UF_50V 22UF_20V Tantalum 220UF_50V Tantalum 22UF_20V
CY27
CY34
CY33
INTEGRATED DEVICE TECHNOLOGY, INC.
CLOCK GEN, RESET
SIZE
CRONUS_RHEA
SHEET
DATE: 3-23-1998_14:22
CPU_CRST_N CPU_RST_N CPU_MCLK 22UF_10V
0.10UF-50V
CPU_ACK_N CPU_BERR_N CPU_RTRY_N 0.10UF-50V
0.10UF-50V
0.10UF-50V CPU_BREQ_N CPU_BGNT_N
0.10UF-50V
0.10UF-50V VCC_CPU
CPU_OSCMD0 CPU_OSCMD1 CPU_OSCMD2 22UF_10V
0.10UF-50V CX12
CX11 0.10UF-50V
0.10UF-50V
CPU_NMI_N
CX10 0.10UF-50V
0.10UF-50V
0.10UF-50V VCC_CPU
CPU_PCST[0:4]
CPU_PCST0 CPU_PCST1 1K,1/8W
CPU_PCST0 CPU_WD0 CPU_PCST1 CPU_WD1 CPU_PCST2 CPU_PCST3
CPU_PCST2 CPU_PCST3 CPU_PCST4
CPU_PCST4
CPU_CIP_N CPU_TRST_N
CPU_LAST
CPU_CTSTMODE CPU_CWRDSBL CPU_WR_N
INTEGRATED DEVICE TECHNOLOGY, INC.
CPU_TQFP
CPU_PGA
SIZE
CRONUS_RHEA
SHEET
DATE: 3-23-1998_14:22
CPU_AD[0:31] R_MEM_CS0_N CPU_BE[0:3] R_MEM_CS1_N R_MEM_CS2_N R_MEM_CS3_N R_MEM_CS4_N R_MEM_CS5_N
CPU_AD10
CPU_AD11
CPU_AD12
CPU_AD13
CPU_AD14
CPU_AD15
CPU_AD16
CPU_AD17
CPU_AD18
CPU_AD19
CPU_AD20
CPU_AD21
CPU_AD22
CPU_AD23
CPU_AD24
CPU_AD25
CPU_AD26
CPU_AD27
CPU_AD28
CPU_AD29
CPU_AD30
CPU_ACK_N CPU_ADDR2 CPU_ADDR3 CPU_ALE
CPU_AD31
CPU_AD0
CPU_AD1
CPU_AD2
CPU_AD3
CPU_AD4
CPU_AD5
CPU_AD6
CPU_AD7
CPU_AD8
CPU_BE0
CPU_BE1
CPU_BE2
CPU_BE3
CPU_AD9
CPU_ACK_N
CPU_BE0_N
CPU_BE1_N
CPU_BE2_N
CPU_BE3_N
R_MEM_WE[0:3]_N CPU_AD10 CPU_AD11 CPU_AD12 CPU_AD13 CPU_AD14 CPU_AD15 CPU_AD16 CPU_AD17 CPU_AD18 CPU_AD19 CPU_AD20 CPU_AD21 CPU_AD22 CPU_AD23 CPU_AD24 CPU_AD25 CPU_AD26 CPU_AD27 CPU_AD28 CPU_AD29 CPU_AD30 CPU_AD31 MEM_CS0_N MEM_CS2_N MEM_CS4_N MEM_CS1_N MEM_CS3_N MEM_CS5_N CPU_AD0 CPU_AD1 CPU_AD2 CPU_AD3 CPU_AD4 CPU_AD5 CPU_AD6 CPU_AD7 CPU_AD8 CPU_AD9 MEM_WE3_N MEM_WE2_N MEM_WE1_N MEM_WE0_N MEM_OE_N MEM_WAIT_N MEM_245_OE_N MEM_ADS2 RH_ADS2 R_MEM_WE3_N R_MEM_WE2_N R_MEM_WE1_N R_MEM_WE0_N R_MEM_OE_N R_MEM_WAIT_N R_MEM_245_OE_N
CPU_ALE
CPU_ADS3
CPU_WR_N CPU_CIP_N CPU_LAST CPU_BERR_N RHEA_CLK CPU_CRST_N RH_RST_N CPU_BREQ_N CPU_BGNT_N RH_INTR3_N CPU_DT/R_N
CPU_WR_N CPU_CIP_N CPU_LAST_N CPU_BERR_N CPU_MCLK_N CPU_CRST_N
CPU_ADS2
MEM_ADS3 CPU_RST_N MEM_ADS4 CPU_BRQ_N MEM_ADS5 CPU_BGT_N MEM_ADS6 CPU_INTR3_N MEM_ADS7 CPU_DT_R_N MEM_ADS8 MEM_ADS9 RAS/CS0_N MEM_ADS10 RAS/CS1_N MEM_ADS11 RAS/CS2_N MEM_ADS12 RAS/CS3_N CAS/BEMSK0_N CAS/BEMSK1_N MEM_ADS15 CAS/BEMSK2_N MEM_ADS16 CAS/BEMSK3_N MEM_ADS17 SD_245_OE_N MEM_ADS18 SD_WE_N MEM_ADS19 SD_CKE SD_CAS_N MEM_ADS21 SD_RAS_N MEM_ADS22 MEM_ADS13 MEM_ADS14
RH_ADS3 RH_ADS4 RH_ADS5 RH_ADS6
RH_ADS7 RH_ADS8 RH_ADS9 RH_ADS10
R_RAS0 R_RAS1 R_RAS2 R_RAS3 R_CAS0 R_CAS1 R_CAS2 R_CAS3 R_245OE_N R_WE_N R_CKE R_SDCAS_N R_SDRAS_N RH_TC1_N RH_TC0_N RH_DRQ1 RH_DRQ0
RH_ADS11 RH_ADS12 RH_ADS13 RH_ADS14
RHEA_CHIP
RH_ADS15 RH_ADS16 RH_ADS17 RH_ADS18
RH_ADS19 RH_ADS20 RH_ADS21 RH_ADS22 RH_ADS[2:22]
MEM_ADS20
TMR_TC/GATE1_N TMR_TC/GATE0_N DMA_RDY/DONE1_N DMA_RDY/DONE0_N
(pio2) PCI_FRAME_N (pio3) PCI_SERR_N (pio0) PCI_PERR_N (pio1) PCI_STOP_N PCI_IRDY_N
PCI_FRAME# PCI_SERR# PCI_PERR# PCI_STOP# PCI_IRDY# PCI_TRDY# PCI_RST# PCI_PAR PCI_LOCK# R_PCI_CLK PCI_DEVSEL#
RH_RX0 RH_TX0 RH_RX1 RH_TX1
UART_RX0 UART_TX0 UART_RX1 UART_TX1
(pio6) (pio7) (pio4) (pio5)
PCI_TRDY_N PCI_RST_N PCI_PAR PCI_LOCK_N PCI_CLK PCI_DSEL_N
RH_SE_DI RH_SE_DO RH_SE_CS RH_SE_SK
SE_DI (pio8) JTAG_TRST_N PCI_CBE3_N PCI_CBE2_N PCI_CBE1_N PCI_CBE0_N PCI_REQ0_N PCI_REQ1_N PCI_REQ2_N PCI_GNT0_N PCI_GNT1_N SE_DO (pio11) SE_CS (pio9) SE_SK (pio10) PCI_GNT2_N
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_GNT1#
PCI_GNT2#
RH_TRST_N PCI_REQ1# PCI_REQ2# PCI_C/BE3# PCI_C/BE2# PCI_C/BE1# PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 RH_TDO RH_TDI RH_TMS RH_TCK PCI_C/BE0# PCI_REQ3#
PCI_GNT3#
PCI_GNT[1:3]# PCI_REQ[1:3]# PCI_C/BE[0:3]# PCI_AD[0:31]
VCC_RHEA
INTEGRATED DEVICE TECHNOLOGY, INC.
0.10UF-50V CX13 0.10UF-50V CX14 0.10UF-50V CX15 0.10UF-50V CX16 0.10UF-50V CX17 22UF_10V CY14
RHEA_CHIP
SIZE
CRONUS_RHEA
SHEET
DATE: 3-23-1998_14:23
CPU_AD[0:31] VCC3.3
MEM_D[0:31] VCC3.3 CPU_AD0 DM_D[0:31] CPU_AD0 CPU_AD1
CPU_AD0
MEM_D0 MEM_D1
DM_D0 DM_D1
CPU_AD1 CPU_AD2
RP16 10K(R8)
CPU_AD1 CPU_AD2 CPU_AD2 CPU_AD3 CPU_AD3 CPU_AD4
163245C
MEM_D2 MEM_D3
164245T
22UF_10V
DM_D2 DM_D3 DM_D4
CPU_AD3 CPU_AD4
MEM_D4 MEM_D5
CY19 22UF_10V
CPU_AD4 CPU_AD5 CPU_AD5 CPU_AD6 CPU_AD6 CPU_AD7
CPU_AD5
DM_D5
CPU_AD6
MEM_D6 MEM_D7
DM_D6
CPU_AD7
CY18 CX56 0.10UF-50V
CPU_AD7
DM_D7
CX55 0.10UF-50V VCC3.3
CPU_AD8 CPU_AD8 CPU_AD8
DM_D8
MEM_D8 MEM_D9 MEM_D10 CX54 0.10UF-50V
CPU_AD9 CPU_AD10
CPU_AD9
CPU_AD9 CPU_AD10 CPU_AD11
DM_D9 DM_D10 DM_D11
RP17 10K(R8)
CPU_AD10
CPU_AD11
MEM_D11
164245T
CPU_AD11 CPU_AD12 CPU_AD13
CPU_AD12
163245C
CPU_AD12 CPU_AD13 CPU_AD14
MEM_D12 MEM_D13 MEM_D14
DM_D12
CX53 0.10UF-50V
CPU_AD13
DM_D13 DM_D14
CPU_AD14
CPU_AD14 CPU_AD15
CPU_AD15
MEM_D15 CX52 0.10UF-50V
CPU_AD15
DM_D15
CX51 0.10UF-50V VCC3.3
CPU_AD16
MEM_D16
CX50 0.10UF-50V
CPU_AD16 CPU_AD16 CPU_AD17 CPU_AD17 CPU_AD18 CPU_AD18
DM_D16 DM_D17 DM_D18 DM_D19
163245C
CPU_AD17
MEM_D17 MEM_D18
CPU_AD18 CPU_AD19
164245T
MEM_D19 MEM_D20
RP14 10K(R8)
CPU_AD19 CPU_AD19 CPU_AD20 CPU_AD20 CPU_AD21 CPU_AD21 CPU_AD22 CPU_AD22
CPU_AD20 CPU_AD21
DM_D20 DM_D21 DM_D22 DM_D23
MEM_D21
CPU_AD22
MEM_D22 MEM_D23
CPU_AD23
CPU_AD23 CPU_AD23
VCC3.3
CPU_AD24
MEM_D24
CPU_AD25 CPU_AD24 CPU_AD24
MEM_D25 MEM_D26 MEM_D27
DM_D24
CPU_AD26 CPU_AD27
164245T
CPU_AD25
CPU_AD25 CPU_AD26 CPU_AD27
DM_D25 DM_D26 DM_D27
RP15 10K(R8)
CPU_AD26
CPU_AD28
MEM_D28
CPU_AD27
CPU_AD28
CPU_AD28
163245C
CPU_AD29 CPU_AD30
MEM_D29 MEM_D30 MEM_D31
DM_D28
CPU_AD29
CPU_AD29
DM_D29 DM_D30
CPU_AD31
CPU_AD30
CPU_AD30 CPU_AD31
22UF_10V
CPU_AD31
DM_D31
22UF_10V
R_245OE_N
CX106 0.10UF-50V
CPU_DT/R_N R_MEM_245_OE_N
CX105 0.10UF-50V
INTEGRATED DEVICE TECHNOLOGY, INC.
Keep
these
resistor
network
nearer
processor
SIZE
DATA
BUFFERS
DAMPING
RESISTORS
CRONUS_RHEA
SHEET
DATE: 3-23-1998_14:23
INIT*3 INT*2 BOOTPROM WIDTH BITS BITS BITS RESERVED
INT*1 RESERVED INT*0 Timer GNT* PCST4 RESERVED PCST3 PCST2 CLOCK PCST1 MULTIPLIER MASTER PCST0 CLOCK
RESERVED
Enable Disable
LITTLE
GENERATE PCLOCK MULTIPLY MULTIPLY MULTIPLY MULTIPLY MULTIPLY MULTIPLY MULTIPLY RESERVED
MODE
BITS
RSTINIT CPU_INT[0:5]
EPLD_CLK CPU_PCST0 CPU_PCST1 CPU_PCST2 CPU_PCST3 CPU_PCST4 RP19 10K(R8)
CPU_PCST[0:4]
CPU_INT0
CPU_INT1
CPU_INT2
CPU_INT3
CPU_INT4
CPU_INT5
CPU_BGNT_N CPU_NMI_N
IO64
IO62
IO61
IO52
IO60
IO59
IO58
IO57
IO56
IO55
IO53
GCLK
IO63
IO54
MODEIN0 MODEIN1 MODEIN2 MODEIN3 MODEIN4 MODEIN5 MODEIN6
GCLRN
IO51 IO50 IO49 IO48 IO47 IO46
CPU_CRST_N CPU_RST_N R_MEM_WAIT_N SRAM_WE_N SRAM_CS0_N SRAM_CS1_N SRAM_CS2_N SRAM_CS3_N RH_ADS22 RH_ADS21 RH_ADS20 R_MEM_WE3_N R_MEM_WE2_N R_MEM_WE1_N R_MEM_WE0_N RH_INTR3_N
MODEIN7 MODEIN8
IO10 IO11 IO12 EPM7128E_84-7
IO45 IO44 IO43 IO42 IO41 IO40 IO39 IO38 IO37 IO36 IO35 IO34 IO33
MODEIN9
R_BOOT19
OE1N
IO20
IO21
IO22
IO23
IO24
IO25
IO26
IO27
IO28
IO29
IO30
IO31
IO32
10K(R8) RP20 FLASH_N ROMSZ R_MEM_OE_N RH_ADS19 PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# SCC_INT_N MEM_D[0:7]
MEM_D0
MEM_D1 MEM_D2 MEM_D3 MEM_D4 MEM_D5 MEM_D6 MEM_D7
OE2N
IO13 R_BOOT20 IO14 R_BOOT21 IO15 R_BOOT22 IO16 IO17 IO18 IO19
744-083-R220 R_RAS0 R_RAS1 R_RAS2 R_RAS3 RN11 22-OHM 744-083-R220 DR_RAS0 DR_RAS1 DR_RAS2 DR_RAS3
R_MEM_CS5_N R_MEM_CS4_N R_MEM_CS3_N R_CAS2 RH_RST_N R_CAS3 R_MEM_CS2_N R_MEM_CS1_N R_MEM_CS0_N RH_ADS[2:22] 744-083-R220 RH_ADS2 RH_ADS3 RH_ADS4 RH_ADS5 22-OHM 744-083-R220 RH_ADS6 RH_ADS7 RH_ADS8 RH_ADS9 22-OHM DRAM_ADS6 DRAM_ADS7 DRAM_ADS8 DRAM_ADS9 RH_ADS14 RH_ADS15 DRAM_ADS2 DRAM_ADS3 DRAM_ADS4 DRAM_ADS5 RH_ADS10 RH_ADS11 RH_ADS12 RH_ADS13 744-083-R220 R_CKE 22-OHM 744-083-R220 0.10UF-50V CX71 0.10UF-50V CX70 0.10UF-50V CX69 0.10UF-50V CX68 22UF_10V 22UF_10V 22-OHM DRAM_ADS14
R_CAS0 R_CAS1
RN12 22-OHM 744-083-R220
DR_CAS0 DR_CAS1 DR_CAS2 DR_CAS3
DRAM_ADS[2:15]
R_WE_N
RN13 22-OHM
DR_WE_N DR_CKE DR_SDRAS_N DR_SDCAS_N
DRAM_ADS10 R_SDRAS_N DRAM_ADS11 R_SDCAS_N DRAM_ADS12 DRAM_ADS13
INTEGRATED
DEVICE
MODE
TECHNOLOGY,
LOGIC
INC.
CY22
DRAM_ADS15
CY24
SELECTION
SIZE
CRONUS_RHEA
SHEET
DATE: 3-22-1999_16:19
VCC3.3 0.10UF-50V
CX36
DRAM_ADS[2:15]
DM_D[0:31]
DM_D13 DM_D14
DM_D10
DM_D11
DM_D12
DM_D15
DM_D10
DM_D11
100DM_D12
DM_D13 DM_D14 DQ45 DQ46
DQ35
DQ36
DQ37
DQ41
DQ42
DQ43
DQ44
DQ45
DQ35
DQ36
DQ37
DQ41
DQ42
DQ43
DQ32
DQ33
DQ34
DQ38
DQ39
DQ40
DQ46
DQ47
DQ32
DQ33
DQ34
DQ38
DQ39
DQ40
DQ44
DRAM_ADS2 DRAM_ADS3 DRAM_ADS4 DRAM_ADS5 DRAM_ADS6 DRAM_ADS7 DRAM_ADS8 DRAM_ADS9 DRAM_ADS10 DRAM_ADS11 DRAM_ADS12 DRAM_ADS13 DR_CAS[0:3] DR_CAS0 DR_CAS1 DR_CAS2 DR_CAS3 DR_CAS0 DR_CAS1 DR_CAS2 VCC3.3 DR_CAS3
DRAM_ADS2 DRAM_ADS3
DRAM_ADS4 DRAM_ADS5 168PIN-EDO_DIMM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 VCC3.3 RP11 10K(R8)
DQ47
104DM_D15
DM_D0
DM_D1
DM_D2
DM_D3
DM_D4
DM_D5
DM_D6
DM_D7
DM_D8
DM_D9
DM_D0
DM_D5
DM_D6
DM_D8
DM_D1
DM_D2
DM_D3
DM_D4
DM_D7
DM_D9
168PIN-EDO_DIMM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DM_D0 DM_D1 DM_D2 DM_D3 DM_D4 DM_D5 DM_D6 DM_D7 DM_D8 DM_D9 DM_D10 DM_D11 DM_D12 DM_D13 DM_D14 DM_D15 DM_D16 DM_D17 DM_D18 DM_D19 DM_D20 DM_D21 DM_D22 DM_D23 DM_D24 DM_D25 DM_D26 DM_D27 DM_D28 DM_D29 DM_D30 DM_D31
DRAM_ADS6 DRAM_ADS7 DRAM_ADS8 DRAM_ADS9 DRAM_ADS10 DRAM_ADS11 DRAM_ADS12 DRAM_ADS13 DR_CAS0 DR_CAS1 DR_CAS2 DR_CAS3 DR_CAS0 DR_CAS1 DR_CAS2 DR_CAS3
CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7
CAS0 CAS1 CAS2 CAS3 CAS4 CAS5 CAS6 CAS7
DRAM_ADS14 DRAM_ADS15
DRAM_ADS14 DRAM_ADS15
RAS0 RAS2 OE0* OE2* WE0* WE2* DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62
DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
RAS0 RAS2 OE0* OE2* WE0* WE2* DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62
DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DR_RAS0 DR_RAS2
DQ63
DM_D16
DM_D17
DM_D16
DM_D17
DM_D18
DM_D19
DM_D20
DM_D21
DM_D22
DM_D23
DM_D24
DM_D25
DM_D26
DM_D27
DM_D28
DM_D29
DM_D30
DM_D18
DR_WE_N DR_RAS1 DR_RAS3
DM_D19
INTEGRATED DEVICE TECHNOLOGY, INC.
SIZE
DRAM
DM_D31
DQ63
DIMM'S
CRONUS_RHEA
SHEET
DATE: 3-23-1998_14:23
VCC3.3
DQ46
DQ35
DQ36
DQ37
DQ41
DQ42
DQ43
DQ44
DQ32
DQ33
DQ34
DQ38
DQ39
DQ40
DQ45
DQ47
168PIN-SDDIMM DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQMB0 DQMB1 DQMB2 DQMB3 DQMB4 DQMB5 DQMB6 DQMB7 CKE0 CKE1 RAS* CAS* DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
EP_A[0:17] EP_A10 EP_A11 EP_A12 EP_A13 EP_A14 EP_A15 EP_A16 EP_A17 EP_A0 EP_A1 EP_A2 EP_A3 EP_A4 EP_A5 EP_A6 EP_A7 EP_A8 EP_A9 EP_A0 EP_A1 EP_A2 EP_A3 EP_A4 EP_A5 27C080 MEM_D0 MEM_D1 MEM_D2 MEM_D3 MEM_D4 MEM_D5 MEM_D6 MEM_D7 EP_A6 EP_A7 EP_A8 EP_A9 EP_A10 EP_A11 EP_A12 EP_A13 EP_A14 EP_A15 EP_A16 EP_A17 27C080 MEM_D16 MEM_D17 MEM_D18 MEM_D19 MEM_D20 MEM_D21 MEM_D22 MEM_D23
EP_A0 EP_A1 GCLRN EP_A2 IO51 IO50 IO49 IO48 IO47 A18_FWR0_N IO46 IO45 A18_FWR2_N IO44 A18_FWR1_N IO43 A18_FWR3_N IO42 RH_ADS2 IO41 IO40 IO39 IO38 IO37 IO36 IO35 IO34 IO33 EP_A3 EP_A4 EP_A5 EP_A6 EP_A7 EP_A8 EP_A9 EP_A10 EP_A11 EP_A12 EP_A13 EP_A14 EP_A15 EP_A16 EP_A17 GCLK IO64 IO63 IO62 IO61 IO52 IO53 IO54 IO55 IO56 IO57 IO60 IO59 IO58
CPU_BE0
CPU_ALE CPU_ADDR2 CPU_ADDR3 CPU_WD1 CPU_WD0 R_MEM_WE3_N R_MEM_WE2_N R_MEM_WE1_N R_MEM_WE0_N
IO10 IO11 IO12 IO13 IO14 IO15 IO16 IO17 IO18 IO19
EPM7064_84-7
OE1N
IO20
IO21
IO22
IO23
IO24
IO25
IO26
IO27
IO28
IO29
IO30
IO31
IO32
OE2N
EP_A0 EP_A1 EP_A2 EP_A3 EP_A4 EP_A5 MEM_D8 MEM_D9 EP_A6 EP_A7 EP_A8 EP_A9 EP_A10 EP_A11 EP_A12 EP_A13 EP_A14 EP_A15 EP_A16 EP_A17
EP_A0 EP_A1 EP_A2 EP_A3 EP_A4 EP_A5 EP_A6 EP_A7 EP_A8 EP_A9 EP_A10 EP_A11 EP_A12 EP_A13 EP_A14 EP_A15 EP_A16 EP_A17
MEM_D24 MEM_D25 MEM_D26 MEM_D27 MEM_D28 MEM_D29 MEM_D30 MEM_D31
27C080
27C080
MEM_D10 MEM_D11 MEM_D12 MEM_D13 MEM_D14 MEM_D15
MEM_D[0:31]
0.10UF-50V CX100
0.10UF-50V CX99
0.10UF-50V CX98
0.10UF-50V CX97
0.10UF-50V CX25
0.10UF-50V CX24
0.10UF-50V CX23
22UF_10V
22UF_10V
CY32
CY15
INTEGRATED
DEVICE
EPROM
TECHNOLOGY,
LOGIC
INC.
FLASH
SIZE
CRONUS-RHEA
SHEET
DATE: 11-23-1998_14:05
93C46
PCI_EPM_DO
RH_SE_DO
PCI_EPM_SK
PIO10
RH_SE_SK PCI_EPM_CS PIO9
RH_SE_CS PCI_EPM_DI
RH_SE_DI
URT_TX0
RH_TX0
URT_RX0 RH_RX0 URT_TX1 RH_TX1 URT_RX1
STRIP8 RH_RX1
PCI_TRST# PCI_TDI RH_TC0_N
PCI_TCK# PCI_TMS RH_TRST_N RH_TDI SCC_DRQA_N RH_TCK RH_TMS RH_DRQ0 SCC_DRQB_N RH_TC1_N
RH_DRQ1
VCC3.3
TPVCC_3V3 0.10UF-50V CX94
TPVCC4 0.10UF-50V CX95
TPVCC_3V4
CY28 URTCAP1P
1UF_50V
URTCAP1N URTCAP2P MEM_D[0:7] MEM_D0 MEM_D1 MEM_D2 MEM_D3 MEM_D4 MEM_D5 MEM_D6 MEM_D7
C113
1UF_50V 1UF_50V
CY35 CY30 VU10 MAX238
URTCAP2N CY29 RXDA TXDA CTSA RTSA SYNCA W_REQA DTR_REQA RTXCA TRXCA DCDA 85C30 RXDB TXDB SCCRXDA SCCTXDA SCCRXDB SCCTXDB
1UF_50V
R1OUT
R1IN
T1IN R2OUT T2IN
T1OUT R2IN T2OUT SCC_RXDBRS SCC_TXDBRS
R3OUT T3IN R4OUT
R3IN T3OUT R4IN
RH_RXDARS
RH_TXDARS RH_RXDBRS
T4IN
T4OUT
RH_TXDBRS
EP_A1 R_MEM_CS5_N EP_A0 SCC_INT_N
A_~B D_~C
DB9-M
CTSB RTSB DTR_REQB DCDB W_REQB RTXCB TRXCB SYNCB
IACK
RH_TXDARS RH_RXDARS
OSC10MHZ
PCLK
3.6864MHZOSC DB9-M
SCCDTRA
RH_RXDBRS
SCCDRQA
RH_TXDBRS
SCCDTRB SCCDRQB
DB9-M
URT_TX1 URT_RX1
VCC3.3
URT_TX0 URT_RX0
10K(R8) RP18
0.10UF-50V CX63
0.10UF-50V CX64
0.10UF-50V CX65
0.10UF-50V CX66
22UF_10V
22UF_10V
CY21
CY20
INTEGRATED DEVICE TECHNOLOGY, INC.
SERIAL COMM. CONTROLLER
SIZE
CRONUS-RHEA
SHEET
DATE: 3-23-1998_14:24
CPU_ADDR2 CPU_ADDR3 CPU_ALE CPU_WR_N CPU_CIP_N CPU_ACK_N CPU_LAST
HP-CONN HP-CONN SAMTEC-80M CPU_BGNT_N RH_RST_N CPU_BREQ_N CPU_BERR_N CPU_CRST_N CPU_BE2 CPU_BE3 CPU_BE0 HP-CONN
INTEGRATED DEVICE TECHNOLOGY, INC.
RHEA_POD1
SIZE
CRONUS_RHEA
SHEET
DATE: 3-23-1998_14:25
RH_INTR3_N R_RAS0 R_RAS1 R_RAS2 R_RAS3 R_CAS0 R_CAS1 R_MEM_CS0_N R_MEM_CS1_N R_MEM_CS2_N R_MEM_CS3_N R_MEM_CS4_N R_MEM_CS5_N R_MEM_WAIT_N HP-CONN R_CAS2 R_CAS3 R_245OE_N R_WE_N R_CKE R_SDCAS_N R_SDRAS_N RH_TC1_N RH_TC0_N HP-CONN RH_DRQ1 RH_DRQ0 RH_RX0 RH_RX1 RH_TX0 RH_TX1 RH_TRST_N RH_TDO RH_TDI RH_TMS RH_TCK R_MEM_WE0_N R_MEM_WE1_N R_MEM_WE2_N R_MEM_WE3_N R_MEM_OE_N RH_SE_SK RH_SE_DO RH_SE_CS CPU_DT/R_N RH_SE_DI R_MEM_245_OE_N HP-CONN
CPU_MCLK
SAMTEC-80M
INTEGRATED DEVICE TECHNOLOGY, INC.
RHEA_POD2
SIZE
CRONUS_RHEA
SHEET
DATE: 3-23-1998_14:25
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6
PCI_C/BE2#
HP-CONN
PCI_AD7
PCI_AD8 PCI_AD9
PCI_AD10 PCI_AD11
PCI_AD12 PCI_AD13
PCI_AD14 PCI_AD15
PCI_AD16 PCI_AD17
PCI_AD18 PCI_AD19
PCI_AD20 PCI_AD21
PCI_AD22
HP-CONN
SAMTEC-80M
PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 RHEA_POD3 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 SIZE
INTEGRATED DEVICE TECHNOLOGY, INC.
CRONUS_RHEA
SHEET
DATE: 3-23-1998_14:25
RH_ADS2 RH_ADS3 RH_ADS4 RH_ADS5 RH_ADS6 RH_ADS7 RH_ADS8
HP-CONN RH_ADS9 RH_ADS10 RH_ADS11 RH_ADS12 RH_ADS13 RH_ADS14 RH_ADS15 RH_ADS16 RH_ADS17 RH_ADS18 RH_ADS19 RH_ADS20 RH_ADS21 RH_ADS22 PCI_FRAME# PCI_PERR# HP-CONN
PCI_SERR# PCI_DEVSEL#
SAMTEC-80M
INTEGRATED DEVICE TECHNOLOGY, INC.
RHEA_POD4
SIZE
CRONUS_RHEA
SHEET
DATE: 3-23-1998_14:26
VCC3.3
-12V
2.7K(R8) +12V
2.7K(R8)
PCI_TRST1# PCI_TMS1
PCI_TCK1
B15B15
PCI_INTA# PCI_INTC#
PCI_PR1#S1 PCI_PR2#S1
PCI_RST# PCI_GNT1# VCC3.3 +12V -12V 22UF_10V 22UF_10V 22UF_20V Tantalum Tantalum 22UF_20V
PCI-5V-32BIT-FEMALE-CONNECTOR
B16B16
PCI_TRDY# PCI_STOP# PCI_5KPU1 PCI_5KPU2 PCI_PAR PCI_FRAME#
PCI_TRST[1:3]# PCI_TRST1# PCI_TRST2# PCI_TRST3#
PCI_C/BE0#
5.1K(R8)
5.1K(R8) PCI-FCONN32-5V
PCI_TMS[1:3] 0.1UF_50V 0.1UF_50V 0.1UF_50V 0.1UF_50V 0.1UF_50V 0.1UF_50V
PCI_REQ[1:3]#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_TMS1
PCI_TMS2
PCI_TMS3
INTEGRATED DEVICE TECHNOLOGY, INC.
PCI-BUS
SLOT
SIZE
5.1K(R8) 5.1K(R8) 5.1K(R8)
CRONUS-RHEA
SHEET
DATE: 3-23-1998_14:26
VCC3.3
-12V
+12V
PCI_TCK2 PCI_TDO2 PCI_INTB# PCI_INTD# PCI_PR1#S2 PCI_PR2#S2 B15B15
PCI_AD30 PCI_AD28 PCI_AD26 PCI_AD24 PCI_AD13 PCI_AD22 PCI_AD20 PCI_AD18 PCI_AD16
PCI_TRST2# PCI_TMS2 PCI_TDI2 PCI_INTA# PCI_INTC#
PCI_RST# PCI_GNT2#
L_PCI_REQ2# PCI_AD31 PCI_AD29 PCI_AD27 PCI_AD25
PCI_AD23 PCI_AD21 PCI_AD19 PCI_AD17
PCI-5V-32BIT-FEMALE-CONNECTOR
PCI_CLK2
B16B16
PCI_C/BE3#
PCI_C/BE2# PCI_IRDY# PCI_DEVSEL# PCI_LOCK# PCI_PERR# PCI_SERR# PCI_C/BE1# PCI_AD14 PCI_AD12 PCI_AD10
PCI_FRAME# PCI_TRDY# PCI_STOP# PCI_5KPU3 PCI_5KPU4 PCI_PAR PCI_AD15 PCI_AD13 PCI_AD11 PCI_AD9
PCI_AD8 PCI_AD7 PCI_AD5 PCI_AD3 PCI_AD1
PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0
PCI_C/BE0#
VCC3.3 +12V
-12V PCI-FCONN32-5V 22UF_20V Tantalum 22UF_10V 22UF_10V Tantalum CY10 CY11
PCI_AD[0:31]
22UF_20V
INTEGRATED DEVICE TECHNOLOGY, INC.
PCI-BUS
SIZE
SLOT
CRONUS-RHEA
SHEET
DATE: 3-23-1998_14:26
VCC3.3
-12V
+12V
B1B1 PCI_TCK3 PCI_TDO3 B2B2 PCI_INTB# PCI_INTD# PCI_PR1#S3 PCI_PR2#S3
PCI_TRST3# PCI_TMS3 PCI_TDI3 PCI_INTA# PCI_INTC#
B14B14 B15B15 PCI_CLK3 L_PCI_REQ3# PCI_AD31 PCI_AD29 PCI_AD27 PCI_AD25 B16B16 B17B17 B18B18 B19B19 B20B20 B21B21 B22B22 B23B23 B24B24 B25B25 B26B26 PCI_AD23 PCI_AD21 PCI_AD19 PCI_AD17 PCI_C/BE2# PCI_IRDY# PCI_DEVSEL# PCI_LOCK# PCI_PERR# PCI_SERR# PCI_C/BE1# PCI_AD14 PCI_AD12 PCI_AD10 B27B27 B28B28 B29B29 B30B30 B31B31 B32B32 B34B34
PCI_AD30 PCI_AD28 PCI_AD26 PCI_AD24 PCI_AD14 PCI_AD22 PCI_AD20 PCI_AD18 PCI_AD16
PCI_RST# PCI_GNT3#
PCI-3V-32BIT-FEMALE-CONNECTOR
PCI_C/BE3#
PCI_FRAME# PCI_TRDY# PCI_STOP# PCI_5KPU5 PCI_5KPU6 PCI_PAR PCI_AD15 PCI_AD13 PCI_AD11 PCI_AD9
B36B36 B37B37 B38B38 B40B40
B41B41 B42B42 B43B43
B45B45 B46B46 B47B47 B48B48 B49B49 B50B50 B51B51
PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 VCC3.3 +12V -12V 22UF_20V Tantalum 22UF_10V 22UF_10V Tantalum 22UF_20V PCI_C/BE0#
PCI_AD8 PCI_AD7 PCI_AD5 PCI_AD3 PCI_AD1
B53B53 B54B54 B55B55 B56B56 B57B57 B58B58 B59B59
B61B61 B62B62
CY12
CY13
PCI-FCONN32-3V PCI_AD[0:31]
INTEGRATED DEVICE TECHNOLOGY, INC.
PCI-BUS
SIZE
SLOT
3.3V
CRONUS-RHEA
SHEET
DATE: 3-23-1998_14:27
FCT257DT
PCI_CLK0 S_PCI_CLK
PCI_TRST# -12V +12V
PCI_AD16 PCI_AD17 VCC3.3 PCI_C/BE2# PCI_FRAME# PCI_IRDY# PCI_TRDY# VCC3.3 PCI_DEVSEL# PCI_STOP# VCC3.3 PCI_LOCK# PCI_PERR#
OE_N
R_PCI_CLK
PCI_TCK# PCI_TMS PCI_TDI PCI_TDO
FCT257DT
RH_RST_N S_PCI_RST#
OE_N
PCI_RST#
PCI_GNT3#
FCT257DT
L_PCI_REQ3# S_PCI_IDSEL
OE_N
PCI_REQ3#
connector
connector
FCT257DT
L_PCI_REQ2# PCI_5KPU7
OE_N
VCC3.3 PCI_SERR# PCI_PAR VCC3.3 PCI_AD15 PCI_C/BE1# VCC3.3 PCI_AD14 PCI_AD13 PCI_AD11 PCI_AD12
PCI_AD10 PCI_AD9 KEY5 KEY6 KEY7 KEY8
PCI_REQ2#
KEY1 KEY2 KEY3 KEY4
FCT257DT OE_N
S_PCI_CLK PCI_GNT1# PCI_REQ1#
S_PCI_RST#
PCI_AD30 PCI_AD31 PCI_AD29 PCI_AD28 PCI_AD26 PCI_AD27 PCI_AD25 PCI_AD24
R_BOOT20
universal
universal
edge
RH_SE_CS
edge
PCI_GNT2#
VCC3.3
PCI_C/BE0# PCI_AD8
PCI_AD7 PCI_AD6 PCI_AD4 PCI_AD5 PCI_AD3 PCI_AD0
0.10UF-50V CX18 0.10UF-50V CX19 22UF_10V
VCC3.3
CY26
VCC3.3
PCI_AD2 PCI_AD1
VCC3.3 S_PCI_IDSEL PCI_C/BE3# VCC3.3 PCI_AD23 PCI_AD22 PCI_AD20 PCI_AD21 PCI_AD19 PCI_AD18 VCC3.3
PCI-EDGECONN
PCI-EDGECONN PCI_AD[0:31]
INTEGRATED DEVICE TECHNOLOGY, INC.
SATELLITE CONNECTOR
SIZE
CRONUS_RHEA
SHEET
DATE: 3-23-1998_14:27
-RESET inputs EPLD_clk: INPUT; RSTinitN: INPUT; RHrstN: INPUT; MODEin[9.0]: INPUT; Rboot22: INPUT; Rboot21: INPUT; Rboot20: INPUT; Rboot19: INPUT; -RESET outputs CPUcrstN: OUTPUT; CPUrstN: OUTPUT; CPUintN[5.0]: OUTPUT; CPUnmiN: OUTPUT; CPUbgntN: OUTPUT; CPUpcst[4.0]: OUTPUT; RHads22: OUTPUT; RHads21: OUTPUT; RHads20: OUTPUT; RHads19: OUTPUT; -INTERRUPT inputs
SCCintN: INPUT; RHintr3N: INPUT; PCIintAN: INPUT; PCIintBN: INPUT; PCIintCN: INPUT; PCIintDN: INPUT;
-SRAM control inputs Rmemcs1N: INPUT; RmemweN[3.0]: INPUT; RmemoeN: INPUT;
-SRAM control outputs SRAMcsN[3.0]: OUTPUT; SRAMweN: OUTPUT; -BUS CYCLE CONTROL OUTPUT RmemwaitN: OUTPUT; -SOFTWARE PORT MEMd[7.0]: BIDIR; Rmemcs3N: INPUT; FUTURE INPUTS Rmemcs0N: INPUT;- EPROM chip select Rmemcs2N: INPUT;- RESERVED chip select Rmemcs4N: INPUT;- RESERVED chip select Rmemcs5N: INPUT;- chip select
Variable Section (optional) VARIABLE Node Declarations count_rst_dly: NODE; SOFTrst: NODE; RmemweNX: NODE; RmemcsXN: NODE; PCST[4.0]: TRI; CPUbgntNtri: TRI; RHads22tri: TRI; RHads21tri: TRI; RHads20tri: TRI; RHads19tri: TRI; SWport[7.0]: TRI;
Register Declaration CLEAR_RST_DLY CPUcrstN: DFF; CPUrstN: DFF; RmemwaitN: DFF; rst_dly[6.0]: DFFE; SOFTport[7.0]: DFFE; State Machine Declaration Reset state_machine reset_sm MACHINE BITS (RST1,RST0) WITH STATES( RST_IDLE= RST_CRST= RST_RST= WAIT state_machine wait_sm MACHINE BITS (WST2,WST1,WST0) WITH STATES( WAIT_IDLE= WAIT1= WAIT2= WAIT3= WAIT4= WAIT5= WAIT6= WAIT7= Logic Section BEGIN Defaults Statement DFF;
DEFAULTS CPUcrstN= VCC; CPUrstN= VCC; RmemwaitN= VCC; rst_dly[6.0]= GND; SOFTport[7.0]= GND; CLEAR_RST_DLY VCC; DEFAULTS; CLEAR_RST_DLY.clk GLOBAL(EPLD_clk); CLEAR_RST_DLY.clrn RSTinitN; CPUcrstN.clk= GLOBAL(EPLD_clk); CPUcrstN.clrn= RSTinitN; CPUrstN.clk= GLOBAL(EPLD_clk); CPUrstN.clrn= RSTinitN; RmemwaitN.clk= GLOBAL(EPLD_clk); RmemwaitN.clrn= RSTinitN; rst_dly[].clk= GLOBAL(EPLD_clk); rst_dly[].clrn= CLEAR_RST_DLY; rst_dly[].ena= count_rst_dly;
State Machine Defaults reset_sm.clk= GLOBAL(EPLD_clk); reset_sm.reset= !RSTinitN; wait_sm.clk= GLOBAL(EPLD_CLK); wait_sm.reset= CPUrstN; -RESET LOGIC rst_dly[]= rst_dly[]
-MODE INITIALIZATION
PCST[].oe= !CPUrstN; PCST[0].in= MODEin[0]; CPUpcst[0]= PCST[0].out; PCST[1].in= MODEin[1]; CPUpcst[1]= PCST[1].out; PCST[2].in= MODEin[2]; CPUpcst[2]= PCST[2].out; PCST[3].in= MODEin[3]; CPUpcst[3]= PCST[3].out; PCST[4].in= MODEin[4]; CPUpcst[4]= PCST[4].out; CPUbgntNtri.oe= !CPUrstN; CPUbgntNtri.in= MODEin[5]; CPUbgntN= CPUbgntNtri.out; RHads22tri.oe= !CPUrstN; RHads22tri.in= Rboot22; RHads22= RHads22tri.out; RHads21tri.oe= !CPUrstN; RHads21tri.in= Rboot21; RHads21= RHads21tri.out; RHads20tri.oe= !CPUrstN; RHads20tri.in= Rboot20; RHads20= RHads20tri.out; RHads19tri.oe= !CPUrstN; RHads19tri.in= Rboot19; RHads19= RHads19tri.out; -INTERRUPT LOGIC
CPUintN[0]=!(!CPUrstN !MODEin[6] CPUrstN !SCCintN CPUintN[1]=!(!CPUrstN !MODEin[7] CPUrstN !PCIintaN); CPUintN[2]=!(!CPUrstN !MODEin[8] CPUrstN !PCIintbN CPUintN[3]=!(!CPUrstN !MODEin[9] CPUrstN !RHintr3N CPUintN[4]=!( CPUrstN !PCIintcN CPUintN[5]=!( CPUrstN !PCIintdN CPUnmiN=VCC; -SRAM CONTROL LOGIC RmemweNX= RmemweN0 RmemweN1 RmemweN2 RmemweN3 SRAMcsN0= !(!Rmemcs1N !RmemweN0 #!Rmemcs1N !RmemoeN SRAMcsN1= !(!Rmemcs1N !RmemweN1 #!Rmemcs1N !RmemoeN SRAMcsN2= !(!Rmemcs1N !RmemweN2 #!Rmemcs1N !RmemoeN SRAMcsN3= !(!Rmemcs1N !RmemweN3 #!Rmemcs1N !RmemoeN SRAMweN= !(!Rmemcs1N !RmemweNX -BUS CYCLE CONTROL LOGIC RmemcsXN= Rmemcs0N Rmemcs1N Rmemcs2N Rmemcs3N Rmemcs4N Rmemcs5N
CASE wait_sm WHEN WAIT_IDLE RmemwaitN= VCC; wait_sm= WAIT1; WHEN WAIT1=> (RmemcsXN) THEN RmemwaitN= GND; wait_sm= WAIT2; ELSE RmemwaitN= VCC; wait_sm= WAIT_IDLE; WHEN WAIT2=> (RmemcsXN) THEN RmemwaitN= GND; wait_sm= WAIT3; ELSE RmemwaitN= VCC; wait_sm= WAIT_IDLE; WHEN WAIT3=> (RmemcsXN) THEN RmemwaitN= GND; wait_sm= WAIT4; ELSE RmemwaitN= VCC; wait_sm= WAIT_IDLE; WHEN WAIT4=> (RmemcsXN) THEN RmemwaitN= GND; wait_sm= WAIT5; ELSE
RmemwaitN= VCC; wait_sm= WAIT_IDLE; WHEN WAIT5=> (RmemcsXN) THEN RmemwaitN= GND; wait_sm= WAIT6; ELSE RmemwaitN= VCC; wait_sm= WAIT_IDLE; WHEN WAIT6=> (RmemcsXN) THEN RmemwaitN= GND; wait_sm= WAIT7; ELSE RmemwaitN= VCC; wait_sm= WAIT_IDLE; WHEN WAIT7=> (RmemcsXN) THEN RmemwaitN= VCC; wait_sm= WAIT_IDLE; ELSE RmemwaitN= VCC; wait_sm= WAIT_IDLE;
CASE; RmemwaitN= VCC; -S/W PROGRAMMABLE PORT LOGIC
SWport[].oe= (!Rmemcs3N !RmemoeN SWport[].in SOFTport[]; MEMd[]= SWport[].out; SOFTport[].d= MEMd[]; SOFTport[].clrn= CPUrstN; SOFTport[].clk= GLOBAL(EPLD_clk); SOFTport[].ena= !(!Rmemcs3N !RmemweN0 SOFTrst= SOFTport[0]; -RESET LOGIC CASE reset_sm WHEN RST_IDLE CPUrstN= GND; reset_sm= RST_CRST; WHEN RST_CRST count_rst_dly= VCC; (rst_dly[6]) THEN CPUrstN reset_sm= RST_RST; ELSE CPUrstN= GND; reset_sm= RST_CRST; WHEN RST_RST CLEAR_RST_DLY GND; (SOFTrst !RHrstN) THEN (!RHrstN) THEN CPUrstN= GND; reset_sm= RST_IDLE; ELSE reset_sm= RST_RST; CASE; GND;
END; Address gen. 8/16/32 devices Flash write generation. EPLD_clk: INPUT; CPU_rstN: INPUT; Rmem_cs0_N: INPUT; Rmem_cs5_N: INPUT; FlashN: INPUT; CPUaddrs2: INPUT; CPUaddrs3: INPUT; RHads[22.2]: INPUT; CPU_beN[3.0]: INPUT; CPU_aleN: INPUT; CPU_wdN[1.0]: INPUT; RmemWrN[3.0]: INPUT; RmemoeN: INPUT; EP_a[17.0]: OUTPUT; A18_FwrN[3.0]: OUTPUT; A18_A19: OUTPUT; ~10MHz Clock generation. OSC10Mhz: OUTPUT; Brh_clk: OUTPUT; control signals SCC_WR_N: OUTPUT; SCC_RD_N: OUTPUT;
Variable Section (optional) VARIABLE Node Declaration count_dly: NODE;
Register Declaration Counter[4.0]: DFF; OSC10Mhz: DFF;
State Machine Declaration
Logic Section BEGIN Defaults Statement DEFAULTS Counter[4.0]= GND; OSC10Mhz= GND; State Machine Defaults -END DEFAULTS;
Counter[4.0].clk= GLOBAL(EPLD_clk); Counter[4.0].clrn= CPU_rstN; OSC10Mhz.clk= Counter[4]; OSC10Mhz.clrn= CPU_rstN;
-ADDRESS LOGIC CPU_wdN[1.0] THEN EP_a[0] CPU_beN[0]; EP_a[1] CPU_beN[1]; EP_a[2] CPUaddrs2; EP_a[3] CPUaddrs3; EP_a[17.4] RHads[17.4]; FlashN THEN A18_FwrN[3.0] RHads[18]; A18_A19= RHads[19]; ELSE A18_FwrN[3]= RmemWrN[3]; A18_FwrN[2]= RmemWrN[2]; A18_FwrN[1]= RmemWrN[1]; A18_FwrN[0]= RmemWrN[0]; A18_A19= Rhads[18]; ELSIF CPU_wdN[1.0] THEN EP_a[0] CPU_beN[1]; EP_a[1] CPUaddrs2; EP_a[2] CPUaddrs3; EP_a[17.3] RHads[18.4]; FlashN THEN A18_FwrN[3.0]= RHads[19]; A18_A19= RHads[20]; ELSE A18_FwrN[3]= RmemWrN[3];
A18_FwrN[2]= RmemWrN[2]; A18_FwrN[1]= RmemWrN[1]; A18_FwrN[0]= RmemWrN[0]; A18_A19= Rhads[19]; ELSIF CPU_wdN[1.0] THEN EP_a[0] CPUaddrs2; EP_a[1] CPUaddrs3; EP_a[17.2] RHads[19.4]; FlashN THEN A18_FwrN[3.0] RHads[20]; A18_A19= RHads[21]; ELSE A18_FwrN[3]= RmemWrN[3]; A18_FwrN[2]= RmemWrN[2]; A18_FwrN[1]= RmemWrN[1]; A18_FwrN[0]= RmemWrN[0]; A18_A19= Rhads[20]; -OSCILLATOR LOGIC OSC10Mhz.d= !OSC10Mhz.q; Counter[].q THEN Counter[].d ELSE Counter[].d Counter[].q Brh_clk= GLOBAL(EPLD_clk); LOGIC SCC_WR_N= CPU_rstN RmemWrN0 Rmem_cs5_N SCC_RD_N= CPU_rstN RmemoeN Rmem_cs5_N
END;

Version October 1999 2975 Stender Way, Santa Clara, California 95

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