DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
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DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
Robert Stodieck
APPLICATION NOTE AN-24
APPLICATION NOTE AN-24
INTRODUCTION
Error Detection Correction (EDC) chip itself element system. connected surrounding system controlled left system designer. Because there many design variations possible, important designer develop clear idea target design before beginning design process. Basic design approaches perturbations enumerated this application note. details control logic depend configuration system, topology, nature system involved, nature diagnostic hardware used. data topology highly dependent individual target system. This application note approaches topology issue first. advantages disadvantages using word widths that different from system discussed. next topic covered system with cache. Then operational configuration system discussed. This implies answering questions about unit handles errors particular system discussed. operating system deals with function discussed, followed practical discussion some obvious hardware topics. final topic memory system diagnostics verification. appendix includes tables software that useful debugging writing diagnostic software board. Data Topology Most contemporary CPUs execute write operations byte other sub-word width types. These cause special problems units since transactions with memory carried whole width words. facilitate partial word write operations with IDT39C60 IDT49C460 type units, tri-state transceivers normally required between system unit. These buffers required prevent contention between system drivers units data outputs during partial word write operations. Figure shows arrangement appropriate large DRAM arrays. need isolation data system shown examining data paths, shown with white arrows. These used final write operation partial-word write cycle. this case, only data bits being written from processor memory. processor system drivers tri-stated byte boundaries then this buffers could removed, this common situation. Depending memory size, additional buffering required between memory proper. buffer configuration must determined before beginning memory controller design. appropriate general purpose topology shown Figure common other sets bi-directional
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buffers latched type such IDT74FCT646 instead IDT74FCT245 shown. family waveforms appropriate format shown Figure shown Figure waveform diagrams include precise timing considerations which left designer. given system, buffers separating from memory IC's eliminated capacitance speed considerations allow. Width System Width width System normally matched. However, there valid reasons making both wider narrower than system bus. Wide words significantly more efficient than narrower word widths terms amount checkbit memory used given amount data memory. amount check-bit memory required data bits bits data bits organized word bits handles 32-bit words. Twenty-four bits check-bit memory would required data bits organized four 16-bit data words. purposes speed, would ideal have 8-bit words systems that byte write operations. This would make unnecessary ever have read memory location before writing partial word these systems. Unfortunately, eight-bit words grossly inefficient terms check-bit memory usage. Therefore, word widths normally 16-bits more. Since word widths must generally 16-bits more check-bit memory efficiency, since generalpurpose computers generally byte partial-word-write operations, general-purpose computers force unit able process partial word-width write operations. Partial word-width write operations require subsystem execute read-modify-write type memory cycle. Thus, controller must take over control memory system execute read before completing partial word write. some applications, where use, desirable speed processing prohibiting partial word operations either hardware level software level. Speed critical sections code should executed without partial-word write operations. read-modify-write cycle executed during partial-word write identical correction cycle executed during read cycle when error occurred. readmodify-write cycle should confused with readmodify write cycle executed some CPU's. Verification memory system using word wider than system word complicated fact that memory write cycles become read-modify-write cycles (i.e. partial-word-write cycles). Careful consideration diagnostic procedures needs made during design avoid unnecessarily complex debugging procedures.
2917/-
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
74FCT245
Optional
IDT71256
74FCT245
74FCT245
IDT71256
IDT71981
IDT71981
IDT71981
IDT71256
2917
IDT71256 IDT71981
74FCT245
IDT39C60
Figure general purpose 16-bit data topology. Corresponding timing waveforms shown Figure IDT74FCT245 buffers separate data from Main memory. Separate-I/O RAMs used check-bit memory.
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
READ-CORRECT ALWAYS CORRECT ERROR
NON-CASCADED CONFIGURATION
READ-NO ERROR
WRITE PARTIAL WORD -CORRECT ALWAYS
ERROR DETECT TIME LIMIT 0123 4WW567
GROUP-LOWER BYTE PROCESSOR
ERROR DETECT TIME LIMIT
GROUP-UPPER BYTE PROCESSOR BUS(1)
39C60 GROUP CORRECT=1
OEBYTE OEBYTE
LEIN LEOUT /GEN
OEBYTE OEBYTE
LEIN LEOUT /GEN
OEBYTE OEBYTE
LEIN LEOUT /GEN
ERROR
GROUP-UPPER LOWER BYTES-MEMORY BUS(2)
ERROR
ERROR
71256 GROUP-UPPER LOWER BYTES-71981 CHECK MEMORY
2917
Figure sample family timing waveforms system. target system based IDT71256 static RAMs main memory with IDT71981 separate RAMs check-bit memory. (See Figure partial word write case illustrates order byte write.
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
74FCT245 74FCT245 74FCT245
74FCT245
74FCT244
8-15
DRAM
DRAM
32-Bit SYSTEM
16-23
74FCT245
24-31
8-15
74FCT244
DRAM
DRAM
74FCT245
DRAM
DRAM
16-23
74FCT244
IDT49C460
16-23
DRAM
DRAM
CHECK-BIT DRAM
74FCT245
24-31
74FCT244
DRAM
DRAM
74FCT244
24-31
74FCT244
8-15
74FCT244
74FCT244
DRAM
2917
Figure general purpose 32-bit topology wide DRAMs. white arrows indicate data flow paths used funal write phase partial word write cycle. Data bits being written into memory from processor.
Systems Using Cache systems using cache memory, desirable place function between cache main memory, opposed locating function between processing elements cache. Parity used singlebit error detection scheme between cache. RISC architectures tend require more memory accesses unit time than complex-instruction-set processors. This makes cache memory more important RISC system. appropriate topology RISC type processor with cache memory shown Figure cache memory also affords possibility using different error correcting philosophy. function located between cache main memory, then allowable data reads corrected sent cache, immediately written back main memory, after error been discovered. this approach, corrected memory words updated normal write-back processes cache memory. Instruction reads must thought differently than data reads since instructions normally written back memory from cache. However, possible write corrected instruction word back memory after
detection, since instruction usually backed different media. most systems there know whether operating instructions data, correction philosophy must selected that applied both instruction data words. Diagnostic Hardware syndrome latch capturing syndrome values after errors transferring them system data always recommended. Providing check-bit memory read-back ability allows direct verification gross functionality check-bit memory board'. This greatly facilitates check-bit memory verification. More subtle problems explored indirectly interpreting correction patterns known data using syndrome data interpret failure patterns. Depending configuration, possible same latch capture check-bits from check-bit memory, second latch provided allow this. Ideally, diagnostic hardware includes address latches capture address error. However, this practical particular application. sufficient identify individual which error occurred.
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
79R2020
74FCT244 IDT6167
74FCT245
74FCT244
DRAM
DRAM
74FCT244
74FCT245
R2000A RISC
74FCT244
IDT6167
DRAM
DRAM
74FCT244
DRAM
DRAM
74FCT244
IDT6167
74FCT245
74FCT244
79R2020
74FCT244 IDT6167
DRAM
DRAM
DRAM
DRAM
RISC
CACHE
WRITE-BACK BUFFERS
IDT49C460
DRAM
74FCT244
2917
24-31
CHECK-BIT DRAM
Figure arrangement appropriate with caches such IDT79R3000 IDT79R2000 RISC processor.
74FCT244
79R2020
16-23
74FCT244
79R2020
74FCT245
8-15
74FCT244
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
OVERVIEW OPERATIONAL MODES
Watch Correct Always Memory Read Cycle bus-watch system, errors only corrected after they have been detected chip. Data corrected written back memory scrub errors, only after error been detected. theory, chip only "watches" normally, does slow memory read cycles with correction delays unless error been detected. Since errors during read operations normally very rare, read cycle bus-watch systems normally faster than correct-always systems. correct-always systems, data read system always corrected. control logic simpler design implement because there only type read cycle. Memory cycle timing correct-always systems completely deterministic thus such systems lend themselves more effectively real-time applications. Watch Correct Always Partial Word Write Cycle write operation that width less than word width forces subsystem execute read cycle prior actually writing memory. This required provide unit with whole data word written into memory purpose check-bit generation. time saved correcting data read from memory prior subsequent write operation. partial-word-write operation virtually identical read cycle correct-always mode read cycle with error detected. Consequently, partial word write usually done "correct always" mode. Operating System Involvement systems capable doing partial-word-write operations, necessary initialize memory power This done hardware usually done operating system. Initialization implies writing every memory location with arbitrarily chosen constant thereby writing check-bit memory with correct corresponding check-bits. need initialize memory results from nature read-modify-write cycle required event partialword-write operation. memory been initialized, read cycle will normally result error indication attempt `correct' data field before writing back memory. This tends introduce errors into previously written data bytes sub-words. possible design state machine controller that corrects single errors fashion transparent CPU. This always desirable since masks hard singlebit errors that indicate hardware problems. case, operating system must become involved event multiple errors only issue appropriate error message system operator.
desirable single errors much information about error practical. Relevant data ideally includes syndrome bits identify location word, physical address error. complete transparency, such that desired real-time systems, error logging must eliminated accommodated entirely hardware. real-time systems, interrupting after error occurrence conventional error data. Syndrome data collected, other error information system hardware retains retrieved. Non-obvious Hardware Topics 32-bit system with bi-directional check-bit 64-bit cascaded mode, check-bit input-output syndrome functions time-multiplexed onto same bus. unit correction mode, input latches open, OESC pins low, will tend oscillate. This combination control inputs would appropriate normal operation might occur idle period between memory cycles unless designer specifically designs this condition out. oscillation occurs this condition because units attempting output syndrome bits based data `check-bit' inputs. However, syndrome outputs this state being back check-bit inputs. result oscillation check-bit/syndrome bus. important sometimes overlooked fact that acceptable allow inputs most CMOS parts `float'. result doing this increased power consumption, chip noise sometimes outright oscillation which lead latch-up. check-bit inputs data unit should allowed float when being used. power systems particular, inputs must brought logic highs lows when use. This imply tri-stating some buffers that would otherwise tri-stated when actively driving, actually including pull-up pulldown resistors bias when actively being driven. Basic Unit Operation Basic 32-bit 49C460 operation with timing diagrams illustrated Figures These timing diagrams also appropriate 16-bit IDT39C60 system. IDT39C60, LEout Generate functions have separate pins. IDT49C460, they both controlled pin. usually convenient when using IDT39C60 wire pins together. non-expanded case, with either unit, input latch convenient logically dictated (i.e., LEin tied high). Also, correct simply left asserted normal operation. "detect" mode usually only used diagnostic aid, which allows data correction function shut while still generating error signal based input data.
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
Diagnostic Modes Since function introduces complicating layer between system memory, diagnostic modes provided provide testability entire memory subsystem. memory systems where word wider than system memory, verification complicated fact that writes partial word writes. Good diagnostic design requires forethought. unit's internal diagnostic latches have distinct unrelated data fields. check-bit data field used provide check data substituted normal check-bits diagnostic modes. These will written memory diagnostic generate mode, substituted check-bits read from memory diagnostic-detect correct mode. second field diagnostic latch control field. control field ignored except when part placed internal control mode. control byte used control operating features part when part been placed internal control mode. Each control field corresponds part overrides logic sense that when part internal control mode. example, could place part into correct mode setting correct unit logic high, could part into internal control mode correct diagnostic latch `1'. Thus there always ways achieve mode operation. example, diagnostic modes entered setting external diagnostic inputs appropriately, entering internal control mode setting diagnostic latch bits appropriately. internal control mode provided convenience useful controlling operating modes during diagnostic testing software initialization. Conceptually, important realize that anything that done this mode done with external logic well.
Memory System Verification Strategies When design being verified, critical isolate different problem factors; this function diagnostics. prove function primary memory array, unit placed pass-through mode that does interact with data stream. Once primary memory array been verified functional, check-bit memory must verified. diagnostic generate mode used write known data into check-bit memory. Reading check-bit memory directly through possible, gross functional testing must done external latch with logic analyzer. Using external latch greatly facilitates check-bit memory verification. Collecting syndrome data from error events requires that external latch included design capture syndrome data after error occurred. should possible clear this latch after reading contents from system bus. Depending configuration, possible same latch capture check-bits from check-bit memory. More subtle problems explored indirectly interpreting correction patterns known data using syndrome data interpret failure patterns.
SUMMARY
error detection correction unit located critical path between memory. operational configuration intimately affects speed final system. wide variation between computer architectures that desirable for, unit necessarily generalized process. object this application note been illuminate some topics that designer will encounter process designing system.
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
MEMORY
DATA CHECK BITS
WRITE WORD MEMORY-GENERATE CHECK-BITS-WRITE CHECK-BITS MEMORY
CB0-7
OE0-3
DATA LATCH
ERROR DECODE CORRECT
DATA INPUT LATCH
CHECK GENERATE
OESC
SC0-7
SYSTEM LEIN
CHECK LATCH DIAGNOSTIC LATCH SYNDROME GENERATE ERROR DETECT
ERROR MULT ERROR
LEDIAG CODE ID0, DIAG MODE0, LEOUT/GEN CORRECT
CONTROL LOGIC
2917
LEOUT/GEN
LEIN
DATA,
CORRECT
ERROR
SC0-7
OESC
DIAG MODE0, LEDIAG CODE ID0, PDAE T@RS00002 8/18/87
2917
Figure 32-bit full-word-width write operation (generate mode).
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
MEMORY
DATA CHECK BITS
READ WORD FROM MEMORY-DETECT ERRORS- CORRECT WORD LATCH CORRECTION OUTPUT LATCH CB0-7
OE0-3
DATA LATCH
ERROR DECODE CORRECT
DATA INPUT LATCH
CHECK GENERATE
OESC
SC0-7
SYSTEM LEIN
CHECK LATCH DIAGNOSTIC LATCH SYNDROME GENERATE ERROR DETECT
ERROR MULT ERROR
LEDIAG CODE ID0, DIAG MODE0, LEOUT/GEN CORRECT
CONTROL LOGIC
ERROR DETECT MIN. TIME LIMIT
2917
LEOUT/GEN
LEIN
DATA,
DON'T CARE DATA LATCHED INTO INPUT LATCH
CORRECT
ERROR
SC0-7
OESC
DIAG MODE0, LEDIAG CODE ID0, PDAE T@RS00003 8/18/87
2917
Figure Memory read error detect. Identical read operations first phase partial-word-write operation (correct mode).
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
MEMORY
DATA CHECK BITS
WRITE CONNECTED WORD CHECK-BITS MEMORY CB0-7
OE0-3
DATA LATCH
ERROR DECODE CORRECT
DATA INPUT LATCH
CHECK-BIT CHECK GENERATE SC0-7
OESC
SYSTEM LEIN
CHECK LATCH DIAGNOSTIC LATCH SYNDROME GENERATE ERROR DETECT
ERROR MULT ERROR
LEDIAG CODE ID0, DIAG MODE0, LEOUT/GEN CORRECT
CONTROL LOGIC
2917
LEOUT/GEN
LEIN
DATA,
CORRECT
ERROR
SC0-7
OESC
DIAG MODE0, LEDIAG CODE ID0,
2917
Figure Memory correct check-bit regenerate. Identical second phase read operation which error occurred, partial-word-write operation except state individual byte output enables.
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
ERROR DECIMAL SYNDROME DECIMAL EQUIVALENT>>
2917
ERROR errors check-bit error Multiple errors data-bit error decimal equivalent syndrome
Table 32-bit Syndrome Tables with Hex, Binary Decimal Equivalents.
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
ERROR
2917
ERROR errors check-bit error Multiple errors data-bit error decimal equivalent syndrome
Table 64-bit Syndrome Tables with Hex, Binary Decimal Equivalents.
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
DATA 1000F 1000 1000C 10003 10024 1002B 10027 10028 10022 1002D 10021 1002E 10009 10006 1000A 10005
DATA 10100 1010F 10103 1010C 1012B 10124 10128 10127 1012D 10122 1012E 10121 10106 10109 10105 1010A
DATA 10029 10026 1002A 10025 1002 1000D 10001 1000E 10004 1000B 10007 10008 1002F 10020 1002C 10023
DATA 10126 10129 10125 1012A 1010D 10102 1010E 10101 1010B 10104 10108 10107 10120 1012F 10123 1012C
2917
Table Minimal 32-check-bit data tables diagnostic use. data value listed generate every possible check-bit pattern.
DESIGNING WITH IDT49C460 IDT39C60 ERROR DETECTION CORRECTION UNITS
APPLICATION NOTE AN-24
DATA
DATA
DATA 10000 10001 10002 10003 10004 10005 10006 10007 10008 10009 1000A 1000B 1000C 1000D 1000E 1000F 10020 10021 10022 10023 10024 10025 10026 10027 10028 10029 1002A 1002B 1002C 1002D 1002E 1002F
DATA 10100 10101 10102 10103 10104 10105 10106 10107 10108 10109 1010A 1010B 1010C 1010D 1010E 1010F 10120 10121 10122 10123 10124 10125 10126 10127 10128 10129 1012A 1012B 1012C 1012D 1012E 1012F
2917
Table Minimal 32-bit data check-bit tables diagnostic use. least data value listed every possible check-bit pattern. This table identical Table except sequence presentation.
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