RISC Processor Market Overview Over past years, total volume 64-b

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RISC Processor Market Overview Over past years, total volume 64-b

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RISC Processor Market Overview
Over past years, total volume 64-bit RISC microprocessor shipments increased substantially. From 1995 1996, volume increased more than percent. 1996, more than million units were shipped1. Today, embedded market, which includes consumer electronics, browsers, internetworking equipment2, printers others, uses more than percent this volume. year 2000, industry will ship more than million units satisfy explosive growth consumer devices Internet systems. 1996 shipments MIPS®-based microprocessors alone were more than million units, more than triple previous year. Current MIPS licensees include Integrated Device Technology (IDT), NEC, NKK, QED, Sony, Logic, Philips Toshiba. these, primary broad line supplier off-the-shelf microprocessors embedded market. IDT's shipments have increased constantly since 1990, with volume tripling from 1995 1996. offers extensive line 64-bit MIPS-based RISC microprocessors having range price/performance levels accommodate various system requirements. IDT's 32-bit 64-bit microprocessor offerings very well suited internetworking equipment. They have very fast interrupt-response times combined with fast execution speeds large on-chip caches. These features make them ideal packet header analysis manipulation dynamic environment. These processors also have extremely fast internal external bandwidths, making them optimal power many internetworking systems where data flows continuously. Major internetworking equipment suppliers including Cisco Systems, Networks, NewBridge, Madge Networks, Yurie Systems, Extreme Networks Olicom employ microprocessors hearts their systems.
Recent Trends Internetworking Industry
internetworking industry very dynamic sense that standards, revisions features introduced regularly. computer power increased dramatically over past decade, applications have been introduced
"Muscle machines `90s: Review", Semico Research Corp., Tony Massimini, March 1997 term "internetworking industry" will used this document refer universe that constitutes internetworking equipment system providers well systems they design.
marketplace, users demanding much more bandwidth from "network" that driving these changes. example, internetworking industry seen move from shared-media hubs switches. These products provide user with wire's full bandwidth instead having share bandwidth with multiple users same wire. With advent switches, corporate data networks becoming more more complex. This complexity increase drives requirement allow professionals fully manage corporate network. current trend incorporate network management capability within switch. These known "managed switches." Wire speed also increasing. Ethernet transfers, example, have increased from Mbps Mbps, recently have reached 1000 Mbps (Gigabit Ethernet). concert with these trends, internetworking designers must constantly improve system price/performance meet exponential growth Internet sites, increase number users tend share more more resources. Specifically, system designers face several challenges: constantly increase number packets second (pps) system handle constantly reduce price port constantly improve functionality system incorporating emerging standards features simplify network management
These trends requirements demonstrate that internetworking systems static, rather, need constantly adapt newly emerging standards technology advances. achieve this flexibility, more functionality implemented software.
Ideal Microprocessor Internetworking Systems
meet described goals, microprocessors used heart internetworking systems must provide very fast interrupt-response time quick task switching efficiently handle dynamic pattern data traffic. Additionally, CPUs need execute extremely fast clock rates implement efficiently various complex network protocols network management routines. Internal external microprocessor bandwidth also very critical maintain overall system performance. internal external peak bandwidth must sustainable with large percentage -greater than percent-dedicated data accesses (minimal usage instruction accesses). Bringing data microprocessor very high speeds enables loading header data updating routing/switching tables into internal D-cache record times. Further, 64-bit internal microprocessor architecture enables transfer header between core internal caches about three clock cycles, allowing service more packets seconds. Finally, microprocessor must supported host support development tools enable quick design time verification, thus speeding time market.
Look IDT's Microprocessor Family
offers extensive line 32-bit 64-bit RISC microprocessors based MIPS architecture. 32-bit family currently based industry standard R3000, includes R3041TM, R3051TM, R3052TM, R3081and R36100TM. Each offers various levels on-chip instruction data caches, clock rates, memory management capability, system level integration other features. Table compares company's 32-bit microprocessors.
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64-bit family currently includes RV4640TM, RV4650TM, RV4700and RV5000TM. Each offers various levels on-chip caches, clock rates, memory management capability, capability, system width other features. Table illustrates differences among company's 64-bit microprocessors.
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Real-time Interrupt-Response
Most today's internetworking systems dynamic. This means that software executing continuous loop polling various ports sub-modules service them traditional systems. Instead, software constantly responding interrupts from sub-module needing service. This dynamic implementation frees software from constant polling enables execute other important tasks parallel. internetworking systems become more more complex, supporting network management features, higher wire speeds increased number ports, capability software switch tasks respond interrupt fast possible become elements. interrupt-response time then software performance system performance. interrupt-response time microprocessor includes more steps than just servicing exception, usually function underlying architecture microprocessor. interrupt-response mechanism characterized following five steps: Recognition exception: which microprocessor recognizes that interrupt pending. Preservation state: which microprocessor firmware saves state various registers cache main memory). Decoding exception: which microprocessor firmware determines which exception interrupt occurred needs serviced. Servicing exception: this step which exception routine does real work services pending exception. Restoring state: final step restore back state registers what they were before exceptions. this case microprocessor firmware reads back various registers from caches from main memory) into microprocessor registers.
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first three steps fifth directly influenced underlying architecture. IDT's 64-bit MIPS microprocessor families, microprocessor hardware recognizes exception automatically. firmware responsible preserving state, decoding exception finally restoring state microprocessor exception. Figure illustrates time takes microprocessor recognize exception processing required firmware. RV4700, executing MHz, completes four steps about R3081, executing MHz, completes four steps about This fast-interrupt response time 32-bit 64-bit microprocessor family enables designing interrupt-based systems.
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Execution Frequency
importance internetworking system's software constantly increasing. software's complexity involvement vary between system classes. example, software switches largely involved with overall switch management while actual switching LAN's traffic handled dedicated hardware such switching fabrics crossbar switches. software involved tasks such controlling hardware, setting switch configuration monitoring traffic. software also heavily involved network management routines tasks. router, other hand, software more involved data traffic flow tasks like making routing decisions, maintaining routing tables, running routing protocols executing network management routines.
Most switches implement network management protocols such simple Network Management Protocol (SNMP) Remote Monitoring (RMON) that enable professionals troubleshoot problems their networks. These protocols require great software bandwidth become part switch's critical performance path. Further, complexity these protocols increases with number ports switch. software must execute these routines fast efficiently possible. pipeline frequency thus directly related performance switch. IDT's 32-bit microprocessor family uses efficient 5-stage pipeline capable sustaining peak single-cycle execution rate without data dependencies instruction issue restrictions. Similarly, IDT's 64-bit family uses same efficient 5-stage pipeline capable sustaining peak single-cycle execution rate MHz. example, R3051 support first four groups RMON about ports Mbps each. RV4640 support ports Mbps each. Routers general require more "intelligence" than switches because they higher network hierarchy (operate network layer). example, software router involved with network management, routing table maintenance, packet address resolution other tasks. integral part packet routing/switching task. software look header, determine best route packet send complexity software increases with number ports supported, number different network layer protocols implemented, network management features incorporated wire speed interface various ports. pipeline frequency directly impacts performance router. Usually takes about 4003 instructions route forward packet, addition about transactions move data into CPU. R3081 route software eight ports Mbps each only consume about percent bandwidth. high-end routers, RV4700 route more than 200K software. trend architecture high-end routers divide workload among number line cards master card. line cards independent routers support more than million while aggregate bandwidth entire router about Gbps. line cards hardware software route data packets. Usually, line cards hardware elements optimized switch data packets Network Layer (L3) type network layer protocol like rest data packets (ones needing special attention ones that will still routed using microprocessor. microprocessor provides flexibility constantly adapt system standards implement features while hardware offers speed advantage. such implementations, hardware usually switch more than about million while still handle remaining 400K pps.
Importance Internal Caches
MIPS RISC architecture, internal primary caches tightly coupled execution core. caches play important role increasing overall performance reducing percentage time accesses external memory subsystem. Large internal instruction caches hold some critical performance sensitive routines, such routing code network management code, that have direct impact system performance make them always available execution core. Having these routines constantly available frees from contending local accesses main memory. Thus, more efficient bandwidth system performance obtained enabling system memory manipulate data traffic flow into system optimum way. Further, option lock some content cache very valuable software implementation some functions like Asoft SAR, soft modem, managing switching fabrics. Similarly, larger cache, lesser time spends accessing main memory. most internetworking systems, data cache holds local variables used various network management routines. router, cache stores part look-up table used routing/switching packet. RV5000 also direct access Level (L2) cache through dedicated port. rule thumb that system performance increases about percent when cache used.
estimates from system designers internetworking systems
Internal Bandwidth
software content complexity contemporary internetworking systems increases, CPU's internal bandwidth becomes major contributor overall system performance. When manipulating packets, analyzes packet header (usually available cache) make decision. During this operation, accesses data cache very frequently extract packet header, analyze access look-up table. Similarly, when gathering network statistics executing network management protocols, accesses data information from internal data cache. internal bandwidth (along with frequency size internal caches) direct effect performance manipulating packets number ports manage. internal bandwidth defined rate which execution core retrieve data instructions from caches write data back data cache. internal bandwidth then function width internal busses, speed which these busses operate access rates from cache. IDT's "Harvard" microprocessor architecture separate caches. internal buses always execute pipeline frequency. CPU, busses access time from caches match pipeline frequency. 32-bit microprocessor family, width registers internal data instruction busses bits. MHz, maximum peak bandwidth from data cache MBps. Figure illustrates internal architecture IDT's 32-bit microprocessor family.
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Value 64-bit Architecture
64-bit microprocessor architecture, width internal data registers bits while width instruction still bits. important note that MIPS architecture instructions always bits wide maintain compatibility with MIPS Instruction Architecture (ISA). Figure illustrates internal architecture 64-bit family. RV5000, instruction 64-bit because dual-issue needs read instructions every cycle.
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64-bit microprocessor family, width registers internal data bits. MHz, maximum peak bandwidth from data cache GBps. maximum peak bandwidth from cache half cache bandwidth GBps. cache accesses completely independent from cache accesses, interfere with bandwidth from cache. 64-bit wide data enables entire header packet transferred between data cache microprocessor register file using three clock cycles. router application, extracts manipulates header, reduces time-to-live count modifies checksum fewer instructions than 32-bit microprocessor architectures. 64-bit implements various search algorithms table look-up, such Patricia Tree algorithm, very efficiently. This enables compute next best address record times compared 32-bit microprocessors. 64-bit microprocessor architecture offers tremendous advantages over traditional 32-bit architectures. higher internal bandwidth, higher clock speed, faster interrupt-response time larger on-chip data instruction caches enable microprocessor manipulate packets record times. example, RV4700 makes routing decisions more than 200,000 pps. RV5000 executing makes routing decisions more than 350,000 software.
External Bandwidth
dynamic networking systems, data traffic constantly flowing through system. maintain wire speed manipulate/manage this traffic, must able access external memory fast possible. external bandwidth becomes major element total system's performance. will affect maximum number pps, number ports that manage.
external bandwidth rate which Interface Unit (BIU) retrieves/stores data from/to main memory. This function width external bus, speed which runs repetition rate. repetition rate over number clock cycles between each data element. 32-bit microprocessor family, external bits wide runs maximum. peak external bandwidth approximates MBps. 64-bit microprocessor family, external one-half one-eighth pipeline frequency. Depending actual microprocessor selected, external width could bits wide. with 64-bit operating MHz, external peak bandwidth MBps. running MHz, bandwidth MBps. large on-chip primary cache minimizes need access main program memory, enables larger percentage (usually greater than percent) external bandwidth dedicated data transfers. 64-bit enables transfer full packet header between internal data cache main memory with minimum number operations. This more efficient system since fewer cycles employed header transfer compared 32-bit external bus. unused cycle microprocessor optimized manipulate data traffic flow system without impacting CPU's performance.
Software Hardware Investment
Today, most internetworking system suppliers proprietary software differentiator their products. Changing software base from microprocessor architecture another daunting task. Since MIPS microprocessors softwarecompatible, software base maintained easily upgraded across several product platforms generations. This preserved investment software base enables faster product development, well upgrade existing products, reach market timely manner. IDT's extensive product offering allows system designers take advantage MIPS architecture their organization's whole product offering. Further, microprocessors maintain software compatibility across offerings other MIPS microprocessor vendors. offers multiple bus- pin-compatible microprocessors. Hardware design also leveraged across multiple systems similar that software investment preserved. example, system designed with low-end R3041 later upgraded higher performance using R3052 R3081 without requiring system modifications. 64-bit microprocessors protocol-compatible. This means that proprietary ASIC off-the-shelf system controller used with every member 64-bit family.
Price/Performance
Internetworking systems demand products various points along price/performance curve satisfy different needs information infrastructure. network hierarchy, price differentiator among variable offerings. high end, system performance element. meet internetworking industry needs, fields family 64-bit microprocessors falling over economic range price/performance points. Each suited particular class application. Figure lists entire catalog IDT's 32and 64-bit microprocessors, their relative price/performance levels. This extensive selection allows system designer choose best microprocessor requirements system being implemented, without making price and/or performance sacrifices. This flexibility enables system designer achieve desired price port every class internetworking system.
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Total System Solution
offers complete system solution (either directly from through third party vendor) internetworking suppliers, including: Hardware software development tools (compiler, debugger, logic analyzer,.) Evaluation boards support components Standard communications protocols (RMON, stack, AUNI,.) Actual working reference designs (Ethernet switch,
Summary
continuously enhancing performance devices, regularly introducing speed grades enhancements internal architecture. Some these "adds" include "prefetch" instruction implemention non-blocking load operation speed data movement capability CPU. These enhancements allow system designer continuously increase number packets seconds that system handle, incorporate features. offers extensive family 64-bit microprocessors based MIPS architecture. These devices wellsuited internetworking system applications. Fast interrupt-response times combined with fast execution speeds large onchip caches make them ideal packet header analysis manipulation. extremely fast internal external bandwidth makes them optimal heart various internetworking systems where data flows continuously. offers 64-bit microprocessors with price/performance points that service levels internetworking infrastructure. These devices software-compatible, preserving investment software across multiple platforms. Hardware compatibility also maintained within 32-bit family within 64-bit family, allowing hardware designs leveraged across multiple systems.

RISC Processor Market Overview Over past years, total volume 64-b

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