APPLICATION NOTE AN-201 IDT77305 RECEIVE MODE FAQ'S APPLICAT

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APPLICATION NOTE AN-201 IDT77305 RECEIVE MODE FAQ'S APPLICAT

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77305 RECEIVE MODE FAQ's
APPLICATION NOTE AN-201
IDT77305 RECEIVE MODE FAQ'S
APPLICATION NOTE AN-201
Integrated Device Technology, Inc.
Fred Santilo Question: When Cell Ready (CR[3:0]) output pins updated? Answer: CR[3:0] pins assert high clock cycle (WCLK) after last byte cell written FIFO port. CR[3:0] de-assert clock cycle (RCLK) before last word cell been read from FIFO port. Figure timing diagram. Figure Timing diagram CR[3:0] outputs
RCLK WCLK Data_A[8:0] CR-0 SOCS Q[17:0] Mux[2:1]
Question: When Load (LDM) intput when output? Answer:The input when IDT77305 Slave mode (MSE when device used Master mode (MSE with Round Robin Sequencer disabled (RRE output when device Master mode (MSE with Round Robin Sequencer enabled (RRE Table Truth Table Load input output input Master/Slave Master with without Slave Master with without Slave Slave
Question: When Mux1 Mux2 (Mux[2:1]) pins inputs when they outputs? Answer:The Mux[2:1] pins inputs when IDT77305 Slave mode (MSE when device used Master mode (MSE with Round Robin Sequencer disabled (RRE Mux[2:1] pins outputs when device Master mode (MSE with Round Robin Sequencer enabled (RRE Table Truth Table Mux[2:1] Mux[2:1] input output input Master/Slave Master with without Slave Master with without Slave Slave
logo registered trademark Integrated Device Technology, Inc. ©1997 Integrated Device Technology, Inc. 2/98
77305 RECEIVE MODE FAQ's
APPLICATION NOTE AN-201
Question: Load (LDM) Mux[2:1] pins work when Round Robin Sequencer disabled? Answer:LDM Mux[2:1] used select FIFO port when Round Robin Sequencer disabled (RRE polling device (Alayer) change address Mux(2:1) inputs during clock cycle(RCLK), FIFO port selected until asserted. Once known that polled FIFO port cell transfer, determined CR[3:0], address placed Mux[2:1] assterted same clock cycle (RCLK). asserted clock cycle after appropriate CR-n asserts high. asserted prior during CR-n assertion first word data will read until clock cycle (RCLK) after appropriate CR-n asserts. latch address asserted clock cycle (RCLK) after last word current cell transfered. This also assumes that appropriate CR-n asserted high FIFO port cell transfer. will ignored asserted prior last word current cell being transfered. There must cell FIFO port when asserted. Once asserted another FIFO port cannot selected until cell read from currently selected FIFO port. This prevents selection another FIFO port during cell transfer. Figure timing diagram. Figure Timing diagram Load Mux[2:1] inputs
RCLK WCLK Data_A[8:0] Data_B[8:0] CR-0 CR-1 SOCS Q[17:0] Mux[2:1]
Question: does cell size programming work IDT77305? Answer:Cell size programming accomplished with control pins Output Enable (OE) Reset (RST), input pins Cell Ready (CR[3:0]), Cell Size Selection (CSS), Cell Transfer (ECT) Cell Ready Composite (CRC). With de-asserted high asserted CR[3:0], CSS, pins cell size inputs. binaray value cell size programmed placed input pins loaded rising edge RST. order from CR-0, CR-1, CR-2, CR-3, CSS, CRC. default cell size bytes selected when asserted asserted low. default cell size also loaded rising edge RST. Figure timing diagram with example program byte cell size. When both de-asserted high CR[3:0], CSS, pins tri-stated. When asserted de-asserted high CR[3:0], CSS, pins outputs. Table cell size programming truth table. Table Truth Table Cell Size Programming Note values loaded rising edge Reset
Function CR[3:0], CSS, ECT, cell size inputs Selects default cell size bytes CR[3:0], CSS, ECT, tri-stated CR[3:0], CSS, ECT, outputs CR[3:0] then cell FIFO then cell FIFO asserts high with SOCS de-asserts last word cell then FIFO(s) cell then least FIFO cell
77305 RECEIVE MODE FAQ's
APPLICATION NOTE AN-201
Figure Timing diagram cell size programming Note values loaded rising edge
RCLK CR-0 (I/O) CR-1 (I/O) CR-2 (I/O) CR-3 (I/O) (I/O) (I/O) (I/O)
Question: does Cell Transfer (ECT) operate when output? Answer:ECT will assert high with SOCS first word output data. fourth last word cell will de-assert low. Figure Timing diagram Cell Transfer (ECT)
RCLK CR-0 SOCS
Q[17:0] Mux[2:1]
Question: read Round Robin Sequencer state machine diagram Figure IDT77305 data sheet? Answer:Please refer Figure next page. note section shows circle with bi-directional arrow pointing Inside circle LDM, Mux2 Mux1, arrow corresponds CLAV[3:0]. initial condition state machine LDM, Mux2, Mux1 CLAV[3:0] 0000. This condition corresponds circle diagram containing arrow containing 0000 pointing move around state machine choose appropriate CLAV[3:0] LDM, Mux2, Mux1 values. instance, initial values LDM, Mux2, Mux1 CLAV[3:0] 0000. next possible state machine actions LDM, Mux2, Mux1 CLAV[3:0] 0000, LDM, Mux2, Mux1 CLAV[3:0] 1000, LDM, Mux2, Mux1 CLAV[3:0] x100, LDM, Mux2, Mux1 CLAV[3:0] xx10, LDM, Mux2, Mux1 CLAV[3:0] xxx1.
77305 RECEIVE MODE FAQ's
APPLICATION NOTE AN-201
Figure Round Robin Sequencer state machine
00X1 XX1X XXXX 0000
XXXX
0010
0000
0001
XX10
X1XX
0XX1
X10X X10X XXX1
10XX 0X10
0000 100X 0000 1000 XXXX 1XXX X100 XXXX 0100
NOTE: Mux2 Mux1 CLAV
Initial condition Mux2, Mux1 Reset Reset CLAV3-0 0000

APPLICATION NOTE AN-201 IDT77305 RECEIVE MODE FAQ'S APPLICAT

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