3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
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IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.8mm pitch LFBGA package, balls Extended commercial range -40°C +85°C 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin
IDT74ALVCH32374 ADVANCE INFORMATION
DESCRIPTION:
This 32-bit edge-triggered D-type flip-flop built using advanced dual metal CMOS technology. This high-speed, low-power register ideal buffer register data synchronization storage. Output Enable (OE) clock (CLK) controls organized operate device four 8-bit registers, 16-bit registers, 32-bit register with common clock. Flow-through organization signal pins simplifies layout. inputs designed with hysteresis improved noise margin. ALVCH32374 been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ALVCH32374 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistor.
Drive Features ALVCH32374: High Output Drivers: ±24mA Suitable heavy loads
APPLICATIONS:
3.3V High Speed Systems 3.3V lower voltage computing systems
Functional Block Diagram
SEVEN OTHER CHANNELS
SEVEN OTHER CHANNELS
SEVEN OTHER CHANNELS
SEVEN OTHER CHANNELS
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4909/-
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
CONFIGURATION
32374
LFBGA TOPVIEW
BALL LFBGA PACKAGE ATTRIBUTES
Max. Nom. Min.
0.8mm
VIEW
5.5mm
13.5mm
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ABSOLUTE MAXIMUM RATING
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each
Unit
NEW16link
CAPACITANCE +25oC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NEW16link
Max. ±100
NOTE: applicable device type.
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
FUNCTION TABLE (each flip-flop)
Inputs xCLK Outputs
DESCRIPTION
Names xCLK Description Data Inputs(1) Clock Inputs 3-State Outputs 3-State Output Enable Inputs (Active LOW)
NOTE: These pins have "Bus-Hold." other pins standard inputs, outputs, I/Os.
NOTE: HIGH Voltage Level Voltage Level Don't Care High-Impedance LOW-to-HIGH Transition Level before indicated steady-state input conditions were established
1998 Integrated Device Technology, Inc.
DSC-123456
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: 40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Quiescent Power Supply Current Variation 2.3V, 18mA 3.3V 3.6V input 0.6V, other inputs Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Min. Typ.(1) Max. Unit
NEW16link
NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NEW16link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 3.0V 12mA 24mA Max. 0.55
NEW16link
Unit
2.3V 2.3V 2.7V 3.0V 3.0V Output Voltage 2.3V 3.6V 2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25oC
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
SWITCHING CHARACTERISTICS
2.5V 0.2V Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xCLK Output Enable Time Output Disable Time Setup Time, data before Hold Time, data after Pulse Duration, HIGH Output Skew(2) Min. Max. Min. 2.7V Max. 3.3V 0.3V Min. Max. Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
NEW16link
PHAS INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
ALVC Link
TEST CIRCUITS OUTPUTS
Pulse Generator
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT ITCH NORM ALLY CLOSE tPZH OUTPUT ITCH NORM ALLY OPEN HIGH LOAD tPLZ DISABLE LOAD
LOAD Open
D.U.T.
ALVC Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
ALVC Link NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
NEW16link
Open
OUTPUT SKEW INPUT
tPLH1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT tPLH2
PLH2
Link
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ORDERING INFORMATION
ALVC XXXX Device Type Package Range Bus-Hold
Low-Profile Fine Pitch Grid Array F96-1
32-Bit Edge Triggered D-Type Flip-Flop with 3-State Outputs 32-Bit Density with Resistors, ±24m
Bus-Hold -40°C +85°C
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