High performance 64-bit microprocessor, based RISCore4000 Minimized br

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High performance 64-bit microprocessor, based RISCore4000 Minimized br

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High performance 64-bit microprocessor, based RISCore4000 Minimized branch load delays, through streamlined 5-stage scalar pipeline. Single double precision floating-point unit peak MFLOP/s Dhrystone MIPS Flexible RC4700-compatible Joint on-chip, virtual-to-physical address mapping On-chip two-way associative caches 16KB instruction cache (I-cache) 16KB data cache (D-cache) Optional I-cache D-cache locking (per set), provides improved real-time support Enhanced, flexible interface allows simple, low-cost design 64-bit Interface option, 1000MB/s bandwidth support 32-bit Interface option, 500MB/s bandwidth support SDRAM timing protocol, through delayed data write cycles RC4000/RC5000 family bus-protocol compatibility runs fraction pipeline clock (1/2 1/8)
Implements MIPS-III Instruction Architecture (ISA) 3.3V with tolerant Software compatible with entire RISController Series Embedded Microprocessors Industrial temperature range support Active power management Powers down inactive units, through sleep-mode feature 100% compatibility between RC64474 RC4640 100% compatibility between RC64475 RC4650 RC64474 available 128-pin package, 32-bit only systems RC64475 available 208-pin package, full 64/32 systems Simplified board-level testing, through full Joint Test Action Group (JTAG) boundary scan Windows® compliant
MIPS 64-bit RISCore4000 Core System Control Coprocessor (CPO)
MFLOPS Single/Double Precision
Control Data Instruction
16KB Instruction Cache (Lockable)
32-/64-bit Synchronized System Interface
16KB Data Cache (Lockable)
logo registered trademark RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, RISCore trademarks Integrated Device Technology, Inc.
1998 Integrated Device Technology, Inc. DSC/4952
Implementation MIPS-III architecture results 64-bit operations, improved performance commonly used code sequences operating system kernels, faster execution floating-point intensive applications. RISCore4000 integer unit implements load/store architecture with single cycle operations (logical, shift, add, subtract) autonomous multiply/divide unit. consists integer adder logic unit. adder performs address calculations addition arithmetic operations, logic unit performs processor's logical shift operations. Each unit highly optimized perform operation single pipeline cycle. Both 64-bit data operations performed RISCore4000, utilizing general purpose 64-bit registers (GPR) that used integer operations address calculation. complete on-chip floating-point coprocessor (CP1), which includes floating-point register file execution units, forms "seamless" interface, decoding executing instructions parallel with integer unit. CP1's floating-point execution units support both single double precision arithmetic-as specified IEEE Standard 754- separated into multiply unit combined add/convert/ divide/square root unit. Overlap multiplies add/subtract supported, multiplier partially pipelined, allowing initiation multiply instruction every fourth pipeline cycle. floating-point register file made thirty-two 64-bit registers. floating-point unit take advantage 64-bit wide data cache issue co-processor load store doubleword instruction every cycle. RISCore4000's system control coprocessor (CP0) registers also incorporated on-chip provide path through which virtual memory system's page mapping examined changed, exceptions handled, operating mode selections controlled.
Extending Integrated Device Technology's (IDT) RISCore4000 based choices (see Table RC64474 RC64475 high performance 64-bit microprocessors targeted towards applications that require high bandwidth, real-time response rapid data processing ideal products ranging from internetworking equipment (switches, routers) multimedia systems such browsers, set-top boxes, video games, Windows®CE based products. Based IDT's RISCore4000, these processors rated Dhrystone MIPS Million floating point operations second, MHz. internal cache bandwidth these devices over 3GB/second. 64-bit external bandwidth more than 1000MB/s, 32-bit external bandwidth 500MB/s. RC64474 packaged 128-pin footprint package uses 32-bit external bus, offering ideal combination 64-bit processing power 32-bit low-cost memory systems. RC64475 packaged 208-pin footprint package uses full 64-bit external bus. RC64475 ideal applications requiring 64-bit performance 64-bit external bandwidth. IDT's RISCore4000 250MHz 64-bit execution core that uses 5-stage pipeline, eliminating "issue restrictions" associated with other more complex pipelines. RISCore4000 implements MIPS-III Instruction Architectue (ISA) upwardly compatible with applications that earlier generation parts.
Detailed system operation information provided RC64474/RC64475 user's manual.
Performance Caches External
64-bit RISCore4000 extensions >260MIPS mflops, single precision only 8kB/8kB, 2-way, lockable 32-bit
64-bit RISCore4000 extensions >260MIPS mflops, single precision only 8kB/8kB, 2-way, lockable 64-bit
64-bit RISCore4000 >260MIPS mflops, single double precision 16kB/16kB, 2-way 64-bit
64-bit RISCore4000 >330MIPS mflops, single double precision 16kB/16kB, 2-way, lockable 32-bit, Superset compatible w/RC4640 3.3V, tolerant 180-250 page Cache locking, JTAG, syncDRAM mode, 32bit external
64-bit RISCore4000 >330MIPS mflops, single double precision 16kB/16kB, 2-way, lockable 31-or 64-bit, Superset compatible RC4650 3.3V, tolerant 180-250 page Cache locking, JTAG, syncDRAM mode, 3264- option
Voltages Frequencies Packages Features
3.3V 100-200 PQFP Base-Bounds Cache locking, on-chip MAC, 32-bit external
3.3V 100-200 MQUAD Base-Bounds Cache locking, on-chip MAC, 32-bit option
3.3V 100-200 MQUAD page Large Primary caches
secure user processing environment provided through user, supervisor, kernel operating modes virtual addressing system software. Bits status register determine which these modes used. configured 64-bit virtual addressing, virtual address space layout becomes upwardly compatible extension 32-bit virtual address space layout. Figure illustration address space layout 32-bit virtual address operation.
0xFFFFFFFF 0xE0000000 0xDFFFFFFF
also contains information control cache coherency protocol each page. However, hardware-based cache coherency supported. RC64474 RC64475 enhance IDT's entire RISCore4000 series through implementation features such boundary scan, facilitate board level testing; enhanced support SyncDRAM, simplify system implementation improve performance; tolerant I/Os, enable interfacing with devices. RC64474/475 processors offer direct migration path designs based IDT's RC4640/RC4650 processors2, through full socket compatibility. Also, full 64-bit-family software busprotocol compatibility ensures RC64474/475 access existing market development infrastructure, allowing quicker time market.
Kernel virtual address space (kseg3) Mapped, 0.5GB Supervisor virtual address space (sseg) Mapped, 0.5GB Uncached kernel physical address space (kseg1) Unmapped, 0.5GB Cached kernel physical address space (kseg0) Unmapped, 0.5GB
0xC0000000 0xBFFFFFFF 0xA0000000 0x9FFFFFFF
array hardware software tools available assist system designers rapid development RC64474/475 based systems. This accessibility allows wide variety customers take full advantage device's high-performance features while addressing today's aggressive time-to-market demands.
0x80000000 0x7FFFFFFF
keep RC64474 RC64475's high-performance pipeline full operating efficiently, on-chip instruction data caches have been incorporated. Each cache data path accessed same single pipeline clock cycle. 16KB two-way associative instruction cache (I-cache) virtually indexed, physically tagged word parity protected. Because this cache virtually indexed, virtual-to-physical address translation occurs parallel with cache access, further increasing performance allowing both operations occur simultaneously. instruction cache provides peak instruction bandwidth 1000MB/sec 250MHz. 16KB two-way associative data cache (D-cache) byte parity protected fixed 32-byte (eight words) line size. protected with single parity bit. allow simultaneous address translation data cache access, D-cache virtually indexed physically tagged. data cache provide bytes each clock cycle, peak bandwidth 2GB/sec. lock critical sections code and/or data into caches quick access, "cache locking" feature been implemented. Once enabled, cache said locked when particular piece code data loaded into cache that cache location will selected later refill other data. This feature locks (8KB) Instruction and/or Data.
User virtual address space (useg) Mapped, 2.0GB
0x00000000
Figure Kernel Mode Virtual Addressing (32-bit Mode)
RC64474/RC64475's Memory Management Unit (MMU) controls virtual memory system's page mapping consists translation lookaside buffer (TLB) used virtual memorymapping sub-system. This large, fully associative maps virtual pages their corresponding physical addresses. organized pairs even-odd entries maps virtual address address space identifier into large, 64GB physical address space. assist controlling amount mapped space replacement characteristics various memory regions, mechanisms provided. First, page size configured per-entry basis, page size 16MB increments 4x). second mechanism controls replacement algorithm, when miss occurs. random replacement algorithm provided select entry written with mapping; however, processor provides mechanism whereby system specific number mappings locked into avoid being randomly replaced, which facilitates design real-time systems, allowing deterministic access critical software.
ensure socket compatibility, refer Table Table back data sheet.
handshake signals: RdRdy*, WrRdy*, ExtRqst*, Release*, Table lists RC64474/475 Instruction data cache ValidOut*, ValidIn*; interrupt inputs simple timing attributes. specification that capable transferring data between processor memory peak rate 1000MB/sec included Characteristics Instruction Data system interface. boot-time selectable option system interface 32-bits wide-using basically same protocols Size 16KB 16KB 64-bit system-is also supported. Organization 2-way 2-way boot-time mode control interface initializes fundamental associative associative processor modes. boot-time mode control interface serial interface that operates very frequency (MasterClock divided Line size 256). This low-frequency operation allows initialization inforread unit 32-bits 32-bits mation kept low-cost EPROM; alternatively, twenty-orso bits could generated system interface ASIC simple write policy write-back, write-through PAL. boot-time serial stream configuration options listed with without write-allocate Table page clocking interface allows easily mated with Line transfer order sub-block order, sub-block order, external reference clocks. input clock reference load load clock between 125MHz. on-chip phasesequential order, locked-loop (PLL) generates pipeline clock (PClock) through store multiplication system interface clock values 2,3,4,5,6,7 Miss restart entire line miss word defined system reset. This allows pipeline clock after transfer implemented significantly higher frequency than system interParity per-word per-byte face clock. RC64474/475 support single data (one eight bytes) 8-word block transfers SysAD bus. Cache locking RC64474/475 implement additional write protocols that double effective write bandwidth. write re-issue
repeat rate cycles write. Pipelined writes have same cycle write repeat rate issue additional write after WrRdy* de-asserts. Choosing 64-bit wide system interface dictates whether RC64475 supports 64-bit system interface that cache line block transaction requires double word data cycles compatible with RC4650 system interface. system inter- single word cycles well whether single data transfer-larger face consists 64-bit Address/Data with eight check bits than bytes-must divided into smaller transfers. 9-bit command that parity protected. Board-level testing during Run-Time mode facilitated through During 64-bit operation, RC64475 system address/data full JTAG boundary scan facility. pins-TDI, TDO, TMS, TCK, (SysAD) transfers protected with 8-bit parity check bus, TRST* JTAG32*-have been incorporated support stanSysADC. When initialized 32-bit operation, RC64475's dard JTAG interface. SysAD viewed 32-bit multiplexed that protected parity check bits. RC64474 supports 32-bit system interface3 that facilitate discrete interface SDRAM, RC64474/475 compatible with RC4640. During 32-bit operation, SysAD trans- interface enhanced with programmable delay that inserted fers performed 32-bit multiplexed (SysAD 0:31) that between write address write data, during write cycles (for protected parity check bits (SysADC 0:6). both block non-block writes). Writes external memory-whether they cache miss writeThe delay defined MasterClock cycles backs, stores uncached write-through addresses-use activated controlled through mode (17:15) settings selected on-chip write buffer. write buffer holds maximum four during reset initialization sequence. `000' setting provides addresses 64-bit data pairs. entire buffer used same write operations timing RC4640, RC4650, RC5000 data cache writeback allows processor proceed processors. parallel with memory updates.
More details
provided RC64474/475 user's guide.
Table lists boot-time mode stream.
Serial Description
Reserved Writeback data rate System interface data rate block writes only:
Serial Description
Clock Multiplier MasterClock multiplied internally generate PClock
Value Mode Setting
Clock multiplier: Multiply Multiply Multiply Multiply Multiply Multiply Multiply Reserved Little endian endian RC4x00 compatible Reserved pipelined writes write re-issue
Value Mode Setting
Must zero 64-bit: dddd ddxddx ddxxddxx dxdxdx ddxxxddxxx ddxxxddxxx dxxdxxdxxdxx ddxxxxxxddxxxxxx dxxxdxxxdxxxdxxx 9:15 Reserved 32-bit wwwwwwww wwxwwxwwxwwx wwxxwwxxwwxxwwxx wxwxwxwxwxwxwxwx wwxxxwwxxxwwxxxwwxxx wwxxxwwxxxwwxxxwwxxx wxxwxxwxxwxxwxxwxxwxxwxx 9:15 Reserved
EndBit Specifies byte ordering
10:9
Non-block write Selects nonblock write type. MSB.
TmrIntEn Disables timer interrupt Int*[5]
Enabled Timer Interrupt Disabled Timer Interrupt
System interface width Drv_Out output driver slew rate control. MSB. Affects only nonclock outputs.
64-bit system interface 32-bit system interface Output driver strength: 100% strength (fastest) strength strength strength (slowest)
14:13
17:15
WAdrWData_ Write address write data delay MasterClock cycles.
cycles cycle cycles cycles cycles cycles cycles cycles
255:18
Reserved
Must
Executing WAIT instruction enables processor enter Standby mode. internal clocks will shut down, thus freezing pipeline. PLL, internal timer, some input pins (Int[5:0]*, NMI*, ExtReq*, Reset*, ColdReset*) will continue run. Once Standby Mode, interrupt, including internally generated timer interrupt, will cause exit Standby Mode.
RC64474/475 guaranteed case temperature range +85° commercial temperature devices; +85° industrial temperature devices. type package, speed (power) device, airflow conditions affect equivalent ambient temperature conditions that will meet this specification.
equivalent allowable ambient temperature, calculated using thermal resistance from case ambient (CA) given package. following equation relates ambient case temperatures: where maximum power consumption temperature, calculated using maximum specification device. Typical values various airflows shown Table Note that RC64474/475 processors implement advanced power management, which substantially reduces typical power dissipation device.
Airflow (ft/min) 1000
following list system interface pins available RC64474/475. names ending with asterisk active when low.
Name System Interface ExtRqst* External request external agent asserts ExtRqst* request System interface. processor grants request asserting Release*. Release interface response assertion ExtRqst* read request, processor asserts Release* signals requesting device that system interface available. Read Ready external agent asserts RDRdy* indicate that accept processor read request. Write Ready external agent asserts WrRdy* when accept processor write request. Valid Input Signals that external agent driving valid address data SysAD valid command data identifier SysCmd bus. Valid output Signals that processor driving valid address data SysAD valid command data identifier SysCmd bus. System address/data 64-bit address data communication between processor external agent. During address phases only, SysAd(35:0) contains invalid address information. remaining SysAD(63:36) pins used. whole 64-bit SysAD(63:0) used during data transfer phase. 32-bit mode RC64474, SysAD(63:32) used, regardless Endianness. 32-bit address data communication between processor external agent performed SysAD(31:0). SysADC(7:0) System address/data check 8-bit containing parity check bits SysAD during data cycles. 32-bit mode RC64474, SysADC(7:4) used. SysADC(3:0) contains check bits SysAD(31:0). SysCmd(8:0) System command/data identifier 9-bit command data identifier transmission between processor external agent. System Command Parity single, even-parity Syscmd bus. This signal always driven low. Clock/Control Interface MasterClock Master Clock Master clock input establishes processor operating frequency. multiplied internally 2,3,4,5,6,7,8 generate pipeline clock (PClock). This clock must driven 3.3V (Vcc) clock signals, regardless tolerant setting. Quiet Quiet internal phase locked loop. Type Description
Release*
RdRdy*
WrRdy* ValidIn*
ValidOut*
SysAD(63:0)
SysCmdP
VCCP
Name VSSP Tolerant Type Description Quiet Quiet internal phase locked loop. Tolerant
This used convert ring RC4740/50 tolerant. pure 3.3V systems whreno sigas will driven CPU, this must driven with (3.3V). systems where RC4740/50 expected driven with signals, this input must driven with Interrupt Interface Int*(5:0) NMI* Initialization Interface VCCOk When asserted, this signal indicates processor that power supply been above minimum more than milliseconds will remain stable. assertion VCCOk initiates initialization sequence. Cold reset This signal must asserted power reset cold reset. ColdReset must deasserted synchronously with MasterClock. Reset This signal must asserted reset sequence. asserted synchronously asynchronously cold reset, synchronously initiate warm reset. Reset must de-asserted synchronously with MasterClock. Boot-mode clock Serial boot-mode data clock output system clock frequency divided hundred fifty-six. Boot-mode data Serial boot-mode data input. Interrupt general processor interrupts, bit-wise ORed with bits interrupt register. Non-maskable interrupt Non-maskable interrupt, ORed with interrupt register.
ColdReset*
Reset*
ModeClock
ModeIn JTAG Interface
JTAG Data rising edge TCK, serial input data shifted into either Instruction register Data register, depending controller state.
JTAG Data falling edge TCK, serial data shifted from either instruction data register. When data shifted out, tri-stated (high impedance).
Name Type JTAG Clock Input Description
input test clock used shift into boundary-scan register cells. independent system processor clock with nominal 40-60% duty cycle. JTAG Command Select logic signal received input decoded controller control test operation. sampled rising edge TCK. TRST* JTAG Reset TRST* active-low signal used asynchronous reset debug unit, independent processor logic. During normal operation, JTAG controller will held reset mode, asserting this active pin. When asserted low, this will also cause into tristate mode. JTAG32* JTAG 32-bit scan This used control length scan chanin SYsAD (32-bit 64-bit) JTAG mode. When Vss, 32-bit mode selected. this mode, only SysAD(31:0) part scan chain. When Vcc, 64-bit mode selected. this mode, SysAD(63:0) part scan chain. This built-in pull-down device guarantee 32-bit scan, left uncovered. JR_Vcc JTag This internal pull-down continuously reset JTAG controller left unconnected) bypassing TRst* pin. When supplied with Vcc, TRst* will primary control JTAG reset.
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Figure illustrates direction functional groupings processor signals.
Clock/Control Interface
MasterClock VCCP VSSP tolerant
SysAD(63:0) SysADC(7:0) SysCmd(8:0) SysCmdP
Interface Initialization TRST* JTAG JTag32* JR_Vcc
RC64474/ RC64475 Logic Symbol
VCCOK ColdReset* Reset* ModeClock ModeIn
System Interface Interrupt Interface Interface
RdRdy* WrRdy*
NMI* Int*(5:0)
ExtRqst* Handshake Signals Release* ValidIn* ValidOut*
Figure Logic Diagram RC64474/RC64475
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names followed asterisk active when low. maximum flexibility compatibility with future designs, N.C. pins should left floating.
N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SysAD11 SysCmd8 SysAD42 SysAD10 SysCmd7 SysAD41 SysAD9 SysCmd6 SysAD40 SysAD8 SysCmd5 SysADC4 SysADC0 SysCmd4 SysAD39 SysAD7 SysCmd3
JTAG32* N.C. N.C. N.C. SysCmd2 SysAD36 SysAD4 SysCmd1 SysAD35 SysAD3 SysCmd0 SysAD34 SysAD2 Int5* SysAD33 SysAD1 Int4* SysAD32 SysAD0 Int3* Int2* SysAD16 SysAD48 Int1* SysAD17
N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SysAD52 ExtRqst* SysAD21 SysAD53 RdRdy* Modein SysAD22 SysAD54 Release* SysAD23 SysAD55 NMI* SysADC2 SysADC6 SysAD24 SysAD56 SysAD25 SysAD57
N.C. N.C. SysAD59 ColdReset* SysAD28 SysAD60 Reset* SysAD29 SysAD61 SysAD30 SysAD62 SysAD31 SysAD63 VCCOK SysADC3 SysADC7 N.C. TRst* VCCP VSSP MasterClock SysADC5 SysADC1
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SysAD38 SysAD6 ModeClock WrRdy* SysAD37 SysAD5 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
SysAD49 Int0* SysAD18 SysAD50 ValidIn* SysAD19 SysAD51 ValidOut* SysAD20 N.C. N.C. N.C. N.C.
5VTolerant SysAD26 SysAD58 N.C. SysAD27 N.C. JR_Vcc N.C. N.C. N.C. N.C. N.C. N.C.
SysAD47 SysAD15 SysAD46 SysAD14 SysAD45 SysAD13 SysAD44 SysAD12 SysCmdP SysAD43 N.C.
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Function
JTAG32* SysCmd2 SysAD5 WrRdy* ModeClock SysAD6 SysCmd3 SysAd7 SysCmd4 SysAdC0
Function
Function
Function
SysAD28 ColdReset* SysAD27 JR_Vcc SysAD26 N.C. 5VTolerant SysAD25 SysAD24 SysADC2
SysAD13 SysAD14 SysAD15 SysADC1 MasterClock VssP VccP
SysAD19 ValidIn* SysAD18 Int0* SysAD17 Int1* SysAD16 Int2*
NMI* SysAD23 Release* SysAD22 Modein RdRdy* SysAD21 ExtRqst* SysAD20 ValidOut*
Function
SysCmd5 SysAD8 SysCmd6 SysAD9 SysCCmd7 SysAD10 SysCmd8 SysAD11 SysCmdP SysAD12
TRst*
Function
Function
Int3*
Function
SysAD0 Int4* SysAD1 Int5* SysAD2 SysCmd0 SysAd3 SysCmd1 SysAD4
SysADC3 VccOK SysAD31 SysAD30 SysAD29 Reset*
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ensure socket compatibility between RC4640 RC64474 devices, several changes required, shown below.
RC4640 N.C. RC64474 JTAG32* TRsT* JR_Vcc Tolerant Compatible RC4640? Yes. Yes. Yes. Yes. Yes. Yes. Yes. Yes. Comments internal pull-down, enable 32-bit scan. also left N.C. driven with Vss, JTAG needed. tristated when TRsT* low. driven with JTAG needed. driven with JTAG needed. driven with JTAG needed. driven with JTAG needed. left N.C. RC64474, JTAG need. JTAG needed, must driven Vcc. 3.3V systems, this must driven with 3.3V maintain full RC4640 compatibility. tolerant I/Os needed, then this must driven with which does maintain RC4640 compatibility.
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RC4650 32-bit N.C. RC64475 32-bit RC4650 64-bit JTAG32* N.C. RC64475 64-bit JTAG32* Compatible RC4640? Comments 32-bit, this left unconnected because internal pull-down. 64-bit, this assumes that JTAG will used. using JTAG, this must Vcc. 3.3V systems, this must driven with 3.3V maintain full RC4650 compsibility. tolerant needed, then this must driven with which does maintain RC4650 compatibility. RC64475, left N.C, JTAG need. JTAG needed, must driven Vcc. JTAG needed, left N.C. JTAG needed, left N.C. JTAG needed, left N.C. JTAG needed, left N.C. JTAG needed, left N.C.
5VTolerant
5VTolerant
N.C.
JR_Vcc
JR_Vcc
N.C. N.C. N.C. N.C. N.C.
TRsT*
N.C. N.C. N.C. N.C. N.C.
TRsT*
RC64474/475 3.3V±5% Symbol VTERM TBIAS TSTG IOUT Rating Terminal Voltage with respect Operating Temperature(case) Case Temperature Under Bias Storage Temperature Input Current Output Current Commercial -0.5(2) +125 +125 20(3) 50(4) +4.6 RC64474/475 3.3V±5% Industrial -0.5(2) +4.6 +125 +125 Unit
NOTES ABSOLUTE MAXIMUM RATING TABLE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. minimum -2.0V pulse width less than 15ns. should exceed +0.5 Volts. When more than output should shorted time. Duration short should exceed seconds.
RC64474/475 Grade Commercial Industrial Temperature +85°C (Case) 85°C (Case) 3.3V±5% 3.3V±5%
Commercial Temperature Range-RC64474/64475 (VCC 3.3± TCASE +85°C)
RC64474/RC64475 180MHz Parameter COUT I/OLEAK 0.1V 2.4V -0.5V 2.0V Minimum Maximum 0.1V 0.4V 0.2VCC 0.5V ±10uA 10pF 10pF 20uA 0.1V 2.4V -0.5V 2.0V RC64474/RC64475 200MHz Minimum Maximum 0.1V 0.4V 0.2VCC 0.5V ±10uA 10pF 10pF 20uA 0.1V 2.4V -0.5V 2.0V RC64474/RC64475 250MHz Minimum Maximum 0.1V 0.4V 0.2VCC 0.5V ±10uA 10pF 10pF 20uA Input/Output Leakage |IOUT|= Conditions |IOUT|= 20uA
RC64474 180MHz Parameter System Condition:
standby
RC64474 200MHz Typical(9) 200/50MHz 600mAb
RC64474 250MHz Typical(9) 250/62.5 850mA 1000mA 0pF(8) 50pF SysAd activity(8) 50pF R4x00 compatible writes, 25oC Conditions
Typical(9) 180/45MHz
active
630mAb
850mA
1000
1000mA
1200mA
50pF Pipelined writes write re-issue, 25oC(8)
These specifications tests insure compliance. These tested. They results engineering analysis provided reference only.
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RC64475 180MHz Parameter System Condition:
standby
RC64475 200MHz Typical(9) 200/50MHz 1000
RC64475 250MHz Typical(9) 0pF(8) 50pF SysAd activity(8) 50pF R4x00 compatible writes, 25oC Conditions
Typical(9)
180/45MHz
250/62.5MHz 1100
active,
64-bit optionc
1000
1000
1200
1100mAb
1360mAb
1000
1200
1200
1400
1360
1600
50pF Pipelined writes write re-issue, 25oC(8)
These specifications tests insure compliance. These tested. They results engineering analysis provided reference only. 32-bit option, RC64474 power consumption values.
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Cycle asterClock MCkHigh MCkLow
MCkP
SysAD,SysCmd Driven SysADC
SysAD,SysCmd Received SysADC
Control Signal driven ValidOut* Release* Control Signal received RdRdy* rRdy* ExtRqst* ValidIn* Int*(5:0)
Figure System Clocks Data Setup, Output, Hold timing
Notes diagram: tTCKlow tTCKHIGH tTCKFALL (reset pulse idth) TCKRise
Figure Standard JTAG timing
Commercial Temperature Range RC64474/RC64475 (VCC=3.3V TCASE +85°C)
RC64474/ RC64475 180MHz Parameter Pipeline clock Frequency MasterClock HIGH MasterClock MasterClock Frequency MasterClock Period Clock Jitter MasterClock MasterClock Rise Time MasterClock Fall Time ModeClock Period JTAG Clock Input JTAG Clock HIGH JTAG Clock JTAG Clock Rise Time JTAG Clock Fall Time Symbol PClk tMCHIGH tMCLOW
RC64474/ RC64475 200MHz
RC64474/ RC64475 250MHz ±250 256*
tMCP
Test Conditions Transition Transition
±250 256*
tMCP
Units
tMCP tJitterIn tMCRise tMCFall
tModeCKP
11.1
±250 256*
tTCK tTCKHIGH tTCKLOW tTCKRise tTCKFall
NOTES RC64474/475 AC/DC ELECTRICAL CHARACTERISTIC TABLES: Operation RC64474/RC64475 only guaranteed with Phase Lock Loop enabled. Timings measured from 1.5V clock 1.5V signal. Capacitive load output timings 50pF. Guaranteed design. Typical integer instruction cache miss rates.
Capacitive load deration-RC64474/RC64475
180MHz Parameter Load Derate Symbol Test Conditions 200MHz 250MHz Units ns/25pF
RC64474/ RC64475 180MHz Parameter Data Output(7) Symbol tDM= tDOH* Test Conditions mode14.13 (fastest) mode14.13 (slowest) mode14.13 (fastest) trise tfall RC64474/ RC64475 200MHz 1.0(8) 2.0(8) RC64474/ RC64475 250MHz 1.0(8) 2.0(8) Units
Data Output Hold Data Setup Data Hold
50pf loading external output signals, fastest settings. Also applies JTAG signals (TRST*,TDO,TDI,TMS)
RC64474/ RC64475 Parameter Mode Data Setup Mode Data Hold Symbol RC64474/ RC64475 RC64474/ RC64475 250MHz Units Master Clock Cycle Master Clock Cycle
MasterClock (MClk) ColdReset* Reset*
ModeBit[9:0] MClk cycles
Figure Mode Configuration Interface Reset Sequence
+4mA
VREF
+1.5V
Device Under Test
-4mA
Signal
Signals
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RC64475 available 208-pin power quad (PQUAD) package.
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NOTES: DIMENSIONS MILLIMETERS. SYMBOLS D1/E1 3.50 3.17 31.00 27.59 3.86 3.43 31.40 27.79
TOLERANCES UNLESS OTHERWISE SPECIFIED FRAC ANGLES
Integrated Device Technology, Inc.
3001 Stender Way, Santa Clara, 95054
(408) 492-8333 (408) 727-2328
APPROVALS DRAWN CHECKED
DATE
11/95
SCALE
MQUAD RMKT (.80 PITCH, GULLWING)
SIZE DRAWING
PSC-4054
SHEET
SCALE DRAWING
IDT79RCXX Product Type Operating Voltage XXXX Device Type Speed Package Temp range/ Process
Blank
Commercial Temperature Case) Industrial Temperature Case)
128-pin 208-pin PClk PClk PClk
Embedded Processor
79RC64
3.3V +/-5% 64-bit Embedded Microprocessor
IDT79RC64V474 180, 200, IDT79RC64V475 180, 200, IDT79RC64V474 180, 200, IDT79RC64V474 180, 200, 128-pin package, Commercial Temperature 208-pin package, Commercial Temperature 128-pin package, Industrial Temperature 208-pin package, Industrial Temperature
Integrated Device Technology, Inc.
2975 Stender Way, Santa Clara, 95054-3090 Telephone: (408) 727-6116 (408) 492-8674

High performance 64-bit microprocessor, based RISCore4000 Minimized br

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