True Dual-Ported memory cells which allow simultaneous reads same memo

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True Dual-Ported memory cells which allow simultaneous reads same memo

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HIGH-SPEED 3.3V DUAL-PORT STATIC
True Dual-Ported memory cells which allow simultaneous reads same memory location High-speed access Commercial: 25/35/55ns (max.) Low-power operation IDT70V25S Active: 230mW (typ.) Standby: 3.3mW (typ.) IDT70V25L Active: 230mW (typ.) Standby: 660µW (typ.) Separate upper-byte lower-byte control multiplexed compatibility IDT70V25 easily expands data width bits more
IDT70V25S/L
using Master/Slave select when cascading more than device BUSY output flag Master BUSY input Slave BUSY Interrupt Flag On-chip port arbitration logic Full on-chip hardware support semaphore signaling between ports Fully asynchronous operation from either port LVTTL-compatible, single 3.3V (±0.3V) power supply Available 84-pin PGA, 84-pin PLCC 100-pin TQFP Industrial temperature range (-40°C +85°C) available selected speeds
Functional Block Diagram
R/WL R/WR
I/O8L-I/O15L I/O0L-I/O7L BUSYL
(1,2)
I/O8R-I/O15R Control Control I/O0R-I/O7R BUSYR(1,2) Address Decoder
A12L
MEMORY ARRAY
Address Decoder
A12R
R/WL SEML INTL(2)
NOTES: (MASTER): BUSY output; (SLAVE): BUSY input. BUSY outputs outputs non-tri-stated push-pull.
ARBITRATION INTERRUPT SEMAPHORE LOGIC
R/WR SEMR INTR(2)
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AUGUST 1999
DSC-2944/7
©1999 Integrated Device Technology, Inc.
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
IDT70V25 high-speed Dual-Port Static RAM. IDT70V25 designed used stand-alone Dual-Port combination MASTER/SLAVE Dual-Port 32-bit wider memory system applications results full-speed, error-free operation without need additional discrete logic. This device provides independent ports with separate control, address, pins that permit independent, asynchronous access
Description
reads writes location memory. automatic power down feature controlled permits on-chip circuitry each port enter very standby power mode. Fabricated using IDTs CMOS high-performance technology, these devices typically operate only 230mW power. IDT70V25 packaged ceramic 84-pin PGA, 84-Pin PLCC 100-pin Thin Quad Flatpack.
Configurations(1,2,3)
I/O3L I/O2L I/O1L I/O0L R/WL I/O5L I/O4L I/O7L I/O6L SEML A12L A11L A10L
INDEX
I/O8L I/O9L I/O10L I/O11L I/O12L I/O13L I/O14L I/O15L I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R
INTL BUSYL BUSYR INTR
IDT70V25J J84-1(4) 84-Pin PLCC View(5)
I/O14R I/O15R
SEMR
A12R A11R
A10R
R/WR
I/O9R
I/O12R
I/O13R
I/O10R I/O11R
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6.42
I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R R/WR SEMR A12R A11R A10R
NOTES: pins must connected power supply. pins must connected ground supply. J84-1 package body approximately 1.15 1.15 PN100-1 package body approximately 14mm 14mm 1.4mm. This package code used reference package diagram. This text does indicate orientation actual part marking.
I/O10L I/O11L I/O12L I/O13L I/O14L I/O15L I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
1100
I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L I/O1L I/O0L R/WL SEML A12L A11L A10L
IDT70V25PF PN100-1(4) 100-Pin TQFP View(5)
Index
INTL BUSYL BUSYR INTR 2944
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Configurations(1,2,3) (con't.)
I/O7L
I/O5L
I/O4L
I/O2L
I/O0L
SEML
A11L
A10L
I/O10L
I/O8L
I/O6L
I/O3L
I/O1L
A12L
I/O11L
I/O9L
R/WL
I/O13L
I/O12L
I/O15L
I/O14L
BUSYL IDT70V25G G84-3(4) 84-Pin View(5)
INTL
I/O0R
I/O1R
I/O2R
INTR
BUSYR
I/O3R
I/O4R
I/O5R
I/O7R
SEMR
I/O6R
I/O9R
I/O10R
I/O13R
I/O15R
R/WR
A11R
I/O8R
I/O11R
I/O12R
I/O14R
A12R
A10R
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Index
NOTES: pins must connected power supply. pins must connected ground supply. Package body approximately 1.12 1.12 This package code used reference package diagram. This text does indicate orientation actual part marking.
Names
Left Port R/WL A12L I/O0L I/O15L SEML INTL BUSYL R/WR A12R I/O0R I/O15R SEMR INTR BUSYR Right Port Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag Master Slave Select Power Ground
2944
Names
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Truth Table Non-Contention Read/Write Control
Inputs(1) 8-15 High-Z High-Z DATAIN High-Z DATAIN DATA High-Z DATA High-Z Outputs I/O0-7 High-Z High-Z High-Z DATA DATA High-Z DATAOUT DATAOUT High-Z Mode Deselected: Power Down Both Bytes Deselected Write Upper Byte Only Write Lower Byte Only Write Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled
2944
NOTE: A12L A12R
Truth Table Semaphore Read/Write Control(1)
Inputs 8-15 DATAOUT DATAOUT DATAIN DATAIN
Outputs DATA DATA DATAIN DATAIN
Mode Read Data Semaphore Flag Read Data Semaphore Flag Write DIN0 into Semaphore Flag Write DIN0 into Semaphore Flag Allowed Allowed
2944
NOTE: There eight semaphore flags written I/O0 read from I/O's (I/O0-I/O15). These eight semaphores addressed A0-A2.
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect Temperature Under Bias Storage Temperature Output Current Commercial Industrial -0.5 +4.6 Unit
Maximum Operating Temperature Supply Voltage(1,2)
Grade Commercial Ambient Temperature +70OC
3.3V 0.3V 3.3V 0.3V
2944
TBIAS TSTG IOUT
+125 +125
Industrial
2944
NOTES: This parameter Industrial temperature: specific speeds, packages powers contact your sales office.
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. VTERM must exceed 0.3V.
Recommended Operating Conditions
Symbol Parameter Supply Voltage Ground Input High Voltage Input Voltage Min. -0.5(1) Typ.
Max. VCC+0.3
Unit
2944
Capacitance(1) +25°C, 1.0MHz)
Symbol COUT Parameter Input Capacitance Output Capacitance Conditions(2) VOUT Max. Unit
2944
NOTES: -1.5V pulse width less than 10ns. VTERM must exceed 0.3V.
NOTES: This parameter determined device characterization production tested. references interpolated capacitance when input output signals switch from from
Electrical Characteristics Over Operating Temperature Supply Voltage Range (VCC 3.3V 0.3V)
70V25S Symbol |ILI| |ILO| Parameter Input Leakage Current(1) Output Leakage Current Output Voltage Output High Voltage Test Conditions 3.6V, VIH, VOUT +4mA -4mA Min.
70V25L Min.
Max.
Max.
Unit
2944
NOTE: 2.0V input leakages undefined.
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range(1,6) (VCC 3.3V 0.3V)
70V25X25 Com'l Only Symbol Parameter Dynamic Operating Current (Both Ports Active) Test Condition VIL, Outputs Open fMAX(3) Version COM'L COM'L COM'L COM'L COM'L Typ.
70V25X35 Com'l Only Typ.(2)
70V25X55 Com'l Only Typ.
Max.
Max.
Max.
Unit
ISB1
Standby Current (Both Ports Level Inputs)
SEMR SEML fMAX(3)
ISB2
Standby Current (One Port Level Inputs)
VIH(5) Active Port Outputs Open, f=fMAX(3) SEMR SEML Both Ports 0.2V, 0.2V 0.2V, 0(4) SEMR SEML 0.2V Port 0.2V(5) SEMR SEML 0.2V 0.2V 0.2V Active Port Outputs Open, fMAX(3)
ISB3
Full Standby Current (Both Ports CMOS Level Inputs)
ISB4
Full Standby Current (One Port CMOS Level Inputs)
NOTES: part number indicates power rating 3.3V, +25°C, production tested. 70mA (typ.) fMAX, address control lines (except Output Enable) cycling maximum frequency read cycle 1/tRC, using Test Conditions input levels means address control lines change. Port either left right port. Port opposite from port "A". Industrial temperature: specific speeds, packages powers contact your sales office.
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Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 3.0V Max. 1.5V 1.5V Figures
2944
3.3V DATAOUT BUSY DATAOUT 30pF
3.3V
5pF*
2944
Figure Output Test Load
Figure Output Test Load (For tHZ, tWZ, tOW) *Including scope jig.
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range(4,5)
70V25X25 Com'l Only Symbol READ CYCLE tACE tABE tAOE tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time(3) Byte Enable Access Time
70V25X35 Com'l Only Min. Max.
70V25X55 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
2944
Output Enable Access Time Output Hold from Address Change Output Low-Z Time(1,2) Output High-Z Time(1,2) Chip Enable Power Time
Chip Disable Power Down Time(2) Semaphore Flag Update Pulse SEM) Semaphore Address Access Time
NOTES: Transition measured ±200mV from High-impedance voltage with Output Test Load (Figure This parameter guaranteed device characterization, production tested. access RAM, VIL, VIL, VIH. access semaphore, VIL. part number indicates power rating Industrial temperature: specific speeds, packages powers contact your sales office.
Timing Power-Up Power-Down
2944
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Waveform Read Cycles(5)
ADDR tACE tAOE tABE
DATAOUT
VALID DATA
BUSYOUT
(3,4)
NOTES: Timing depends which signal asserted last, Timing depends which signal de-asserted first, tBDD delay required only case where opposite port completing write operation same address location simultaneous read operations BUSY relation valid output data. Start valid data depends which timing becomes effective last tABE, tAOE, tACE tBDD VIH.
tBDD
2944
Electrical Characteristics Over Operating Temperature Supply Voltage (5,6)
70V25X25 Com'l Only Symbol WRITE CYCLE tSWRD tSPS Write Cycle Time Chip Enable End-of-Write Address Valid End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid End-of-Write Output High-Z Time Data Hold Time
(1,2)
70V25X35 Com'l Only Min. Max.
70V25X55 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
2944
Write Enab Output High-Z(1,2) Output Active from End-of-Write (1,2,4) Flag Write Read Time Flag Contention Window
NOTES: Transition measured ±200mV from High-impedance voltage with Output Test Load (Figure This parameter guaranteed device characterization, production tested. access SRAM, VIL, VIL, VIH. access semaphore, VIH, VIL. Either condition must valid entire time. specification must device supplying write data SRAM under operating conditions. Although values will vary over voltage temperature, actual will always smaller than actual tOW. part number indicates power rating Industrial temperature: specific speeds, packages powers contact your sales office.
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Timing Waveform Write Cycle Controlled Timing(1,5,8)
ADDRESS
DATAOUT
DATAIN
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Timing Waveform Write Cycle Controlled Timing(1,5)
ADDRESS
DATAIN
2944
NOTES: must HIGH during address transitions. write occurs during overlap (tEW memory array writing cycle. measured from earlier R/W) going HIGH end-of-write cycle. During this period, pins output state input signals must applied. transition occurs simultaneously with after transition outputs remain HIGH-impedance state. Timing depends which enable signal asserted last, R/W, This parameter guaranteed device characterization, production tested. Transition measured ±200mV from steady state with Output Test Load (Figure during controlled write cycle, write pulse width must larger (tWZ allow drivers turn data placed required HIGH during controlled write cycle, this requirement does apply write pulse short specified tWP. access RAM, VIL, VIL, VIH. access Semaphore, VIH, VIL. must either condition.
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Timing Waveform Semaphore Read after Write Timing, Either Side(1)
tSAA A0-A2 VALID ADDRESS DATAIN VALID tSWRD
Write Cycle Read Cycle
2944
VALID ADDRESS tACE tSOP DATAOUT VALID(2)
I/O0
tAOE
NOTES: duration above timing (both write read cycle). DATAOUT VALID represents I/O's (I/O0-I/O15 equal semaphore value.
Timing Waveform Semaphore Write Contention(1,3,4)
A0"A"-A2"A" MATCH
SIDE
R/W"A"
SEM"A" tSPS A0"B"-A2"B" MATCH
SIDE
R/W"B"
SEM"B"
NOTES: VIL, VIH, both VIH. timing same left right port. Port either left right port. Port opposite from port This parameter measured from R/W"A" going HIGH R/W"B" SEM"B" going HIGH. tSPS satisfied, there guarantee which side will obtain semaphore flag.
2944
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range(6,7)
70V25X25 Com'l Only Symbol BUSY TIMING (M/S VIH) tBAA tBDA tBAC tBDC tAPS tBDD BUSY Access Time from Address Match BUSY Disable Time from Address Matched BUSY Access Time from Chip BUSY Disable Time from Chip High Arbitration Priority Set-up Time BUSY Disable Valid Data Write Hold After BUSY
70V25X35 Com'l Only Min. Max.
70V25X55 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
BUSY INPUT TIMING (M/S VIL) BUSY Input Write Write Hold After BUSY
PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse Data Delay Write Data Valid Read Data Delay
2944
NOTES: Port-to-port delay through SRAM cells from writing port reading port, refer "TIMING WAVEFORM WRITE PORT-TO-PORT READ BUSY (M/S VIH)". ensure that earlier ports wins. tBDD calculated parameter greater tWDD (actual) tDDD (actual). ensure that write cycle inhibited during contention. ensure that write cycle completed after contention. part number indicates power rating Industrial temperature: specific speeds, packages powers contact your sales office.
Timing Waveform Write Port-to-Port Read BUSY(2,4,5) (M/S VIH)
ADDR"A" MATCH R/W"A" DATAIN tAPS ADDR"B" tBAA BUSY"B" tWDD DATAOUT
VALID
VALID
MATCH tBDA tBDD
NOTES: ensure that earlier ports wins. tAPS ignored (slave). VIL. reading port. (slave), BUSY input. Then this example BUSYA BUSYB input shown above. timing same both left right ports. Port either left right port. Port port opposite from port
tDDD
2944
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Timing Waveform Write with BUSY
R/W"A" BUSY"B"
R/W"B"
NOTES: must both master BUSY input (slave) output (master). BUSY asserted port blocking R/W"B", until BUSY"B" goes HIGH. only slave version.
2944
Waveform BUSY Arbitration Controlled Timing(1) (M/S VIH)
ADDR"A" ADDRESSES MATCH
CE"A" tAPS CE"B" tBAC BUSY"B"
2944
tBDC
Waveform BUSY Arbitration Cycle Controlled Address Match Timing(1) (M/S VIH)
ADDR"A" tAPS ADDR"B" tBAA BUSY"B"
2944
ADDRESS
MATCHING ADDRESS tBDA
NOTES: timing same left right ports. Port either left right port. Port port opposite from tAPS satisfied, BUSY signal will asserted side another there guarantee which side BUSY will asserted.
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range(1,2)
70V25X25 Com'l Only Symbol INTERRUPT TIMING tINS tINR Address Set-up Time Write Recovery Time Interrupt Time Interrupt Reset Time
70V25X35 Com'l Only Min. Max.
70V25X55 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
2944
NOTES: part number indicates power rating Industrial temperature: specific speeds, packages powers contact your sales office.
Waveform Interrupt Timing(1)
ADDR"A" CE"A"
INTERRUPT ADDRESS
R/W"A" tINS INT"B"
2944
ADDR"B" tAS(3) CE"B" INTERRUPT CLEAR ADDRESS
OE"B" tINR INT"B"
2944
NOTES: timing same left right ports. Port either left right port. Port port opposite from Interrupt Flag Truth Table III. Timing depends which enable signal R/W) asserted last. Timing depends which enable signal R/W) de-asserted first.
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Truth Table Interrupt Flag(1)
Left Port R/WL A12L-A0L 1FFF 1FFE INTL L(3)
Right Port R/WR A12R-A0R 1FFF 1FFE INTR L(2)
Function Right INTR Flag Reset Right INTR Flag Left INTL Flag Reset Left INTL Flag
2944
NOTES: Assumes BUSYL BUSYR VIH. BUSY VIL, then change. BUSY VIL, then change.
Truth Table Address BUSY Arbitration
Inputs A12L-A0L A12R -A0R MATCH MATCH MATCH MATCH Outputs BUSYL(1) BUSYR(1) Function Normal Normal Normal Write Inhibit(3)
2944
NOTES: Pins BUSYL BUSYR both outputs when part configured master. Both inputs when configured slave. BUSY outputs IDT70V25 push pull, open drain outputs. slaves BUSY input internally inhibits writes. inputs opposite port were stable prior address enable inputs this port. inputs opposite port became stable after address enable inputs this port. tAPS met, either BUSYL BUSYR will result. BUSY BUSYR outputs cannot simultaneously. Writes left port internally ignored when BUSYL outputs driving regardless actual logic level pin. Writes right port internally ignored when BUSYR outputs driving regardless actual logic level pin.
Truth Table Example Semaphore Procurement Sequence(1,2,3)
Functions Action Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Left Right Semaphore free Left port semaphore token change. Right side write access semaphore Right port obtains semaphore token change. Left port write access semaphore Left port obtains semaphore token Semaphore free Right port semaphore token Semaphore free Left port semaphore token Semaphore free
2944
Status
NOTES: This table denotes sequence events only eight semaphores IDT70V25. There eight semaphore flags written I/O0 read from I/O's (I/O0-I/O15). These eight semaphores addressed A0-A2. VIH, access semaphores. Refer Semaphore Read/Write Control Truth Tables.
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
MASTER Dual Port BUSYL
BUSYR
SLAVE Dual Port BUSYR BUSYL
BUSYL
MASTER Dual Port BUSYR BUSYL
SLAVE Dual Port BUSYR BUSYL
BUSYR
2944
Figure Busy chip enable routing both width depth expansion with IDT70V25 RAMs.
IDT70V25 provides ports with separate control, address pins that permit independent access reads writes location memory. IDT70V25 automatic power down feature controlled controls on-chip power down circuitry that permits respective port into standby mode when selected HIGH). When port enabled, access entire memory array permitted.
Functional Description
write operations prevented port tying BUSY that port LOW. BUSY outputs 70V25 master mode, push-pull type outputs require pull resistors operate. these RAMs being expanded depth, then BUSY indication resulting array requires external gate.
user chooses interrupt function, memory location (mail message center) assigned each port. left port interrupt flag (INTL) asserted when right port writes memory location 1FFE (HEX), where write defined R/WR Truth Table III. left port clears interrupt address location 1FFE access when VIL, R/WL "don't care". Likewise, right port interrupt flag (INTR) when left port writes memory location 1FFF (HEX) clear interrupt flag (INTR), right port must read memory location 1FFF. message bits) 1FFE 1FFF user-defined, since addressable SRAM location. interrupt function used, address locations 1FFE 1FFF used mail boxes, part random access memory. Refer Truth Table interrupt operation.
Interrupts
Busy Logic provides hardware indication that both ports SRAM have accessed same location same time. also allows accesses proceed signals other side that SRAM busy. BUSY then used stall access until operation other side completed. write operation been attempted from side that receives BUSY indication, write signal gated internally prevent write from proceeding. BUSY logic required desirable applications. some cases useful logically BUSY outputs together BUSY indication interrupt source flag event illegal illogical operation. write inhibit function BUSY logic desirable, BUSY logic disabled placing part slave mode with pin. Once slave mode BUSY operates solely write inhibit input pin. Normal operation programmed tying BUSY pins HIGH. desired, unintended
Busy Logic
When expanding IDT70V25 array width while using BUSY logic, master part used decide which side SRAM array will receive BUSY indication, output that indication. number slaves addressed same address range master, BUSY signal write inhibit signal. Thus IDT70V25 SRAM BUSY output part used master (M/S VIH), BUSY input part used slave (M/S VIL) shown Figure more master parts were used when expanding width, split decision could result with master indicating BUSY side array another master indicating BUSY other side array. This would inhibit write operations from port part word inhibit write operations from other port other part word. BUSY arbitration, master, based chip enable address signals only. ignores whether access read write. master/slave array, both address chip enable must valid long enough BUSY flag output from master before actual write pulse initiated with either signal byte enables. Failure observe this timing result glitched internal write inhibit signal corrupted data slave.
Width Expansion with Busy Logic Master/Slave Arrays
IDT70V25 extremely fast Dual-Port CMOS Static with additional address locations dedicated binary semaphore flags. These flags allow either processor left right side Dual-Port SRAM claim privilege over other processor functions defined system designers software. example, semaphore used processor inhibit other from accessing portion Dual-Port SRAM other
Semaphores
6.42
DECODER
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
shared resource. Dual-Port SRAM features fast access time, both ports completely independent each other. This means that activity left port slows access time right port. Both ports identical function standard CMOS Static accessed same time with only possible conflict arising from simultaneous writing simultaneous READ/WRITE non-semaphore location. Semaphores protected against such ambiguous situations used system program avoid conflicts non-semaphore portion Dual-Port SRAM. These devices have automatic power-down feature controlled Dual-Port SRAM enable, SEM, semaphore enable. pins control on-chip power down circuitry that permits respective port into standby mode when selected. This condition which shown Truth Table where both HIGH. Systems which best IDT70V25 contain multiple processors controllers typically very high-speed systems which software controlled software intensive. These systems benefit from performance increase offered IDT70V25's hardware semaphores, which provide lockout mechanism without requiring complex programming. Software handshaking between processors offers maximum system flexibility permitting shared resources allocated varying configurations. IDT70V25 does semaphore flags control resources through hardware, thus allowing system designer total flexibility system architecture. advantage using semaphores rather than more common methods hardware arbitration that wait states never incurred either processor. This prove major advantage very high-speed systems.
semaphore logic eight latches which independent Dual-Port SRAM. These latches used pass flag, token, from port other indicate that shared resource use. semaphores provide hardware assist assignment method called Token Passing Allocation. this method, state semaphore latch used token indicating that shared resource use. left processor wants this resource, requests token setting latch. This processor then verifies success setting latch reading successful, proceeds assume control over shared resource. successful setting latch, determines that right side processor latch first, token using shared resource. left processor then either repeatedly request that semaphores status remove request that semaphore perform another task occasionally attempt again gain control token test sequence. Once right side relinquished token, left side should succeed gaining control. semaphore flags active LOW. token requested writing zero into semaphore latch released when same side writes that latch. eight semaphore flags reside within IDT70V25 separate memory space from Dual-Port SRAM. This address space accessed placing input (which acts
Semaphore Flags Work
chip select semaphore flags) using other control pins (Address, R/W) they would used accessing standard static RAM. Each flags unique address which accessed either side through address pins When accessing semaphores, none other address pins effect. When writing semaphore, only data used. level written into unused semaphore location, that flag will zero that side other side (see Truth Table That semaphore only modi-fied side showing zero. When written into same location from same side, flag will both sides (unless semaphore request from other side pending) then written both sides. fact that side which able write zero into semaphore subsequently locks writes from other side what makes semaphore flags useful interprocessor communications. thorough discussion this feature follows shortly.) zero written into same location from other side will stored semaphore request latch that side until semaphore freed first side. When semaphore flag read, value spread into data bits that flag that reads data bits flag containing zero reads zeros. read value latched into sides output register when that side's semaphore select (SEM) output enable (OE) signals active. This serves disallow semaphore from changing state middle read cycle write cycle from other side. Because this latch, repeated read semaphore test loop must cause either signal (SEM inactive output will never change. sequence WRITE/READ must used semaphore order guarantee that system level contention will occur. processor requests access shared resources attempting write zero into semaphore location. semaphore already use, semaphore request latch will contain zero, semaphore flag will appear one, fact which processor will verify subsequent read (see Truth Table example, assume processor writes zero left port free semaphore location. subsequent read, processor will verify that written successfully that location will assume control over resource question. Meanwhile, processor right side attempts write zero same semaphore flag will fail, will verified fact that will read from that semaphore right side during subsequent read. sequence READ/WRITE been used instead, system contention problems could have occurred during between read write cycles. important note that failed semaphore request must followed either repeated reads writing into same location. reason this easily understood looking simple logic diagram semaphore flag Figure semaphore request latches feed into semaphore flag. Whichever latch first present zero semaphore flag will force side semaphore flag other side HIGH. This condition will continue until written same semaphore request latch. Should other sides semaphore request latch have been written zero meantime, semaphore flag will flip over other side soon written into first sides request latch.
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
second sides flag will stay until semaphore request latch written one. From this easy understand that, semaphore requested processor which requested longer needs resource, entire system hang until written into that semaphore request latch. critical case semaphore timing when both sides request single token attempting write zero into same time. semaphore logic specially designed resolve this problem. simultaneous requests made, logic guarantees that only side receives token. side earlier than other making request, first side make request will receive token. both requests arrive same time, assignment will arbitrarily made port other. caution that should noted when using semaphores that semaphores alone guarantee that access resource secure. with powerful programming technique, semaphores misused misinterpreted, software error easily happen. Initialization semaphores automatic must handled initialization program power-up. Since semaphore request flag which contains zero must reset one, semaphores both sides should have written into them initialization from both sides assure that they will free when needed.
Perhaps simplest application semaphores their application resource markers IDT70V25s Dual-Port SRAM. SRAM divided into blocks which were dedicated time servicing either left right port. Semaphore could used indicate side which would control lower section memory, Semaphore could defined indicator upper section memory. take resource, this example lower Dual-Port SRAM, processor left port could write then read zero Semaphore this task were successfully completed zero read back rather than one), left processor would assume control lower Meanwhile right processor attempting gain control resource after left processor, would read back response zero attempted write into Semaphore this point, software could choose gain
Using SemaphoresSome Examples
control second section writing, then reading zero into Semaphore succeeded gaining control, would lock left side. Once left side finished with task, would write Semaphore then gain access Semaphore Semaphore still occupied right side, left side could undo semaphore request perform other tasks until able write, then read zero into Semaphore right processor performs similar task with Semaphore this protocol would allow processors swap blocks Dual-Port SRAM with each other. blocks have particular size even variable, depending upon complexity software using semaphore flags. eight semaphores could used divide Dual-Port SRAM other shared resources into eight parts. Semaphores even assigned different meanings different sides rather than being given common meaning shown example above. Semaphores useful form arbitration systems like disk interfaces where must locked section memory during transfer device cannot tolerate wait states. With semaphores, once devices determined which memory area off-limits CPU, both devices could access their assigned portions memory continuously without wait states. Semaphores also useful applications where memory WAIT state available both sides. Once semaphore handshake been performed, both processors access their assigned segments full speed. Another application area complex data structures. this case, block arbitration very important. this application processor responsible building updating data structure. other processor then reads interprets that data structure. interpreting processor reads incomplete data structure, major error condition exist. Therefore, some sort arbitration must used between different processors. building processor arbitrates block, locks then able update data structure. When update completed, data structure block released. This allows interpreting processor come back read complete data structure, thereby guaranteeing consistent data structure.
PORT SEMAPHORE REQUEST FLIP FLOP WRITE
PORT SEMAPHORE REQUEST FLIP FLOP
WRITE
SEMAPHORE READ
Figure IDT70V25 Semaphore Logic
SEMAPHORE READ
2944
6.42
IDT70V25S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Ordering Information(1)
XXXXX Device Type Power Speed Package Process/ Temperature Range Blank I(1) Commercial (0°C +70°C) Industrial (-40°C +85°C) 100-pin TQFP (PN100-1) 84-pin (G84-3) 84-pin PLCC (J84-1)
Commercial Only Commercial Only Commercial Only
Speed Nanoseconds
70V25
NOTE: Industrial temperature range available. specific speeds, packages powers contact your sales office.
Standard Power Power 128K 3.3V Dual-Port
2944
Datasheet Document History
3/8/99: Initiated datasheet document history Converted format Cosmetic typographical corrections Pages Added additional notes configurations Page Fixed typographical error Changed drawing format Page Chaged 660mW 660µW
5/19/99: 6/10/99: 8/30/99:
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6.42

True Dual-Ported memory cells which allow simultaneous reads same memo

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