PRELIMINARY IDT723623 IDT723633 IDT723643 NOTE: There errata noti

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CMOS Bus-Matching SyncFIFO256 1,024
PRELIMINARY IDT723623 IDT723633 IDT723643
NOTE: There errata notice last page corrections have been incorporated into this document.
FEATURES:
Memory storage capacity: IDT723623-256 IDT723633-512 IDT723643-1,024 Clocked FIFO buffering data from Port Port Clock frequencies access time) Standard timing (using First Word Fall Through Timing (using flag functions) Programmable Almost-Empty Almost-Full flags; each three default offsets Serial parallel programming partial flags Port sizing bits (long word), bits (word) bits (byte)
Big- Little-Endian format word byte sizes Reset clears data configures FIFO, Partial Reset clears data retains configuration settings Mailbox bypass registers each FIFO Free-running CLKA CLKB asynchronous coincident (simultaneous reading writing data single clock edge permitted) Easily expandable width depth Auto power down minimizes power dissipation Available space-saving 128-pin Thin Quad Flatpack (TQFP) High performance sub-micron CMOS technology Industrial temperature range (-40oC +85oC) available
FUNCTIONAL BLOCK DIAGRAM
Mail Register Port-A Control Logic
Matching Input Register Output Register
CLKA
ARRAY
FIFO1 Mail1, Mail2, Reset Logic
1,024
A0-A35
Write Pointer
Read Pointer B0-B35
Status Flag Logic
FS0/SD FS1/
Programmable Flag Offset Registers
Timing Mode
CLKB Port-B Control Logic SIZE
3269
Mail Register
logo registered trademark, SyncFIFO trademark
COMMERCIAL TEMPERATURE RANGE
©1999 Integrated Device Technology, Inc. latest information contact IDT's site www.idt.com fax-on-demand 408-492-8391.
NOVEMBER 1999
DSC-3269/-
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION:
IDT723623/723633/723643 monolithic, highspeed, low-power, CMOS unidirectional Synchronous (clocked) FIFO memory which supports clock frequencies read access times fast 256/ 512/1,024 dual-port SRAM FIFO buffers data opposite directions. FIFO data Port output 36-bit, 18-bit, 9-bit formats with choice big- Little-Endian configurations. These devices synchronous (clocked) FIFO, meaning each port employs synchronous interface. data transfers through port gated LOW-to-HIGH
transition port clock enable signals. clocks each port independent another asynchronous coincident. enables each port arranged provide simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port bypass FIFOs mailbox registers. mailbox registers' width matches selected Port width. Each mailbox register flag (MBF1 MBF2) signal when mail been stored. kinds reset available these FIFOs: Reset Partial Reset. Reset initializes read write pointers first location memory array selects serial flag
CONFIGURATION
FS0/SD FS1/
CLKA
CLKB SIZE
TQFP (PK128-1, order code: VIEW
3269
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
programming, parallel flag programming, three possible default flag offset settings, Partial Reset also sets read write pointers first location memory. Unlike Reset, settings existing prior Partial Reset (i.e., programming method partial flag default offsets) retained. Partial Reset useful since permits flushing FIFO memory without changing configuration settings. These devices have modes operation: Standard mode, first word written empty FIFO deposited into memory array. read operation required access that word (along with other words residing memory). First Word Fall Through mode (FWFT), first word written empty FIFO appears automatically outputs, read operation required (Nevertheless, accessing subsequent words does necessitate formal read request). state BE/FWFT during Reset determines mode use. FIFO combined Empty/Output Ready Flag (EF/ combined Full/Input Ready Flag /IR). functions selected Standard mode. indicates whether FIFO memory empty. shows whether memory full not. functions selected First Word Fall Through mode. indicates whether FIFO available memory locations. shows whether FIFO data available reading not. marks presence valid data outputs. FIFO programmable Almost-Empty flag (AE) programmable Almost-Full flag (AF). indicates
when selected number words written FIFO memory achieve predetermined "almost-empty state". indicates when selected number words written memory achieve predetermined "almost-full state". FF/IR two-stage synchronized port clock that writes data into array. EF/OR two-stage synchronized port clock that reads data from array. Programmable offsets loaded parallel using Port serial input. Serial Programming Mode (SPM) makes this selection. Three default offset settings also provided. threshold locations from empty boundary threshold locations from full boundary. these choices made using inputs during Reset. more devices used parallel create wider data paths. First Word Fall Through mode, more than device connected series create greater word depths. addition external components unnecessary. time, FIFO actively performing function, chip will automatically power down. During power down state, supply current consumption (ICC) minimum. Initiating operation activating control inputs) will immediately take device Power Down state. IDT723623/723633/723643 characterized operation from 70°C. They fabricated using IDT's high speed, submicron CMOS technology.
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
DESCRIPTIONS
Symbol A0-A35 Name Port Data AlmostEmpty Flag (Port AlmostFull Flag (Port Port Data Description 36-bit bidirectional data port side Programmable Almost-Empty flag synchronized CLKB. when number words FIFO less than equal value Almost-Empty offset register, Programmable Almost-Full flag synchronized CLKA. when number empty locations FIFO less than equal value Almost-Full offset register, 36-bit bidirectional data port side This dual purpose pin. During Master Reset, HIGH will select BigEndian operation. this case, depending size, most significant byte word written Port read from Port first. will select Little-Endian operation. this case, least significant byte word written Port read from Port first. After Master Reset, this selects timing mode. HIGH FWFT selects Standard mode, selects First Word Fall Through mode. Once timing mode been selected, level FWFT must static throughout device operation. HIGH this enables either byte word width Port depend state SIZE. selects long word operation. works with SIZE select size endian arrangement Port level must static throughout device operation. CLKA continuous clock that synchronizes data transfers through Port asynchronous coincident CLKB. FF/IR synchronized LOW-to-HIGH transition CLKA. CLKB continuous clock that synchronizes data transfers through Port asynchronous coincident CLKA. EF/IR synchronized LOW-to-HIGH transition CLKB.
B0-B35
FWFT Big-Endian/ First Word Fall Through
BM(1)
Bus-Match Select (Port Port Clock
CLKA
CLKB
Port Clock
EF/OR
Port Chip Select Port Chip Select Empty/ Output Ready Flag (Port Port Enable Port Enable Full/Input Ready Flag (Port
must enable LOW-to-HIGH transition CLKA read write Port A0-A35 outputs high-impedance state when HIGH. must enable LOW-to-HIGH transition CLKB read write data Port B0-B35 outputs high-impedance state when HIGH.
This dual function pin. Standard mode, function selected. indicates whether FIFO memory empty. FWFT mode, function selected. indicates presence valid data B0-B35 outputs, available reading. FF/OR synchronized LOW-to-HIGH transition CLKB. must HIGH enable LOW-to-HIGH transition CLKA read write data Port must HIGH enable LOW-to-HIGH transition CLKB read write data Port
FF/IR
This dual function pin. Standard mode, function selected. indicates whether FIFO memory full. FWFT mode, function selected. indicates whether there space available writing FIFO memory. FF/IR synchronized LOW-to-HIGH transition CLKA.
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
DESCRIPTIONS (Continued)
Symbol Name Description FS1/SEN FS0/SD dual-purpose inputs used flag offset register programming. During Reset, FS1/SEN FS0/SD, together with SPM, select flag offset programming method. Three offset register programming methods available: automatically load three preset values 64), parallel load from Port serial load. When serial load selected flag offset register programming, FS1/SEN used enable synchronous LOW-to-HIGH transition CLKA. When FS1/SEN LOW, rising edge CLKA load present FS0/ into registers. number writes required program offset registers 723623, 723633, 723643. first write stores Y-register last write stores X-register LSB. HIGH level chooses mailbox register Port read write operation. HIGH level chooses mailbox register Port read write operation. When B0-B35 outputs active, HIGH level selects data from mail1 register output level selects FIFO data output. FS1/ Flag Offset Select Serial Enable, FS0/SD Flag Offset Select Serial Data
Port Mailbox Select Port Mailbox Select
MBF1
Mail1 Register Flag
MBF1
MBF2
LOW-to-HIGH transition CLKA that writes data mail1 register. Writes mail1 register inhibited while MBF1 LOW. MBF1 HIGH LOW-to-HIGH transition CLKB when Port read selected HIGH. MBF1 HIGH following either Reset (RS1) Partial Reset (PRS).
Mail2 Register Flag
RS1/RS2
MBF2 LOW-to-HIGH transition CLKB that writes data mail2 register. Writes mail2 register inhibited while MBF2 LOW. MBF2 HIGH LOW-to-HIGH transition CLKA when Port read selected HIGH. MBF2 HIGH following either Reset (RS2) Partial Reset (PRS).
both pins initializes FIFO read write pointers first location memory sets Port output register zeroes. pulse selects programming method (serial parallel) three programmable flag default offsets. also configures Port size endian arrangement. Four LOW-to-HIGH transitions CLKA four LOW-toHIGH transitions CLKB must occur while LOW. this initializes FIFO read write pointers first location memory sets Port output register zeroes. During Partial Reset, currently selected size, endian arrangement, programming method (serial parallel), programmable flag settings retained.
Resets
Partial Reset
SIZE(1)
Size Select (PortB)
HIGH this when HIGH selects byte (9-bit) size Port this when HIGH selects word (18-bit) size. SIZE works with select size endian arrangement Port level SIZE must static throughout device operation. this selects serial programming partial flag offsets. HIGH this selects parallel programming default offsets 64). HIGH selects write operation selects read operation Port LOW-to-HIGH transition CLKA. A0-A35 outputs HIGH impedance state when W/RA HIGH. selects write operation HIGH selects read operation Port LOW-to-HIGH transition CLKB. B0-B35 outputs HIGH impedance state when W/RB LOW.
SPM(1)
W/RA
Serial ProgramPort Write/ Read Select Port Write/ Read Select
W/RB
Note:
SIZE compatible. These inputs should tied GND.
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(1)
Symbol
Rating Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current VCC) Output Clamp Current VCC) Continuous Output Current VCC) Continuous Current Through Storage Temperature Range
Commercial -0.5 -0.5 +0.5 -0.5 +0.5 ±400
Unit
VO(2) IOUT ICC, IGND TSTG
NOTES: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. input output voltage ratings exceeded provided input output current ratings observed.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Supply Voltage High-Level Input Voltage Low-Level Input Voltage High-Level Output Current Low-Level Output Current Operating Temperature Min. Max. Unit
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
IDT723623 IDT723633 IDT723643 Commercial Parameter
Test Conditions 4.5V, -0.2 Input
Min.
Typ.(1)
Max.
Unit
ICC(2,3)
Other Inputs
Other Inputs
A0-A35 B0-B35 A0-A35 B0-B35
COUT
NOTES: typical values 25°C. additional information, following page. This supply current when each input least specified voltage levels rather than VCC.
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
fdata 25°C 5.5V 5.0V
CC(f) Supply Current
4.5V
3269
Clock Frequency
Figure Typical Characteristics: Supply Current Clock Frequency
CALCULATING POWER DISSIPATION ICC(f) current graph Figure taken while simultaneously reading writing FIFO IDT723623/723633/723643 with CLKA CLKB data inputs data outputs change state during each clock cycle consume highest supply current. Data outputs were disconnected normalize graph zero capacitance load. Once capacitance load data-output channel number IDT723623/723633/723643 inputs driven HIGH levels known, power dissipation calculated with equation below. With ICC(f) taken from Figure maximum power dissipation (PT) these FIFOs calculated CC(f) dc)] VCC2 where: number inputs driven levels increase power supply current each input HIGH level duty cycle inputs HIGH level output capacitance load switching frequency output
When read writes occurring IDT723633, power dissipated single clock (CLKA CLKB) input running frequency calculated 0.184 mA/MHz
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES SUPPLY VOLTAGE OPERATING FREE-AIR TEMPERATURE
723623L12 723623L15 723623L20 723623L30 723633L12 723633L15 723633L20 723633L30 723643L12 723643L15 723643L20 723643L30 Symbol tCLK tCLKH tCLKL tENS1 tENS2 tRSTS tFSS tBES tSPMS tSDS tSENS tFWS tENH tRSTH tFSH tBEH tSPMH tSDH tSENH Parameter Clock Frequency, CLKA CLKB Clock Cycle Time, CLKA CLKB Pulse Duration, CLKA CLKB HIGH Pulse Duration, CLKA CLKB Setup Time, A0-A35 before CLKA B0-B35 before CLKB Setup Time, W/RA before CLKA; W/RB before CLKB Setup Time, ENA, before CLKA; ENB, before CLKB Setup Time, before CLKA CLKB(1) Setup Time, before HIGH Setup Time, BE/FWFT before HIGH Setup Time, before HIGH Setup Time, FS0/SD before CLKA Setup Time, FS1/SEN before CLKA Setup Time, FWFT before CLKA Hold Time, A0-A35 after CLKA B0-B35 after CLKB Hold Time, CSA, W/RA, ENA, after CLKA; CSB, W/RB, ENB, after CLKB Hold Time, after CLKA CLKB(1) Hold Time, after HIGH Hold Time, BE/FWFT after HIGH Hold Time, after HIGH Hold Time, FS0/SD after CLKA Hold Time, FS1/SEN HIGH after CLKA Min. Max. Min. Max. Min. Max. Min. Max. Unit 66.7 33.4
tSPH Hold Time, FS1/SEN HIGH after HIGH tSKEW1 Skew Time, between CLKA CLKB FF/IR tSKEW2(2) Skew Time, between CLKA CLKB
EF/OR,
NOTES: Requirement count clock edge least four needed reset FIFO. Skew time timing constraint proper device operation only included illustrate timing relationship between CLKA cycle CLKB cycle.
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES SUPPLY VOLTAGE OPERATING FREE-AIR TEMPERATURE,
723623L12 723633L12 723643L12 Min. Max. 723623L15 723633L15 723643L15 Min. Max. 723623L20 723633L20 723643L20 Min. Max. 723623L30 723633L30 723643L30 Min. Max.
Symbol Parameter Access Time, CLKA A0-A35 CLKB B0-B35 tWFF Propagation Delay Time, CLKA FF/IR tREF tPAE tPAF tPMF Propagation Delay Time, CLKB EF/OR Propagation Delay Time, CLKB Propagation Delay Time, CLKA Propagation Delay Time, CLKA MBF1 MBF2 HIGH CLKB MBF2 MBF1 HIGH Propagation Delay Time, CLKA B0-B35(1) CLKB A0-A35(2) Propagation Delay Time, A0-A35 valid B0-B35 Valid Propagation Delay Time, LOW, AFA, HIGH, MBF1 HIGH, LOW, HIGH, MBF2 HIGH Enable Time, W/RA A0-A35 Activeand W/RB HIGH B0-B35 Active Disable Time, HIGH A0-A35 high-impedanceand HIGH W/RB B0-B35 high-impedance
Unit
tPMR tMDV tPRF
tDIS
NOTES: Writing data mail1 register when B0-B35 outputs active HIGH. Writing data mail2 register when A0-A35 outputs active HIGH.
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
SIGNAL DESCRIPTION
RESET (RS1/RS2) After power Reset operation must performed providing pulse simultaneously. Afterwards, FIFO memory IDT723623/723633/ 723643 undergoes complete reset taking Reset (RS1/ RS2) input least four Port clock (CLKA) four Port clock (CLKB) LOW-to-HIGH transitions. Reset inputs switch asynchronously clocks. Reset initializes internal read write pointers forces Full/Input Ready flag (FF/IR) LOW, Empty/Output Ready flag (EF/OR) LOW, Almost-Empty flag (AE) LOW, Almost-Full flag (AF) HIGH. Reset (RS1) also forces Mailbox flag (MBF1) parallel mailbox register HIGH, same time MBF2 operate likewise. After Reset, FIFO's Full/Input Ready flag HIGH after clock cycles begin normal operation. LOW-to-HIGH transition FlFO Reset (RS1/RS2) input latches value Big-Endian (BE) input determining order which bytes transferred through Port LOW-to-HIGH transition FlFO Reset (RS1/RS2) input also latches values Flag Select (FS0, FS1) Serial Programming Mode (SPM) inputs choosing Almost-Full Almost-Empty offset programming method (see Almost-Empty Almost-Full flag offset programming below). PARTIAL RESET (PRS) Each FIFO memories IDT723623/ 723633/723643 undergoes limited reset taking associated Partial Reset (PRS) input least four Port clock (CLKA) four Port clock (CLKB) LOW-to-HIGH transitions. Partial Reset inputs switch asynchronously clocks. Partial Reset initializes internal read write pointers forces Full/Input Ready flag (FF/IR) LOW, Empty/Output Ready flag /OR) LOW, Almost-Empty flag (AE) LOW, Almost-Full flag (AF) HIGH. Partial Reset also forces Mailbox flag (MBF1, MBF2) parallel mailbox register HIGH. After Partial Reset, FIFO's Full/Input Ready flag HIGH after clock cycles begin normal operation Whatever flag offsets, programming method (parallel serial), timing mode (FWFT Standard mode) currently selected time Partial Reset initiated, those settings will remain unchanged upon completion reset operation. Partial Reset useful case where reprogramming FIFO following Reset would inconvenient. BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT) This dual purpose pin. time Reset, select function active, permitting choice Big- LittleEndian byte arrangement data read from Port This selection determines order which bytes words)
data transferred through this port. following illustrations, assume that byte word) size been selected Port (Note that when Port configured long word size, Big-Endian function application input "don't care" HIGH BE/FWFT input when Reset (RS1) input goes from HIGH will select Big-Endian arrangement. this case, most significant byte (word) long word written Port will read from Port first; least significant byte (word) long word written Port will read from Port last. BE/FWFT input when Reset (RS1) input goes from HIGH will select Little-Endian arrangement. this case, least significant byte (word) long word written Port will read from Port first; most significant byte (word) long word written Port will read from Port last. Refer Figure illustration function. After Reset, FWFT select function active, permitting choice between possible timing modes: Standard mode First Word Fall Through (FWFT) mode. Once Reset RS1) input HIGH, HIGH BE/FWFT input during next LOW-to-HIGH transition CLKA (for FIFO1) CLKB (for FIFO2) will select Standard mode. This mode uses Empty Flag function indicate whether there words present FIFO memory. uses Full Flag function indicate whether FIFO memory free space writing. Standard mode, every word read from FIFO, including first, must requested using formal read operation. Once Reset (RS1) input HIGH, FWFT input during next LOW-to-HIGH transition CLKA (for FIFO1) CLKB (for FIFO2) will select FWFT mode. This mode uses Output Ready function (OR) indicate whether there valid data data outputs (B0-B35). also uses Input Ready function (IR) indicate whether FIFO memory free space writing. FWFT mode, first word written empty FIFO goes directly data outputs, read request necessary. Subsequent words must accessed performing formal read operation. Following Reset, level applied FWFT input choose desired timing mode must remain static throughout FIFO operation. PROGRAMMING ALMOST-EMPTY ALMOSTFULL FLAGS registers IDT723623/723633/723643 used hold offset values Almost-Empty Almost-Full flags. Almost-Empty flag Offset register labeled Almost-Full flag (AF) Offset register labeled offset registers loaded with preset values during reset FIFO, programmed parallel using FIFO's Port data inputs, programmed serial using Serial Data (SD) input (see Table
NOTE: Either HIGH applied "don't care" input with change logical operation FIFO. Nevertheless, inputs that temporarily "don't care" (along with unused inputs) must left open, rather they must either HIGH LOW.
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
TABLE FLAG PROGRAMMING
FS1/SEN
FSO/SD
REGlSTERS(1) Parallel programming Port Serial Programming reserved reserved reserved
NOTE: register holds offset register holds offset
load FIFO's Almost-Empty flag Almost-Full flag Offset registers with three preset values listed Table Serial Program Mode (SPM) least flag-select inputs must HIGH during LOW-to-HIGH transition Reset input (RS1). example, load preset value into SPM, must HIGH when returns HIGH. program registers from Port perform Reset with HIGH during LOW-to-HIGH transition RS1. After this reset complete, first four writes FIFO1 store data RAM. first write cycles load offset registers order third fourth write cycle should ignored. fifth write cycle FIFO ready loaded with data word. Figure Parallel Programming Almost-Full Flag Almost-Empty Flag Offset Values after Reset (IDT Standard FWFT modes), detailed timing diagram. Port data inputs used offset registers (A7-A0), (A8-A0), (A9-A0) IDT723623, IDT723633 IDT723643, respectively. highest numbered input used most significant binary number each case. Valid programming values registers range from IDT723623; IDT723633; 1,020 IDT723643. After offset registers programmed from Port Full/Input Ready flag (FF/IR) HIGH, both FIFOs begin normal operation. program registers serially, initiate Reset with LOW, FS0/SD FS1/SEN HIGH during LOW-to-HIGH transition RS1. After this reset complete, register values loaded bit-wise through FS0/SD input each LOW-to-HIGH transition CLKA that FS1/SEN input LOW. Thirty-two-, 40-bit writes needed complete programming IDT723623, IDT723633, IDT723643, respectively. four registers written order first-bit write stores most significant register last-bit write stores least significant register. Each register value programmed from (IDT723623), 1,020 (IDT723633), 2,044 (IDT723643). When option program offset registers serially chosen, Full/Input Ready (FF/IR) flag remains
until register bits written. FF/IR HIGH LOWto-HIGH transition CLKA after last loaded allow normal FIFO operation. SPM, FS0/SD, FS1/SEN function same both Standard FWFT modes. FIFO WRITE/READ OPERATION state Port data (A0-A35) lines controlled Port Chip Select (CSA) Port Write/Read Select RA). A0-A35 lines High-impedance state when either W/RA HIGH. A0-A35 lines active outputs when both W/RA LOW. Data loaded into FIFO from A0-A35 inputs LOW-to-HIGH transition CLKA when LOW, W/RA HIGH, HIGH, LOW, HIGH (see Table FIFO writes Port independent concurrent reads Port Port control signals identical those Port with exception that Port Write/Read select (W/RB) inverse Port Write/Read select (W/RA). state Port data (B0-B35) lines controlled Port Chip Select (CSB) Port Write/Read select (W/RB). B0-B35 lines high-impedance state when either HIGH W/RB LOW. B0-B35 lines active outputs when W/RB HIGH. Data read from FIFO B0-B35 outputs LOW-to-HIGH transition CLKB when LOW, W/RB HIGH, HIGH, LOW, EFB/ORB HIGH (see Table FIFO reads Port independent concurrent writes Port setup hold time constraints port clocks port Chip Selects Write/Read selects only enabling write read operations related highimpedance control data outputs. port enable during clock cycle, port's Chip Select Write/Read select change states during setup hold time window cycle. When operating FIFO FWFT mode Output Ready flag LOW, next word written automatically sent FIFO's output register LOW-to-HIGH transition port clock that sets Output Ready flag HIGH. When Output Ready flag HIGH, data residing FIFO's memory array clocked output register only when
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
TABLE PORT ENABLE FUNCTION TABLE
W/RA
CLKA
A0-A35 OUTPUTS high-impedance state high-impedance state high-impedance state high-impedance state Active, mail2 register Active, mail2 register Active, mail2 register Active, mail2 register
PORT FUNCTION None None FIFO write Mail1 write None None None Mail2 read (set MBF2 HIGH)
TABLE PORT ENABLE FUNCTION TABLE
W/RB
CLKB
B0-B35 OUTPUTS high-impedance state high-impedance state high-impedance state high-impedance state Active, FIFO output register Active, FIFO output register Active, mail1 register Active, mail1 register
PORT FUNCTION None None None Mail2 write None FIFO read None Mail1 read (set MBF1 HIGH)
read selected using port's Chip Select, Write/Read select, Enable, Mailbox select. When operating FIFO Standard mode, regardless whether Empty Flag HIGH, data residing FIFO's memory array clocked output register only when read selected using port's Chip Select, Write/Read select, Enable, Mailbox select. SYNCHRONIZED FIFO FLAGS Each FIFO synchronized port clock through least flip-flop stages. This done improve flag-signal reliability reducing probability metastable events when CLKA CLKB operate asynchronously another. FF/IR, synchronized CLKA. synchronized CLKB. Table shows relationship each port flag number words stored memory. EMPTY/OUTPUT READY FLAGS (EF/OR) These dual purpose flags. FWFT mode, Output Ready (OR) function selected. When OutputReady flag HIGH, data present FIFO output register. When Output Ready flag LOW, previous data word present FIFO output register attempted FIFO reads ignored. Standard mode, Empty Flag (EF) function selected. When Empty Flag HIGH, data available FIFO's memory reading output register. When Empty Flag LOW, previous data word present FIFO output register attempted FIFO reads ignored.
Empty/Output Ready flag FIFO synchronized port clock that reads data from array (CLKB). both FWFT Standard modes, FIFO read pointer incremented each time word clocked output register. state machine that controls Output Ready flag monitors write pointer read pointer comparator that indicates when FIFO SRAM status empty, empty+1, empty+2. FWFT mode, from time word written FIFO, shifted FIFO output register minimum three cycles Output Ready flag synchronizing clock. Therefore, Output Ready flag word memory next data sent FlFO output register three cycles port Clock that reads data from FIFO have elapsed since time word written. Output Ready flag FIFO remains until third LOW-toHIGH transition synchronizing clock occurs, simultaneously forcing Output Ready flag HIGH shifting word FIFO output register. Standard mode, from time word written FIFO, Empty Flag will indicate presence data available reading minimum cycles Empty Flag synchronizing clock. Therefore, Empty Flag word memory next data sent FlFO output register cycles port Clock that reads data from FIFO have elapsed since time word written. Empty Flag FIFO remains until second LOW-to-HIGH transition synchronizing clock occurs, forcing Empty Flag HIGH; only then data read.
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
TABLE FIFO FLAG OPERATION (IDT STANDARD FWFT MODES)
IDT723623(1,2) (X1+1) [256-(Y1+1)] (256-Y1) Number Words FIFO IDT723633(1,2) (X1+1) [512-(Y1+1)] (512-Y1) IDT723643(1,2) (X1+1) [1,024-(Y1+1)] (1,024-Y1) 1,023 1,024 Synchronized CLKB EF/OR Synchronized CLKA FF/IR
NOTES: almost-empty offset used almost-full offset used Both selected during FIFO reset Port programming. When word loaded empty FIFO shifted output register, previous FIFO memory location free. Data output register does count "word FIFO memory". Since FWFT mode, first word written empty FIFO goes unrequested output register read operation necessary), included memory count.
LOW-to-HIGH transition Empty/Output Ready flag synchronizing clock begins first synchronization cycle write clock transition occurs time tSKEW1 greater after write. Otherwise, subsequent clock cycle first synchronization cycle (see Figures 11). FULL/INPUT READY FLAGS /IR) This dual purpose flag. FWFT mode, Input Ready (IR) function selected. Standard mode, Full Flag (FF) function selected. both timing modes, when Full/Input Ready flag HIGH, memory location free SRAM receive data. memory locations free when Full/Input Ready flag attempted writes FIFO ignored. Full/Input Ready flag FlFO synchronized port clock that writes data array (CLKA). both FWFT Standard modes, each time word written FIFO, write pointer incremented. state machine that controls Full/Input Ready flag monitors write pointer read pointer comparator that indicates when FlFO SRAM status full, full-1, full-2. From time word read from FIFO, previous memory location ready written minimum cycles Full/Input Ready flag synchronizing clock. Therefore, Full/Input Ready flag less than cycles Full/Input Ready flag synchronizing clock have elapsed since next memory write location been read. second LOW-to-HIGH transition Full/Input Ready flag synchronizing clock after read sets Full/Input Ready flag HIGH. LOW-to-HIGH transition Full/Input Ready flag synchronizing clock begins first synchronization cycle read clock transition occurs time tSKEW1 greater after read. Otherwise, subsequent clock cycle first synchronization cycle (see Figures 14). ALMOST-EMPTY FLAGS (AE) Almost-Empty flag FIFO synchronized port clock that reads data from array (CLKB). state machine that controls Almost-Empty flag monitors write pointer read pointer comparator that indicates when FIFO SRAM status almost-empty, almost-empty+1,
most-empty+2. Almost-Empty state defined contents register These registers loaded with preset values during FIFO reset, programmed from Port programmed serially (see Almost-Empty flag Almost-Full flag offset programming above). Almost-Empty flag when FIFO contains less words HIGH when FIFO contains (X+1) more words. data word present FIFO output register been read from memory. LOW-to-HIGH transitions Almost-Empty flag synchronizing clock required after FIFO write Almost-Empty flag reflect level fill. Therefore, Almost-Full flag FIFO containing (X+1) more words remains cycles synchronizing clock have elapsed since write that filled memory (X+1) level. Almost-Empty flag HIGH second LOWto-HIGH transition synchronizing clock after FIFO write that fills memory (X+1) level. LOW-to-HIGH transition Almost-Empty flag synchronizing clock begins first synchronization cycle occurs time tSKEW2 greater after write that fills FIFO (X+1) words. Otherwise, subsequent synchronizing clock cycle first synchronization cycle. (See Figure 15). ALMOST-FULL FLAGS (AF) Almost-Full flag FIFO synchronized port clock that writes data array. state machine that controls Almost-Full flag monitors write pointer read pointer comparator that indicates when FIFO SRAM status almost-full, almost-full-1, almost-full-2. Almost-Full state defined contents register These registers loaded with preset values during FlFO reset programmed from Port programmed serially (see Almost-Empty flag Almost-Full flag offset programming above). Almost-Full flag when number words FIFO greater than equal (256-Y), (512-Y), (1,024-Y) IDT723623, IDT723633, IDT723643 respectively. Almost-Full flag HIGH when number words FIFO less than equal [256-(Y+1)], [512-(Y+1)], [1,024-(Y+1)] IDT723623, IDT723633, IDT723643 respectively. Note that data word present FIFO output register been read from memory.
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
LOW-to-HIGH transitions Almost-Full flag synchronizing clock required after FIFO read Almost-Full flag reflect level fill. Therefore, Almost-Full flag FIFO containing [256/512/1,024-(Y+1)] less words remains cycles synchronizing clock have elapsed since read that reduced number words memory [256/512/1024-(Y+1)]. Almost-Full flag HIGH second LOW-to-HIGH transition synchronizing clock after FIFO read that reduces number words memory [256/512/1024-(Y+1)]. LOW-to-HIGH transition Almost-Full flag synchronizing clock begins first synchronization cycle occurs time tSKEW2 greater after read that reduces number words memory [256/512/1024-(Y+1)]. Otherwise, subsequent synchronizing clock cycle first synchronization cycle. (See Figure 16). MAILBOX REGISTERS 36-bit bypass registers IDT723623/ 723633/723643 pass command control information between Port Port without putting queue. Mailbox Select (MBA, MBB) inputs choose between mail register FIFO port data transfer operation. usable width both Mail1 Mail2 registers matches selected size Port LOW-to-HIGH transition CLKA writes data Mail1 Register when Port write selected CSA, W/RA, with HIGH. selected Port size also bits, then usable width Mail1 register employs data lines A0-A35. selected Port size bits, then usable width Mail1 Register employs data lines A0-A17. this case, A18-A35 don't care inputs.) selected Port size bits, then usable width Mail1 Register employs data lines A0-A8. this case, A9-A35 don't care inputs.) LOW-to-HIGH transition CLKB writes B0-B35 data Mail2 Register when Port write selected CSB, W/RB, with HIGH. selected Port size also bits, then usable width Mail2 employs data lines B0-B35. selected Port size bits, then usable width Mail2 Register employs data lines B0-B17. this case, B18-B35 don't care inputs.) selected Port size bits, then usable width Mail1 Register employs data lines B0-B8. this case, B9B35 don't care inputs.) Writing data mail register sets corresponding flag (MBF1 MBF2) LOW. Attempted writes mail register ignored while mail flag LOW. When data outputs port active, data comes from FIFO output register when port Mailbox Select input from mail register when port Mailbox Select input HIGH. Mail1 Register Flag (MBF1) HIGH LOWto-HIGH transition CLKB when Port read selected CSB, W/RB, with HIGH. 36-bit size, bits mailbox data placed B0-B35. 18-bit size, bits mailbox data placed B0-B17. this case, B18-B35 indeterminate.) 9-bit size, bits mailbox data placed B0-B8. this case, B9-B35 indeterminate.)
Mail2 Register Flag (MBF2) HIGH LOWto-HIGH transition CLKA when Port read selected CSA, W/RA, with HIGH. 36-bit size, bits mailbox data placed A0-A35. 18-bit size, bits mailbox data placed A0-A17. this case, A18-A35 indeterminate.) 9-bit size, bits mailbox data placed A0A8. this case, A9-A35 indeterminate.) data mail register remains intact after read changes only when data written register. Endian Select feature effect mailbox data. SIZING Port configured 36-bit long word, 18bit word, 9-bit byte format data read from FIFO. levels applied Port Size Select (SIZE) BusMatch Select (BM) determine Port size. These levels should static throughout FIFO operation. Both size selections implemented completion Reset, time Full/Input Ready flag HIGH, shown Figure different methods sequencing data transfer available Port when size selection either byteor word-size. They referred Big-Endian (most significant byte first) Little-Endian (least significant byte first). level applied Big-Endian Select (BE) input during LOW-to-HIGH transition selects endian method that will active during FIFO operation. don't care input when size selected Port long word. endian method implemented completion Reset, time Full/Input Ready flag HIGH, shown Figure Only 36-bit long word data written read from FIFO memory IDT723623/723633/723643. Bus-matching operations done after data read from FIFO RAM. These bus-matching operations available when transferring data mailbox registers. Furthermore, both word- byte-size selections limit width data that used mail register operations. this case, only those byte lanes belonging selected word- bytesize carry mailbox data. remaining data outputs will indeterminate. remaining data inputs will don't care inputs. example, when word-size selected, then mailbox data transmitted only between A0-A17 B0-B17. When byte-size selected, then mailbox data transmitted only between A0-A8 B0-B8. (See Figures 18). BUS-MATCHING FIFO READS Data read from FIFO 36-bit long word increments. long word size implemented, entire long word immediately shifts FIFO output register. byte word size implemented Port only first bytes appear selected portion FIFO output register, with rest long word stored auxiliary registers. this case, subsequent FIFO reads output rest long word FIFO output register order shown Figure When reading data from FIFO byte word format, unused B0-B35 outputs LOW.
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
A35-A27
BYTE ORDER PORT
A26-A18
A17-A9
A8-A0
B35-B27 SIZE
B26-B18
B17-B9
B8-B0
Write FIFO
LONG WORD SIZE
Read from FIFO
B35-B27 SIZE B35-B27
B26-B18
B17-B9
B8-B0
B26-B18 B17-B9
B8-B0
1st: Read from FIFO
WORD SIZE BIG-ENDIAN
2nd: Read from FIFO
B35-B27 SIZE B35-B27
B26-B18
B17-B9
B8-B0
B26-B18 B17-B9
B8-B0
1st: Read from FIFO
WORD SIZE LITTLE-ENDIAN
2nd: Read from FIFO
B35-B27 SIZE B35-B27
B26-B18
B17-B9
B8-B0
B26-B18 B17-B9 B8-B0
1st: Read from FIFO
B35-B27 B26-B18 B17-B9 B8-B0
2nd: Read from FIFO
B35-B27 B26-B18 B17-B9 B8-B0
3rd: Read from FIFO
BYTE SIZE BIG-ENDIAN
4th: Read from FIFO
B35-B27 SIZE B35-B27
B26-B18
B17-B9
B8-B0
B26-B18 B17-B9 B8-B0
1st: Read from FIFO
B35-B27 B26-B18 B17-B9 B8-B0
2nd: Read from FIFO
B35-B27 B26-B18 B17-B9 B8-B0
3rd: Read from FIFO
BYTE SIZE LITTLE-ENDIAN
4th: Read from FIFO
3269
Figure sizing
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
CLKA CLKB tRSTS
tRSTH tBES tBEH tFWS tSPMS tFSS tSPMH tFSH tWFF tWFF tREF(2) FWFT
FS1,FS0 tRSF tRSF tRSF
3269
NOTES: must HIGH during Reset. FWFT HIGH, then EF/OR will CLKB cycle earlier than case where BE/FWFT LOW. only reset after power Figure Reset Loading with Preset Value Eight
CLKA CLKB tRSTS tRSTH tWFF tWFF tREF tRSF tRSF tRSF
3269
NOTES must HIGH during Partial Reset. BE/FWFT HIGH, then EF/OR will CLKB cycle earlier than case where BE/FWFT LOW. Figure Partial Reset (IDT Standard FWFT Modes)
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
CLKA
tFSS tFSS FS1,FS0
tFSH tFSH
tWFF tENS2 A0-A35
Offset Offset Dummy Word Dummy Word First Word FIFO1
3269
tENH
NOTE: LOW, W/RA HIGH, LOW. necessary program offset register consecutive clock cycles.
Figure Parallel programming Almost-Full Flag Almost-Empty Flag Offset Values after Reset. (IDT Standard Modes)
CLKA
tFSS
tFSH
tWFF tFSS FS1/ tSDS FS0/SD(2) Offset Offset
3269
tSPH
tSENS
tSENH
tSENS
tSENH
tSDH
tSDS
tSDH
NOTES: necessary program offset register bits consecutive clock cycles. FIFO write attempts ignored until HIGH. Programmable offsets written serially input order offset offset (X).
Figure Serial Programming Almost-Full Flag Almost-Empty Flag Offset Values after Reset (IDT Standard FWFT Modes)
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKA /IRA tCLKL
HIGH
tENS1 tENS1
tENH tENH
tENS2 tENS2 A0-A35
NOTE: Written FIFO. Figure Port Write Cycle Timing FIFO (IDT Standard FWFT Modes)
tENH tENS2 tENH
tENH W1(1)
tENS2
tENH
W2(1)
Operation
3269
tCLK tCLKH CLKB tCLKL
HIGH
tENS2 tMDV B0-B35
(Standard Mode)
tENH
tENS2
tENH
tENS2 Operation W2(1)
tENH
Previous Data
tDIS
tMDV
B0-B35
(FWFT Mode)
tDIS
3269
NOTE: Data read from FIFO
DATA SIZE TABLE FIFO LONG-WORD READS
SIZE MODE(1) (SELECT RESET) SIZE DATA WRITTEN FIFO A35-A27 A26-A18 A17-A9 A8-A0 B35-B27 DATA READ FROM FIFO B26-B18 B17-B9 B8-B0
NOTE: selected Reset: SIZE must static throughout device operation. Figure Port Long-Word Read Cycle (IDT Standard FWFT Modes)
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
CLKB HIGH
tENS2 tMDV B0-B17
(Standard Mode)
tENH Operation Read tDIS tDIS Read
3269
tMDV
Previous Data
Read
B0-B17
(FWFT Mode)
Read
Read
NOTE: Unused word B18-B35 contains zeros word-size reads
DATA SIZE TABLE WORD READS
SIZE MODE SIZE A35-A27 DATA WRITTEN FIFO1 A26-A18 A17-A9 A9-A0
NOTE: selected Reset: SIZE must static throughout device operation.
READ
DATA READ FROM FIFO B17-B9 B8-B0
Figure Port Word Read Cycle Timing (IDT Standard FWFT Modes)
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
CLKB
HIGH
tENS2 tMDV B0-B8
(Standard Mode)
tENH Operation Previous Data Read Read Read Read Read Read Read
3269
tDIS
tMDV
Read tDIS
B0-B8
(FWFT Mode)
Read
NOTE: Unused bytes B9-B17, B18-B26, B27-B35 contain zeros byte-size reads.
DATA SIZE TABLE BYTE READS
SIZE MODE(1) SIZE A35-A27 DATA WRITTEN FIFO A26-A18 A17-A9 A8-A0 READ
NOTE: selected Reset: SIZE must static throughout device operation.
DATA READ FROM FIFO B8-B0
Figure Port Byte Read Cycle Timing (IDT Standard FWFT Modes)
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
tCLKH CLKA tENS2 A0-A35 CLKB FIFO Empty HIGH HIGH tENH HIGH
tCLK tCLKL
tENS2
tENH
tCLK tCLKH tCLKL
tSKEW1
tREF tREF
tENS2
tENH
B0-B35 Data FIFO Output Register
3269
NOTES: tSKEW1 minimum time between rising CLKA edge rising CLKB edge transition HIGH clock next word FIFO output register three CLKB cycles. time between rising CLKA edge rising CLKB edge less than tSKEW1, then transition HIGH load first word output register occur CLKB cycle later than shown. Port size word byte, last word byte read from FIFO, respectively.
Figure Flag Timing First Data Word Fall Through when FIFO Empty (FWFT Mode)
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH tCLKL CLKA tENS2 tENH HIGH tENS2
tENH
HIGH A0-A35 CLKB
tCLK tCLKH tCLKL
tSKEW1
tREF tREF
FIFO Empty B0-B35
3269
HIGH tENS2 tENH
NOTES: tSKEW1 minimum time between rising CLKA edge rising CLKB edge transition HIGH next CLKB cycle. time between rising CLKA edge rising CLKB edge less than tSKEW1, then transition HIGH occur CLKB cycle later than shown. Port size word byte, last word byte read from FIFO, respectively.
Figure Flag Timing First Data Read when FIFO Empty (IDT Standard Mode)
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKB B0-B35 HIGH
Previous Word FIFO Output Register Next Word From FIFO
tCLKL
HIGH tENS2 tENH
tSKEW1 CLKA FIFO Full HIGH
tCLKH
tCLK
tCLKL tWFF tWFF
tENS2 tENS2
tENH
tENH
FIFO
3269
A0-A35
NOTES: tSKEW1 minimum time between rising CLKB edge rising CLKA edge transition HIGH next CLKA cycle. time between rising CLKB edge rising CLKA edge less than tSKEW1, then transition HIGH CLKA cycle later than shown. Port size word byte, tSKEW1 referenced rising CLKB edge that reads last word byte write long word, respectively.
Figure Flag Timing First Available Write when FIFO Full (FWFT Mode)
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
tCLK tCLKH CLKB HIGH tENS2 tENH tCLKL
HIGH B0-B35
Next Word From FIFO
Previous Word FIFO Output Register
tSKEW1(1) CLKA FIFO Full
tCLKH
tCLK
tCLKL
HIGH
tENS2 tENS2
tENH
tENH
FIFO
A0-A35
3269
NOTES: tSKEW1 minimum time between rising CLKB edge rising CLKA edge transition HIGH next CLKA cycle. time between rising CLKB edge rising CLKA edge less than tSKEW1, then transition HIGH CLKA cycle later than shown. Port size word byte, tSKEW1 referenced from rising CLKB edge that reads last word byte long word, respectively. Figure Flag Timing First Available Write when FIFO Full (IDT Standard Mode)
CLKA tENS2 tSKEW2 CLKB
Word FIFO1
tENH
tPAE
(X1+1) Words FIFO1 tENS2
tPAE tENH
3269
NOTES: SKEW2 minimum time between rising CLKA edge rising CLKB edge transition HIGH next CLKB cycle. time between rising CLKA edge rising CLKB edge less than tSKEW2, then transition HIGH CLKB cycle later than shown. FIFO Write LOW, W/RA LOW, LOW), FIFO read (CSB LOW, W/RB HIGH, LOW). Data FIFO output register been read from FIFO. Port size word byte, last word byte read from FIFO, respectively. Figure Timing when FIFO Almost-Empty (IDT Standard FWFT Modes).
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
CLKA tENS2 tPAF [D-(Y+1)] Words FIFO CLKA tENS2 tENH tENH tSKEW2
tPAF (D-Y) Words FIFO
3269
NOTES: tSKEW2 minimum time between rising CLKA edge rising CLKB edge transition HIGH next CLKA cycle. time between rising CLKA edge rising CLKB edge less than tSKEW2, then transition HIGH CLKB cycle later than shown. FIFO Write (CSA LOW, W/RA HIGH, LOW), FIFO read (CSB LOW, W/RB HIGH, LOW). Data FIFO output register been read from FIFO. Maximum FIFO Depth IDT723623, IDT723633, 1,024 IDT723643. Port size word byte, tSKEW2 referenced from rising CLKB edge that reads last word byte long word, respectively. Figure Timing when FIFO Almost-Full (IDT Standard FWFT Modes).
CLKA
tENS1 tENS1
tENH tENH
tENS2 tENS2 tENH tENH
A0-A35 CLKB
tPMF
tPMF
tENS2 B0-B35 tMDV tPMR tDIS (Remains valid Mail1 Register after read)
3269
tENH
FIFO Output Register
NOTE: Port configured word size, data written Mail1 Register using A0-A17 (A18-A35 don't care inputs). this first case B0-B17 will have valid data (B18-B35 will indeterminate). Port configured byte size, data written Mail1 Register using A0-A8 (A9-A35 don't care inputs). this second case, B0-B8 will have valid data (B9-B35 will indeterminate). Figure Timing Mail1 Register MBF1 Flag (IDT Standard FWFT Modes)
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
CLKB tENS1 tENS1 tENS2 tENS2 B0-B35 CLKA
tENH tENH tENH tENH
tPMF
tPMF
tENS2 A0-A35 tMDV FIFO Output Register tPMR tDIS (Remains valid Mail2 Register after read)
3269
tENH
NOTE: Port configured word size, data written Mail2 Register using B0-B17 (B18-B35 don't care inputs). this first case A0-A17 will have valid data (A18-A35 will indeterminate). Port configured byte size, data written Mail2 Register using B0-B8 (B9-B35 don't care inputs). this second case, A0-A8 will have valid data (A9-A35 will indeterminate). Figure Timing Mail2 Register MBF2 Flag (IDT Standard FWFT Modes)
TRANSFER CLOCK WRITE WRITE CLOCK (CLKA) CHIP SELECT
READ CLKB
CLKA
READ CLOCK (CLKB) CHIP SELECT EMPTY FLAG/ OUTPUT READY /OR) READ ENABLE (ENB)
723623 723633 723643
WRITE SELECT
WRITE ENABLE (ENA) ALMOST-FULL FLAG A0-A35 DATA (Dn)
723623 723633 723643
READ SELECT /RB) ALMOST-EMPTY FLAG B0-B35 DATA (Qn)
B0-B35
A0-A35
FULL FLAG/ INPUT READY
/IR)
3269
NOTES: Mailbox feature supported depth expansion applications. (MBA GND) Transfer clock should either Write Port Clock (CLKA) Read Port Clock (CLKB), whichever faster. amount time takes last FIFO chain (i.e. valid data appear last FIFO's outputs) after word been written first FIFO delays each individual FIFO: 1)*(4*transfer clock) RCLK, where number FIFOs expansion TRCLK CLKB period. amount time takes FF/IR first FIFO chain after word been read from last FIFO delays each individual FIFO: 1)*(3*transfer clock) 2*TWCLK, where number FIFOs expansion TWCLK CLKA period. Figure Block Diagram 1,024 Synchronous FIFO Memory with Programmable Flags used Depth Expansion Configuration
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
From Output Under Test
PROPAGATION DELAY LOAD CIRCUIT Timing Input Data, Enable Input VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Enable tPLZ Low-Level Output tPZH High-Level Output tPZL tPHZ VOLTAGE WAVEFORMS ENABLE DISABLE TIMES In-Phase Output Input Low-Level Input VOLTAGE WAVEFORMS PULSE DURATIONS High-Level Input
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
3269
NOTE: Includes probe capacitance. Figure Load Circuit Voltage Waveforms.
ORDERING INFORMATION
XXXXXX Device Type Power Speed Package Process/ Temperature Range BLANK Commercial (0°C +70°C) Thin Quad Flat Pack (TQFP, PK128-1) Commercial Only Clock Cycle Time (tCLK) Speed Nanoseconds
Power
723623 Synchronous FIFO with Bus-Matching 723633 Synchronous FIFO with Bus-Matching 723643 1,024 Synchronous FIFO with Bus-Matching
NOTE: Industrial temperature range available special order.
3269
IDT723623/723633/723643 Bus-Matching SyncFIFO256 1,024
COMMERCIAL TEMPERATURE RANGE
FIFO Marketing June 1997
36-BIT FIFO DATA SHEET ERRATA CONCERNING MASTER RESET FUNCTION (Affects IDT723622/723632/723642, IDT723623/723633/723643, IDT723624/723634/723644 IDT723626/723636/723646)
recently identified some omissions errors regarding descriptions master partial reset functions following 36-bit FIFO data sheets (all versions dated December 1996 earlier): IDT723622/723632/723642, IDT723623/723633/723643, IDT723624/723634/723644 IDT723626/723636/723646. corrections clarifications described will included new, corrected versions data sheets.
723622/723632/723642, 723624/723634/723644 723626/723636/723646 Data sheets these FIFOs explicitly state necessity, right after device power performing Master Reset operation providing pulse both Master Reset inputs, MRS1 MRS2 (RST1 RST2 IDT723622/723632/ 723642) simultaneously. Afterwards, these inputs used independently: MRS1 master reset FIFO1 MRS2 master reset FIFO2.
723623/723633/723643 TQFP Configuration December 1996 data sheet incorrectly labeled pins. 119, previously known MRS, been renamed RS1. Previously identified called RS2. initiate master reset operation right after device power pulse must provided both reset inputs, simultaneously. Afterwards, these inputs used independently: master reset FIFO together with Mail1 Register, reset Mail2 Register (forcing Mailbox Flag MBF2 HIGH). case partial reset operation, performs partial reset FIFO together with Mail1 Register. Once again, resets Mail2 Register. Designers have already begun designing according December 1996 data sheet should consider following recommendations where appropriate: existing design uses neither Mail2 Register (associated with MBF2 lines) flag, changes design needed. Even this design originally followed data sheet dated December 1996 earlier, FIFO will operate properly. design does either Mail2 Register flag, then that design must adapted meet specification changes.

PRELIMINARY IDT723623 IDT723633 IDT723643 NOTE: There errata noti

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