IDT723613 Free-running CLKA CLKB asynchronous coincident (permits

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IDT723613 Free-running CLKA CLKB asynchronous coincident (permits

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CMOS Clocked FIFO With Bus-Matching Byte Swapping
IDT723613
Free-running CLKA CLKB asynchronous coincident (permits simultaneous reading writing data single clock edge) storage capacity FIFO buffering data from Port Port Mailbox bypass registers each direction Dynamic Port sizing bits (long word), -bits (word), bits (byte) Selection Big- Little-Endian format word byte sizes Three modes byte-order swapping Port Programmable Almost-Full Almost-Empty flags Microprocessor interface control logic flags synchronized CLKA flags synchronized CLKB Passive parity checking each Port
Parity Generation selected each Port Low-power advanced CMOS technology Supports clock frequencies Fast access times Available 132-pin quad flatpack (PQFP) spacesaving 120-pin thin quad flatpack (TQFP) Industrial temperature range (-40oC available
DESCRIPTION:
IDT723613 monolithic, high-speed, low-power, CMOS synchronous (clocked) FIFO memory which supports clock frequencies read-access times fast dual-port SRAM FIFO buffers data from port port FIFO flags indicate empty full conditions, programmable flags, Almost-Full (AF) Almost-Empty (AE), indicate when selected number
FUNCTIONAL BLOCK DIAGRAM
CLKA Port-A Control Logic Parity Gen/Check
Bus-Matching Output Byte Swapping Register
Mail Register
Parity Generation
ODD/
Input Register
ARRAY
Output Register
Device Control
Write Pointer
Read Pointer
Status Flag Logic
FIFO
CLKB Programmable Flag Offset Registers Port-B Port-B Control Control Logic Logic SIZ0 SIZ1
Parity Gen/Check
Mail Register
3145
logo registered trademark SyncFIFO trademark
COMMERCIAL TEMPERATURE RANGE
©1999 Integrated Device Technology, Inc. latest information contact IDT's site www.idt.com fax-on-demand 408-492-8391.
August 1999
DSC-3145/-
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (Continued)
words stored memory. FIFO data port output 36-bit, 18-bit, 9-bit formats with choice bigor Little-Endian configurations. Three modes byte-order swapping possible with bus-size selection. Communication between each port bypass FIFO 36bit mailbox registers. Each mailbox register flag signal when mail been stored. Parity checked passively each port ignored desired. Parity generation selected data read from each port. more devices used parallel create wider data paths. IDT723613 synchronous (clocked) FIFO, meaning each port employs synchronous interface. data transfers
through port gated LOW-to-HIGH transition continuous (free-running) port clock enable signals. continuous clocks each port independent another asynchronous coincident. enables each port arranged provide simple interface between microprocessors and/or buses with synchronous interfaces. Full Flag (FF) Almost-Full (AF) flag FIFO two-stage synchronized port clock (CLKA) that writes data into array. Empty Flag (EF) Almost-Empty (AE) flag FIFO two-stage synchronized port clock (CLKB) that reads data from array. IDT723613 characterized operation from 70°C.
CONFIGURATION
CLKA
SIZ1 SIZ0
CLKB
ODD/
3145
NOTE: internal connection
TQFP (PN120-1, order code: VIEW
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
CONFIGURATION (Continued)
CLKA
ODD/
SIZ1 SIZ0
CLKB
3145
Electrical center beveled edge. identifier corner.
PQFP
(PQ132-1, order code: PQF) VIEW
NOTES: internal connection. Uses Yamaichi socket IC51-1324-828.
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
DESCRIPTION
Symbol Name 0-A35 Port Data Almost-Empty Flag Description 36-bit bidirectional data port side Programmable Almost-Empty flag synchronized CLKB. when Port Port number 36-bit words FIFO less than equal value offset register, Programmable Almost-Full flag synchronized CLKA. when Port number 36-bit empty locations FIFO less than equal value offset register, 36-bit bidirectional data port side Selects bytes port used during byte word FIFO reads. selects most significant bytes B0-B35 use, HIGH selects least significant bytes. CLKA continuous clock that synchronizes data transfers through port asynchronous coincident CLKB. synchronized LOW-to-HIGH transition CLKA. CLKB continuous clock that synchronizes data transfers through port asynchronous coincident CLKA. Port-B byte swapping data port sizing operations also synchronous LOW-to-HIGH transition CLKB. synchronized LOW-to-HIGH transition CLKB. must enable LOW-to-HIGH transition CLKA read write data port A0-A35 outputs high-impedance state when HIGH. must enable LOW-to-HIGH transition CLKB read write data port B0-B35 outputs high-impedance state when HIGH. synchronized LOW-to-HIGH transition CLKB. When LOW, Port FIFO empty, reads from memory disabled. Data read from FIFO output register when HIGH. forced when device reset HIGH second LOW-to-HIGH transition CLKB after data loaded into empty FIFO memory. must HIGH enable LOW-to-HIGH transition CLKA read write data port must HIGH enable LOW-to-HIGH transition CLKB read write data port synchronized LOW-to-HIGH transition CLKA. When LOW, Port FIFO full, writes memory disabled. forced when device reset HIGH second LOW-to-HIGH transition CLKA after reset. LOW-to-HIGH transition latches values FS1, which loads four preset values into Almost-Full flag AlmostEmpty flag offsets. high level chooses mailbox register port read write operation. When A0-A35 outputs active, mail2 register data output. MBF1 LOW-to-HIGH transition CLKA that writes data mail1 register. Writes mail1 register inhibited while MBF1 LOW. MBF1 HIGH LOW-to-HIGH transition CLKB when port read selected both SIZ1 SIZ0 HIGH. MBF1 HIGH when device reset. MBF2 LOW-to-HIGH transition CLKB that writes data mail2 register. Writes mail2 register inhibited while MBF2 LOW. MBF2 HIGH LOW-to-HIGH transition CLKA when port read selected HIGH. MBF2 HIGH when device reset.
0-B35
Almost-Full Flag
CLKA
Port Data Big-Endian Select
Port Clock
CLKB
Port Clock
Port Chip Select
Port Chip Select
Empty Flag
Port Enable Port Enable Full Flag
FS1, Flag Offset Selects
MBF1
Port Mailbox Select Mail1 Register Flag
MBF2
Mail2 Register Flag
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (Continued)
Symbol ODD/
EVEN PEFA
Name Odd/Even Parity Select
Port Parity Error Flag
(Port
PEFB
Port Parity Error Flag
(Port
Port Parity Generation
Port Parity
Reset
SIZ0, SIZ1
Port Size Selects
(Port
SW0,
Port Byte Swap Selects
(Port
Port Write/Read Select Port Write/Read Select
Description parity checked each port when ODD/EVEN HIGH, even parity checked when ODD/EVEN LOW. ODD/EVEN also selects type parity generated each port parity generation enabled read operation. When byte applied terminals A0-A35 fails parity, PEFA LOW. Bytes organized A0-A8, A9-A17, A18-A26, A27-A35, with most significant each byte serving parity bit. type parity checked determined state ODD/EVEN input. parity trees used check A0-A35 inputs shared mail2 register generate parity parity generation selected PGA. Therefore, mail2 read with parity generation having LOW, HIGH, W/RA LOW, HIGH HIGH, PEFA flag forced HIGH regardless state A0-A35 inputs. When valid byte applied terminals B0-B35 fails parity, PEFB LOW. Bytes organized B0-B8, B9-B17, B-18-B26, B27-B35, with most significant each byte serving parity bit. byte valid when used size selected port type parity checked determined state ODD/EVEN input. parity trees used check B0-B35 inputs shared mail1 register generate parity parity generation selected PGB. Therefore, mail1 read with parity generation having LOW, HIGH, W/RB LOW, SIZ1 SIZ0 HIGH HIGH, PEFB flag forced HIGH regardless state B0-B35 inputs. Parity generated data reads from mail2 register when HIGH. type parity generated selected state ODD/EVEN input. Bytes organized A0-A8, A9-A17, A18-A26, A27-A35. generated parity bits output most significant each byte. Parity generated data reads from port when HIGH. type parity generated selected state ODD/EVEN input. Bytes organized B0-B8, B9-B17, B18-B26, B27-B35. generated parity bits output most significant each byte. reset device, four LOW-to-HIGH transitions CLKA four LOW-toHIGH transitions CLKB must occur while LOW. This sets MBF1, MBF2 flags HIGH flags LOW. LOWto-HIGH transition latches status inputs select Almost-Full flag Almost-Empty flag offset. LOW-to-HIGH transition CLKB latches states SIZ0, SIZ1, following LOW-to-HIGH transition CLKB implements latched states port size. Port sizes long word, word, byte. HIGH both SIZ0 SIZ1 accesses mailbox registers port 36-bit write read. beginning each long word FIFO read, four modes byteorder swapping selected SW1. four modes swap, byte swap, word swap, byte-word swap. Byte-order swapping possible with bus-size selection. HIGH selects write operation selects read operation port LOW-to-HIGH transition CLKA. A0-A35 outputs high-impedance state when W/RA HIGH. HIGH selects write operation selects read operation port LOW-to-HIGH transition CLKB. B0-B35 outputs high-impedance state when W/RB HIGH.
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(1)
Symbol
Rating Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current, VCC) Output Clamp Current, VCC) Continuous Output Current, VCC) Continuous Current Through Storage Temperature Range
Commercial -0.5 -0.5 VCC+0.5 -0.5 VCC+0.5 ±500
Unit
IOUT TSTG
NOTES: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "Recommended Operating Conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. input output voltage ratings exceeded provided input output current ratings observed.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Supply Voltage High-Level Input Voltage Low-Level Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature Min. Max. Unit
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
IDT723613 Commercial Min. Typ.(1) Max.
Parameter
Test Conditions 4.5V, 4.5V, 5.5V, 5.5V, 5.5V,
Unit
NOTE: typical values 25°C. additional information, following page.
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
fdata 25°C
5.5V
ICC(f) Supply Current
4.5V
3145
Clock Frequency
Figure Typical Characteristics: Supply Current Clock Frequency
CALCULATING POWER DISSIPATION ICCf current graph Figure taken while simultaneously reading writing FIFO IDT723613 with CLKA CLKB date inputs data outputs change state during each clock cycle consume highest supply current. Data outputs were disconnected normalize graph zero-capacitance load. Once capacitive lead data-output channel known, power dissipation calculated with equation below. With ICC(f) taken from Figure maximum power dissipation (PT) IDT723613 calculated ICC(f) (VOH VOL)2 where: output capacitive load switching frequency output output high-level voltage output high-level voltage
When reads writes occurring IDT723613, power dissipated single clock (CLKA CLKB) input running frequency calculated 0.29mA/MHz
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES SUPPLY VOLTAGE OPERATING FREE-AIR TEMPERATURE
Symbol tCLK tCLKH tCLKL tENS tSZS tSWS tPGS tRSTS tFSS tENH tSZH tSWH tPGH tRSTH tFSH tSKEW1
Parameter Clock Frequency, CLKA CLKB Clock Cycle Time, CLKA CLKB Pulse Duration, CLKA CLKB HIGH Pulse Duration, CLKA CLKB Setup Time, A0-A35 before CLKA B0-B35 before CLKB Setup Time, CSA, W/RA, ENA, before CLKA; CSB,W/RB, before CLKB Setup Time, SIZ0, SIZ1,and before CLKB Setup Time, before CLKB Setup Time, ODD/EVEN before CLKB(1) Setup Time, before CLKA CLKB(2) Setup Time, before HIGH Hold Time, A0-A35 after CLKA B0-B35 after CLKB Hold Time, after CLKA; CSB, W/RB, after CLKB Hold Time, after CLKB Hold Time, ODD/EVEN after CLKB Hold Time, after CLKA CLKB Hold Time, after HIGH Skew Time, between CLKA CLKB
IDT723613L15 IDT723613L20 IDT723613L30 Min. Max. Min. Max. Min. Max. 66.7 33.4
Unit
Hold Time, SIZ0, SIZ1, after CLKB
tSKEW2(3) Skew Time, between CLKA CLKB
NOTES: Only applies clock edge that does FIFO read. Requirement count clock edge least four needed reset FIFO. Skew time timing constraint proper device operation only included illustrate timing relationship between CLKA cycle CLKB cycle.
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES SUPPLY VOLTAGE OPERATING FREE-AIR TEMPERATURE, 30pF
Symbol tWFF tREF tPAE tPAF tPMF Parameter Access Time, CLKA A0-A35 CLKB B0-B35 Propagation Delay Time, CLKA Propagation Delay Time, CLKB IDT723613L15 IDT723613L20 IDT723613L30 Min. Max. Min. Max. Min. Max. Unit
Propagation Delay Time, CLKB Propagation Delay Time, CLKA MBF1 MBF2 HIGH CLKB MBF2 MBF1 HIGH Propagation Delay Time, CLKA B0-B35(1) CLKB A0-A35(2) Propagation delay time, CLKB Propagation Delay Time, CLKA
tPMR tPPE(3) tMDV tPDPE tPOPE tPOPB(4)
11.5
PEFB
Propagation Delay Time, SIZ1, SIZ0 B0-B35 valid Propagation Delay Time, A0-A35 valid PEFA valid; B0-B35 valid PEFB valid
Propagation Delay Time, ODD/EVEN PEFA PEFB Propagation Delay Time, ODD/EVEN parity bits (A8, A17, A26, A35) (B8, B17, B26, B35)
tPEPE
Propagation Delay Time, CSA, ENA, W/RA, MBA, PEFA; CSB, ENB, W/RB, SIZ1, SIZ0, PEFB
tPEPB(4)
Propagation Delay Time, CSA, ENA, W/RA, MBA, parity bits (A8, A17, A26, A35); CSB, ENB, W/RB, SIZ1, SIZ0, parity bits (B8, B17, B26, B35) Propagation Delay Time, MBF1, MBF2 HIGH
tRSF
Enable Time, W/RA A0-A35 active HIGH B0-B35 active Disable Time, HIGH A0-A35 high impedance HIGH B0-B35 high impedance
tDIS
NOTES: Writing data mail1 register when B0-B35 outputs active SIZ1 SIZ0 HIGH. Writing data mail2 register when A0-A35 outputs active. Only applies when port-B size implemented rising CLKB edge. Only applies when reading data from mail register.
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
RESET (RST) IDT723613 reset taking Reset (RST input least four port Clock (CLKA) four port Clock (CLKB) LOW-to-HIGH transitions. Reset input switch asynchronously clocks. device reset initializes internal read write pointers FIFO forces Full Flag (FF) LOW, Empty Flag (EF) LOW, Almost-Empty flag (AE) LOW, Almost-Full flag (AF) HIGH. reset also forces Mailbox Flags (MBF1, MBF2) HIGH. After reset, HIGH after LOW-to-HIGH transitions CLKA. device must reset after power before data written memory. LOW-to-HIGH transition input loads Almost-Full Almost-Empty Offset register with value selected Flag Select (FS0, FS1) inputs. values that loaded into register shown Table FIFO WRITE/READ OPERATION state port data (A0-A35) outputs controlled port-A Chip Select (CSA) port-A Write/Read select (W/R A0-A35 outputs high-impedance state when either W/RA HIGH. A0-A35 outputs active when both W/RA LOW. Data loaded into FIFO from A0-A35 inputs LOW-to-HIGH transition CLKA when LOW, TABLE FLAG PROGRAMMING ALMOST-FULL ALMOST-EMPTY FLAG OFFSET REGISTER
HIGH, HIGH, LOW, HIGH (see Table state port data (B0-B35) outputs controlled port Chip Select (CSB port Write/Read select (W/RB). B0-B35 outputs high-impedance state when either W/RB HIGH. B0-B35 outputs active when both W/RB LOW. Data read from FIFO B0-B35 outputs LOW-to-HIGH transition CLKB when LOW, W/RB LOW, HIGH, HIGH, either SIZ0 SIZ1 (see Table setup hold-time constraints port clocks port Chip Selects (CSA, CSB) Write/Read selects W/RB) only enabling write read operations related high-impedance control data outputs. port enable during clock cycle, port's Chip Select Write/Read select change states during setup hold time window cycle. SYNCHRONIZED FIFO FLAGS Each FIFO flag synchronized port clock through flip-flop stages. This done improve flags' reliability reducing probability metastable events their outputs when CLKA CLKB operate asynchronously another. synchronized CLKA. synchronized CLKB. Table shows relationship each port flag level FIFO fill. EMPTY FLAG (EF) FIFO Empty Flag synchronized port clock that reads data from array (CLKB). When HIGH, data read FIFO output register. When LOW, FIFO empty attempted FIFO reads ignored. When reading FIFO with byte word size port when fourth byte second word last long word read. FIFO read pointer incremented each time word clocked output register. state machine that controls monitors write-pointer read-pointer comparator that indicates when FIFO SRAM status empty, empty+1, empty+2. word written FIFO
TABLE PORT ENABLE FUNCTION TABLE
W/RA
CLKA
A0-A35 OUTPUTS high-impedance state high-impedance state high-impedance state high impedence state Active, mail2 register Active, mail2 register Active, mail2 register Active, mail2 register
PORT FUNCTION None None FIFO write Mail1 write None None None Mail2 read (set MBF2 HIGH)
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
TABLE PORT ENABLE FUNCTION TABLE
W/RB
SIZ1, SIZ0 One, both Both HIGH One, both One, both Both HIGH Both HIGH
CLKB
B0-B35 OUTPUTS high-impedance state high-impedance state high-impedance state high-impedance state Active, FIFO output regisger Active, FIFO output register Active, mail1 register Active mail1 register
PORT FUNCTION None None None Mail2 write None FIFO read None Mail1 read (set MBF1 HIGH)
read FIFO output register minimum three port clock (CLKB) cycles. Therefore, word memory next data sent FIFO output register CLKB cycles have elapsed since time word written. FIFO HIGH second LOW-to-HIGH transition CLKB, data word read FIFO output register following cycle. LOW-to-HIGH transition CLKB begins first synchronization cycle write clock transition occurs time tSKEW1 greater after write. Otherwise, subsequent CLKB cycle first synchronization cycle (see Figure 10). FULL FLAG (FF) FIFO Full Flag synchronized port clock that writes data array (CLKA). When HIGH, SRAM location free receive data. memory locations free when attempted writes FIFO ignored. Each time word written FIFO, write-pointer incremented. state machine that controls monitors write-pointer read-pointer comparator that indicates TABLE FIFO FLAG OPERATION NUMBER 36-BIT WORDS FIFO SYNCHRONIZED CLKB SYNCHRONIZED CLKA
when FIFO SRAM status full, full-1, full-2. From time word read from FIFO, previous memory location ready written minimum three CLKA cycles. Therefore, less than CLKA cycles have elapsed since next memory write location been read. second LOW-to-HIGH transition synchronizing clock after read sets HIGH data written following clock cycle. LOW-to-HIGH transition CLKA begins first synchronization cycle read clock transition occurs time tSKEW greater after read. Otherwise, subsequent clock cycle first synchronization cycle (see Figure 11). ALMOST-EMPTY FLAG (AE) FIFO Almost-Empty flag synchronized port clock that reads data from array (CLKB). state machine that controls flag monitors write-pointer readpointer comparator that indicates when FIFO SRAM status almost-empty, almost-empty+1, almost-empty+2. almost-empty state defined value Almost-Full Almost-Empty Offset register (X). This register loaded with four preset values during device reset (see reset above). flag when FIFO contains less long words memory HIGH when FIFO contains (X+1) more long words. LOW-to-HIGH transitions port Clock (CLKB) required after FIFO write flag reflect level fill. Therefore, flag FIFO containing (X+1) more long words remains CLKB cycles have elapsed since write that filled memory (X+1) level. flag HIGH second CLKB LOW-to-HIGH transition after FIFO write that fills memory (X+1) level. LOWto-HIGH transition CLKB begins first synchronization cycle occurs time tSKEW2 greater after write that fills FIFO (X+1) long words. Otherwise, subsequent CLKB cycle first synchronization cycle (see Figure 12). ALMOST FULL FLAG (AF) FIFO Almost-Full flag synchronized port clock that writes data array (CLKA). state machine that controls
NOTE: value Almost-Empty flag Almost-Full flag Offset register
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
flag monitors write-pointer read-pointer comparator that indicates when FIFO SRAM status almost -full, almostfull-1, almost-full-2. almost-full state defined value Almost-Full Almost-Empty Offset register (X). This register loaded with four preset values during device reset (see reset above). flag when FIFO contains (64-X) more long words memory HIGH when FIFO contains [64-(X+1)] less long words. LOW-to-HIGH transitions port Clock (CLKA) required after FIFO read flag reflect level fill. Therefore, flag FIFO containing [64(X+1)] less words remains CLKA cycles have elapsed since read that reduced number long words memory [64-(X+1)]. flag HIGH second CLKA LOW-to-HIGH transition after FIFO read that reduces number long words memory [64(X+1)]. LOW-to-HIGH transition CLKA begins first synchronization cycle occurs time tSKEW2 greater after read that reduces number long words memory [64-(X+1)]. Otherwise, subsequent CLKA cycle first synchronization cycle (see Figure 13). MAILBOX REGISTERS 36-bit bypass registers (mail1, mail2) IDT723613 pass command control information between port port without putting queue. LOW-toHIGH transition CLKA writes A0-A35 data mail1 register when port write selected CSA, (with HIGH). LOW-to-HIGH transition CLKB writes B0-B35 data mail2 register when port write selected CSB, (and both SIZ0 SIZ1 HIGH). Writing data mail register sets corresponding flag (MBF1 MBF2) LOW. Attempted writes mail register ignored while mail flag LOW. When port data (B0-B35) outputs active, data comes from FIFO output register when either both SIZ1 SIZ0 from mail1 register when both SIZ1 SIZ0 HIGH. Mail1 Register Flag (MBF1) HIGH rising CLKB edge when port read selected CSB, W/RB, ENB, (and both SIZ1 SIZ0 HIGH). Mail2 Register Flag (MBF2) HIGH rising CLKA edge when port read selected CSA, (with HIGH). data mail register remains intact after read changes only when data written register. DYNAMIC SIZING port configured 36-bit long word, 18bit word, 9-bit byte format data read from FIFO. Word- byte-size selections utilize most significant bytes (Big-Endian) least significant bytes (Little-Endian). Port bus-size changed dynamically synchronous CLKB communicate with peripherals various widths. levels applied port bus-size select (SIZ0, SIZ1) inputs Big-Endian select (BE) input stored each CLKB LOW-to-HIGH transition. stored port bus-size selection implemented next rising edge CLKB according Figure
Only 36-bit long-word data written read from FIFO memory IDT723613. Bus-matching operations done after data read from FIFO RAM. Port sizing does apply mail register operations. BUS-MATCHING FIFO READS Data read from FIFO 36-bit long-word increments. long-word bus-size implemented, entire long word immediately shifts FIFO output register upon read. byte word size implemented port only first bytes appear selected portion FIFO output register, with rest long word stored auxiliary registers. this case, subsequent FIFO reads with same bus-size implementation output rest long word FIFO output register order shown Figure Each FIFO read with bus-size implementation automatically unloads data from FIFO output register auxiliary registers. Therefore, implementing port bus-size performing FIFO read before bytes words stored auxiliary registers have been read results loss unread data these registers. When reading data from FIFO byte word format, unused B0-B35 outputs remain inactive static, with unused FIFO output register bits holding last data value decrease power consumption. BYTE SWAPPING byte-order arrangement data read from FIFO changed synchronous rising edge CLKB. Byte-order swapping available mail register data. Four modes byte-order swapping (including swap) done with data port size selection. order bytes rearranged within long word, order within bytes remaines constant. Byte arrangement chosen port Swap select (SW0, SW1) inputs CLKB rising edge that reads long word from FIFO. byte order chosen first byte first word long word read from FIFO maintained until entire long word transferred, regardless states during subsequent reads. Figure example byte-order swapping available long word reads. Performing byte swap bus-size simultaneously FIFO read first rearranges bytes shown Figure then outputs bytes shown Figure PORT-B MAIL REGISTER ACCESS addition selecting port sizes FIFO reads, port Size select (SIZ0, SIZ1) inputs also access mail registers. When both SIZ0 SIZ1 HIGH, mail1 register accessed port long-word read mail2 register accessed port long-word write. mail register accessed immediately bus-sizing operation that underway unaffected mail register access. After mail register access complete, previous FIFO access resume next CLKB cycle. logic diagram Figure shows previous bus-size selection preserved when mail registers accessed from port port bus-size
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
BYTE ORDER PORT
Write FIFO
SIZ1 SIZ0
LONG WORD SIZE
Read from FIFO
SIZ1 SIZ0
1st: Read from FIFO
2nd: Read from FIFO
WORD SIZE BIG-ENDIAN
SIZ1 SIZ0
1st: Read from FIFO
WORD SIZE LITTLE-ENDIAN
2nd: Read from FIFO
SIZ1 SIZ0
1st: Read from FIFO
2nd: Read from FIFO
3rd: Read from FIFO 4th: Read from FIFO
BYTE SIZE BIG-ENDIAN
3145
Figure Dynamic Sizing
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
SIZ1 SIZ0
1st: Read from FIFO
2nd: Read from FIFO
3rd: Read from FIFO
BYTE SIZE LITTLE-ENDIAN
Figure Dynamic Sizing (Continued)
4th: Read from FIFO
3145
implemented each rising CLKB edge according states SIZ0_Q, SIZ1_Q, BE_Q. PARITY CHECKING port data inputs (A0-A35) port data inputs (B0B35) each have four parity trees check parity incoming outgoing) data. parity failure more bytes port data reported level port Parity Error Flag (PEFA). parity failure more bytes port data inputs that valid bus-size implementation reported level port Parity Error Flag (PEFB). Even parity checking selected, Parity Error Flags ignored this feature desired. Parity status checked each input according level Odd/Even parity (ODD/EVEN) select input. parity error more valid bytes port reported level corresponding port Parity Error Flag (PEFA, PEFB) output. Port bytes arranged A0-A8, A9-A17, A18-A26, A27-A35, port bytes arranged B0-B8, B9-B17, B18-B26, B27-B35, valid bytes those used port size implementation. When Odd/Even parity selected, port Parity Error Flag (PEFA, PEFB) byte port odd/even number levels applied bits.
CLKB
four parity trees used check A0-A35 inputs shared mail2 register when parity generation selected port-A reads (PGA HIGH). When port read from mail2 register with parity generation selected with LOW, HIGH, W/RA LOW, HIGH, HIGH, port Parity Error Flag (PEFA) held HIGH regardless levels applied A0-A35 inputs. Likewise, parity trees used check B0B35 inputs shared mail1 register when parity generation selected port reads (PGB HIGH). When port read from mail1 register with parity generation selected with LOW, HIGH, W/RB LOW, both SIZ0 SIZ1 HIGH, HIGH, port Parity Error Flag (PEFB) held HIGH regardless levels applied B0-B35 inputs. PARITY GENERATION HIGH level port Parity Generate select (PGA) port Parity Generate select (PGB) enables IDT723613 generate parity bits port reads from FIFO mailbox register. Port bytes arranged A0-A8, A9-A17, A18-A26, A27-A35, with most significant each byte used parity bit. Port bytes arranged B0-B8, B9-B17, B18B26, B27-B35, with most significant each byte used parity bit. write FIFO mail register stores levels
SIZ0 SIZ1
SIZ0 SIZ1
3145
Figure Logic Diagram SIZ0, SIZ1, Register
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
SWAP
BYTE SWAP
WORD SWAP
BYTE-WORD SWAP
3145
Figure Byte Swapping FIFO Reads (Long-Word Size Example)
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
applied nine inputs byte regardless state Parity Generate select (PGA, PGB) inputs. When data read from port with parity generation selected, lower eight bits each byte used generate parity according level ODD/EVEN select. generated parity bits substituted levels originally written most significant bits each byte word read data outputs. Parity bits FIFO data generated after data read from SRAM before data written output register. Therefore, port Parity Generate select (PGA) Odd/Even parity select (ODD/EVEN) have setup hold time constraints port Clock (CLKA) port Parity Generate select (PGB) ODD/EVEN select have setup hold time constraints port Clock (CLKB).
CLKA
These timing constraints only apply rising clock edge used read long word FIFO output register. circuit used generate parity mail1 data shared port (B0-B35) check parity circuit used generate parity mail2 data shared port (A0-A35) check parity. shared parity trees port used generate parity bits data mail register when port Chip Select (CSA, CSB) LOW, Enable (ENA, ENB) HIGH, Write/Read select (W/RA, W/RB) input LOW, mail register selected (MBA HIGH port both SIZ0 SIZ1 HIGH port port Parity Generate select (PGA, PGB) HIGH. Generating parity mail register data does change contents register.
tRSTH CLKB tRSTS tFSS tFSH
FS1,FS0 tWFF tREF tPAE tPAF tRSF
tWFF
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Figure Device Reset Loading Register with Value Eight
tCLK tCLKH CLKA HIGH tENH tENH tENH tENH Operation tENS tENH tENS tENH tCLKL
tENS tENS
tENS tENS ODD/ tPDPE Valid
NOTE: Written FIFO. Figure FIFO Write Cycle Timing
tPDPE Valid
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IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
CLKB HIGH
tENS tSWS SW1, tSZS tSZS SIZ1, SIZ0 PGB, ODD/ B0-B35 (0,0) tSZH tSZH (1,1)(1) tPGS (0,0) tPGH tDIS
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tENH tSWH
tENS
tENH
Operation
(1,1)
Previous Data
NOTES: SIZ0 HIGH SIZ1 HIGH selects mail1 register output B0-B35. Data read from FIFO1.
DATA SWAP TABLE FIFO LONG-WORD READS FIFO DATA WRITE A35-A27 A26-A18 A17-A9 A8-A0 SWAP MODE FIFO DATA READ B35-B27 B26-B18 B17-B9 B8-B0
Figure FIFO Long-Word Read Cycle Timing
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
CLKB HIGH
tENS tSWS SW1, tSZS tSZS (0,1) tSZH tSZH (1,1)(1) tPGS Little Endian Endian(2) B0-B17 B18-B35 (0,1) tPGH Previous Data Previous Data Read Read Read
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tENH tSWH Operation
SIZ1, SIZ0 PGB, ODD/
(1,1)
tDIS Read tDIS
NOTES; SIZ0 HIGH SIZ1 HIGH selects mail1 register output B0-B35. Unused word B0-B17 B18-B35 holds last FIFO1 output register data word-size reads.
DATA SWAP TABLE FIFO WORD READS
FIFO DATA WRITE A35-A27 A26-A18 A17-A9 A8-A0 SWAP MODE READ FIFO DATA READ BIG-ENDIAN B35-B27 B26-B18 LITTLE-ENDIAN B17-B9 B8-B0
Figure FIFO Word Read-Cycle Timing
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
CLKB HIGH
tENS tSWS SW1, tSZS tSZS SIZ1, SIZ0 PGB, ODD/ EVEN B0-B8 B27-B35 (1,0)
(1,1) tPGS
tENH tSWH Operation
tSZH tSZH (1,0)
(1,1) tPGH
(1,0)
(1,1)
(1,0)
(1,1)
Previous Data Previous Data
Read Read
Read Read
Read Read
tDIS Read tDIS Read
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NOTES: SIZ0 HIGH SIZ1 HIGH selects mail1 register output B0-B35. Unused bytes hold last FIFO output register data byte-size reads.
DATA SWAP TABLE FIFO BYTE READS
FIFO DATA READ FIFO DATA WRITE A35-A27 A26-A18 A17-A9 A8-A0 SWAP MODE READ BIGENDIAN B35-B27 LITTLEENDIAN B8-B0
Figure FIFO Byte Read-Cycle Timing
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
tCLKH CLKA HIGH tENS HIGH CLKB tSKEW1(1) tCLKH tCLK tCLKL tREF FIFO Empty SIZ1, SIZ0 tENH tENS tENH
tCLK
tCLKL
tREF
tENS
tENH
-B35
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NOTES: tSKEW1 minimum time between rising CLKA edge rising CLKB edge transition HIGH next CLKB cycle. time between rising CLKA edge rising CLKB edge less than tSKEW1, then transition HIGH occur CLKB cycle later than shown. Port size long word selected FIFO read SIZ1 LOW, SIZ0 LOW. port-B size word byte, last word byte read from FIFO, respectively.
Figure Flag Timing First Data Read when FIFO Empty
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
tCLKH CLKB SIZ1, SIZ0 HIGH -B35
tCLK
tCLKL
tENS
tENH
Next Word From FIFO
Previous Word FIFO Output Register
tSKEW1 CLKA
tCLKH
tCLK
tCLKL tWFF tWFF
FIFO Full HIGH tENS
NOTES: tSKEW1 minimum time between rising CLKB edge rising CLKA edge transition HIGH next CLKA cycle. time between rising CLKB edge rising CLKA edge less than tSKEW1, then transition HIGH occur CLKA cycle later than shown. Port size long word selected FIFO read SIZ1 LOW, SIZ0 LOW. port size word byte, tSKEW1 referenced from rising CLKB edge that reads last word byte long word, respectively. Figure Flag Timing First Available Write when FIFO Full
FIFO
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tENS
tENH tENH
CLKA tENS tSKEW2 CLKB
tENH
Long Words FIFO
tPAE tPAE
(X+1) Long Words FIFO tENH tENS
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NOTES: tSKEW2 minimum time between rising CLKA edge rising CLKB edge transition HIGH next CLKB cycle. time between rising CLKA edge rising CLKB edge less than tSKEW2, then transition HIGH CLKB cycle later than shown. FIFO write (CSA LOW, W/RA HIGH, LOW), FIFO read (CSB LOW, W/RB LOW, LOW). Port size long word selected FIFO read SIZ1 LOW, SIZ0 LOW. port size word byte, tSKEW2 referenced last word byte long word, respectively. Figure Timing when FIFO Almost-Empty
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
tSKEW2 CLKA tENS tPAF
[64-(X+1)] Long Words FIFO
tENH
tPAF
(64-X) Long Words FIFO
CLKB tENS
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tENH
NOTES: tSKEW2 minimum time between rising CLKA edge rising CLKB edge transition HIGH next CLKA cycle. time between rising CLKA edge rising CLKB edge less than tSKEW2, then transition HIGH CLKB cycle later than shown. FIFO write (CSA L0W, W/RA HIGH, LOW), FIFO read (CSB LOW, W/RB LOW, LOW). Port-B size long word selected FIFO read SIZ1 LOW, SIZ0 LOW. port size word byte, tSKEW2 referenced from last word byte read long word, respectively. Figure Timing when FIFO Almost Full
CLKA tENS tENS tENS tENS CLKB tPMF tPMF tENH tENH tENH tENH
SIZ1, SIZ0 tENS tMDV FIFO Output Register tPMR tDIS (Remains valid Mail1 Register after read)
4661
tENH
NOTE: Port-B parity generation (PGB LOW). Figure Timing Mail1 Register MBF1 Flag
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
CLKB tENS tENS SIZ1, SIZ0 CLKA tPMF tPMF tSZS tENS tSZH tENH tENH tENH
tENS
NOTE: Port-A parity generation (PGA LOW). Figure Timing Mail2 Register MBF2 Flag
tENH
tPMR
tDIS (Remains valid Mail2 Register after read)
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ODD/
tPOPE Valid
NOTE: HIGH.
tPOPE Valid Valid
tPEPE
tPEPE Valid
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Figure ODD/EVEN, W/RA, MBA,
PEFA Timing
ODD/
SIZ1, SIZ0 tPOPE Valid
NOTE: HIGH.
tPOPE Valid Valid
tPEPE
tPEPE Valid
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Figure ODD/EVEN, W/RB, SIZ1, SIZ0,
PEFB Timing
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
ODD/ A17, A26,
NOTE: HIGH. Figure Parity Generation Timing when Reading from Mail2 Register
tPEPB Mail2 Data
tPOPB Generated Parity
tPEPB Generated Parity
Mail2 Data
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ODD/ SIZ1, SIZ0 B17, B26,
NOTE: HIGH.
tPEPB tMDV Mail1 Data
tPOPB Generated Parity
tPEPB Generated Parity
Mail1 Data
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Figure Parity Generation Timing when Reading from Mail1 Register
TRANSFER CLOCK WRITE WRITE CLOCK (CLKA) CHIP SELECT
READ CLKB
CLKA
READ CLOCK (CLKB) CHIP SELECT EMPTY FLAG
WRITE SELECT WRITE ENABLE (ENA) ALMOST-FULL FLAG A0-A35 DATA (Dn) B0-B35 FULL FLAG
READ ENABLE (ENB) READ SELECT
723613 723613
A0-A35
ALMOST-EMPTY FLAG B0-B35 DATA (Qn)
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NOTES: Mailbox feature supported depth expansion applications. (MBA GND) Transfer clock should either Write Port Clock (CLKA) Read Port Clock (CLKB), whichever faster. Retransmit feature supported depth expansion applications. amount time takes last FIFO chain (i.e. valid data appear last FIFO's outputs) after word been written first FIFO delays each individual FIFO: 1)*(4*transfer clock) RCLK, where number FIFOs expansion TRCLK CLKB period. amount time takes first FIFO chain after word been read from last FIFO delays each individual FIFO: 1)*(3*transfer clock) 2*TWCLK, where number FIFOs expansion TWCLK CLKA period. Figure Block Diagram Synchronous FIFO Memory with Programmable Flags used Depth Expansion Configuration
IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING BYTE SWAPPING
COMMERCIAL TEMPERATURE RANGES
PARAMETER MEASUREMENT INFORMATION
1.1k From Output Under Test
PROPAGATION DELAY LOAD CIRCUIT
Timing Input Data, Enable Input VOLTAGE WAVEFORMS SETUP HOLD TIMES Low-Level Input VOLTAGE WAVEFORMS PULSE DURATIONS High-Level Input
Output Enable tPLZ Low-Level Output
tPZL tPZH In-Phase Output Input
High-Level Output
tPHZ VOLTAGE WAVEFORMS ENABLE DISABLE TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
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NOTE: Includes probe capacitance. Figure Load Circuit Voltage Waveforms
ORDERING INFORMATION
XXXXXX Device Type Power Speed Package Process/ Temperature Range BLANK 723613
NOTE: Industrial temperature range available special order.
Commercial (0°C +70°C) Thin Quad Flat Pack (TQFP, PN120-1) Plastic Quad Flat Pack (PQFP, PQ132-1) Commercial Only Power SyncFIFO
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Clock Cycle Time (tCLK) Speed Nanoseconds

IDT723613 Free-running CLKA CLKB asynchronous coincident (permits

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