Mapping Controller Operating voltage: 2.7V~5.2V External Crystal

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Mapping Controller Operating voltage: 2.7V~5.2V External Crystal

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HT16270
Mapping Controller
Operating voltage: 2.7V~5.2V External Crystal 32.768kHz oscillator Standby current <4µA bias, 1/16 duty, frame frequency 64Hz Max. patterns, commons, segments Built-in internal resistor type bias generator 3-wire serial interface kinds time base/WDT selection Time base overflow output
Built-in display address auto increment selectable buzzer frequencies (2kHz/4kHz) Power down command reduces power consumption Software configuration feature Data mode Command mode instructions Three data accessing modes VLCD adjust operating voltage
General Description
HT16270 peripheral device specially designed type used expand display capability. max. display segment device 1024 patterns also supports serial interface, buzzer sound, watchdog timer time base timer functions. HT16270 memory mapping multi-function controller. software configuration feature HT16270 make suitable multiple applications including modules display subsystems. Only three lines required interface between host controller HT16270. HT162X series have many kinds products that match various applications.
Selection Table
HT162X Built-in Osc. Crystal Osc.
HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
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HT16270
Block Diagram
Assignment
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HT16270
Assignment
Chip size: (mil)2 substrate should connected layout artwork.
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HT16270
Coordinates
-116.57 -116.68 -116.72 -116.72 -116.72 -115.93 -116.72 -116.72 -116.72 -115.94 -115.94 -115.94 -115.90 -115.97 -115.93 -115.93 -115.93 -115.93 -115.97 -115.93 -115.93 -115.94 -115.94 -108.08 -96.03 -89.43 -77.43 -70.82 -58.83 -52.17 -40.22 -33.58 -21.58 -14.98 -2.97 3.67 15.63 22.27 34.28 40.88 52.88 59.47 71.47 78.13 90.07 96.72 108.72 116.19 99.90 90.80 84.15 77.50 70.90 64.25 54.75 41.45 21.85 11.39 -0.60 -7.18 -19.21 -25.85 -37.85 -44.45 -56.45 -63.05 -75.05 -81.70 -93.65 -100.30 -112.37 -112.07 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.00 -112.05 -112.00 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.05 -112.00 -112.00 -112.05 -112.05 -112.00 -111.82 116.15 116.15 116.19 116.19 116.15 116.19 116.19 116.19 116.19 116.19 116.19 116.24 116.24 116.19 116.24 116.19 116.19 116.15 116.15 116.19 116.15 116.19 116.11 112.20 100.04 93.42 81.43 74.80 62.77 56.23 44.20 37.57 25.63 18.95 6.97 0.38 -11.65 -18.23 -30.22 -36.89 -48.92 -55.51 -67.45 -74.12 -86.15 -92.72 -104.72 -114.22
Unit:
-99.79 -93.16 -81.18 -74.54 -62.58 -55.93 -43.94 -37.40 -25.37 -18.70 -6.72 -0.09 11.90 18.49 30.51 37.10 49.09 55.76 67.75 74.38 86.36 93.03 104.85 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.24 112.20 112.24 112.24 112.24 112.24 112.29 112.24 112.24 112.25 112.25 112.25
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HT16270
Description
10~13 14~29 30~93
Name
DATA OSCI OSCO VLCD T1~T4 COM0~COM15 SEG0~SEG63
Description
Serial data input/output with pull-high resistor Negative power supply, Ground Crystal oscillator input Crystal oscillato output Positive power supply operating voltage input pad. Time base watchdog timer overflow flag, NMOS open drain output 2kHz 4kHz tone frequency output pair (Tristate output buffer) connected common outputs segment outputs Chip selection input with pull-high resistor. When logic high, data command read from write HT16270 disabled. serial interface circuit also reset. logic level input pad, data command transmission between host controller HT16270 enabled. READ clock input with pull-high resistor. Data HT16270 clocked rising edge signal. clocked data will appear data line. host controller next falling edge latch clocked data. WRITE clock input with pull-high resistor. Data DATA line latched into HT16270 rising edge signal.
Absolute Maximum Ratings*
Supply Voltage .-0.3V 5.5V Input Voltage. VSS-0.3V VDD+0.3V Storage Temperature. -50°C 125°C Operating Temperature. -25°C 75°C
*Note: These stress ratings only. Stresses exceeding range specified under "Absolute Maximum Ratings" cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability.
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HT16270
D.C. Characteristics
Symbol
IDD1 Ta=25°C
Parameter
Operating Voltage Operating Current Operating Current Standby Current Input Voltage Input High Voltage DATA DATA Common Sink Current Common Source Current Segment Sink Current Segment Source Current Pull-high Resistor
Test Conditions Conditions
load/LCD Crystal load/LCD Crystal load Power down mode DATA,
Min. Typ. Max. Unit
-1.8 -1.8 -180 -140
IDD2
ISTB
DATA, VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V DATA,
-0.9 -1.7 -0.9 -1.7
IOL1
IOH1
IOL2
IOH2
IOL3
IOH3
IOL4
IOH4
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HT16270
A.C. Characteristics
Symbol Parameter
Frame Frequency Common Period Serial Data Clock Pin) Serial Data Clock Pin) Serial Interface Reset Pulse Width (Figure tCLK Input Pulse Width (Figure Rise/Fall Time Serial Data Clock Width (Figure Setup Time DATA Clock Width (Figure Hold Time DATA Clock Width (Figure Setup Time Clock Width (Figure Hold Time Clock Width (Figure Write mode Read mode Write mode Read mode Duty cycle Number Duty cycle Crystal oscillator Ta=25°C
Test Conditions Conditions
Crystal oscillator
Min.
3.34 6.67 1.67 3.34
Typ.
n/fLCD
Max. Unit
fSYS
System Clock
fLCD tCOM fCLK1
fCLK2
tsu1
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HT16270
Figure
Figure
Figure
Functional Description
Display memory structure Time base watchdog timer (WDT)
static display organized into bits stores display data. contents directly mapped contents driver. Data accessed READ, WRITE READ-MODIFY-WRITE commands. following mapping from patterns.
time base generator share same divided (/256) counter. TIMER DIS/EN/CLR, DIS/EN/CLR EN/DIS independent from each other. Once timeout occurs, will remain logic level until command issued.
mapping
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HT16270
Timer configurations external clock selected source system frequency, command turns invalid power down mode fails carried until external clock source removed.
Buzzer tone output
following data mode command mode
Operation
READ WRITE READ-MODIFY-WRITE COMMAND
Mode
Data Data Data
simple tone generator implemented HT16270. tone generator output pair differential driving signals which used generate single tone.
Command format
Command
HT16270 configured software setting. There mode commands configure HT16270 resource transfer display data.
successive commands have been issued, command mode omitted. While system operating non-successive command non-successive address data mode, should previous operation mode will reset also. returns "0", operation mode should issued first.
Name
TONE TONE TONE
Command Code
0000-1000-X 010X-XXXX-X 0110-XXXX-X Turn-off tone output
Function
Turn-on tone output, tone frequency 4kHz Turn-on tone output, tone frequency 2kHz
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HT16270
Timing Diagrams
READ mode (command code
READ mode (successive address reading)
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HT16270
WRITE mode (command code
WRITE mode (successive address writing)
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HT16270
READ-MODIFY-WRITE mode (command code
READ-MODIFY-WRITE mode (successive address accessing)
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HT16270
Command mode (command code
Mode (data command mode)
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HT16270
Application Circuits
Notes: connection selected depending requirement voltage applied VLCD must lower than VDD. Adjust display, VDD=5V, VLCD=4V, VR=15k±20%. Adjust (external pull-high resistance) user's time base clock.
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HT16270
Command Summary
Name
READ WRITE READMODIFYWRITE
Command Code
Function
Read data from Write data Read Write data Turn both system oscillator bias generator Turn system oscillator Turn display Turn display Disable time base output
Def.
A7A6A5A4A3A2A1A0D0D1D2D3 A7A6A5A4A3A2A1A0 D0D1D2D3 A7A6A5A4A3A2A1A0 D0D1D2D3
0000-0000-X 0000-0001-X 0000-0010-X 0000-0011-X
TIMER 0000-0100-X TIMER
0000-0101-X 0000-0110-X 0000-0111-X
Disable time-out flag output Enable time base output Enable time-out flag output Turn tone outputs Clear contents time base generator Clear contents stage Tone frequency output: 4kHz Tone frequency output: 2kHz Disable output Enable output Time base clock output: time-out flag after: Time base clock output: time-out flag after: Time base clock output: time-out flag after: Time base clock output: time-out flag after: Time base clock output: 16Hz time-out flag after: Time base clock output: 32Hz time-out flag after:
TONE 0000-1000-X TIMER 0000-1101-X TONE TONE
0000-1111-X 010X-XXXX-X 0110-XXXX-X 100X-0XXX-X 100X-1XXX-X 101X-0000-X 101X-0001-X 101X-0010-X 101X-0011-X 101X-0100-X 101X-0101-X
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HT16270
Name
F128 TOPT NORMAL
Command Code
Function
Time base clock output: 64Hz time-out flag after: 1/16
Def.
101X-0110-X 101X-0111-X 1110-0000-X 1110-0011-X
Time base clock output: 128Hz time-out flag after: 1/32 Test mode Normal mode
Notes: Don't care A7~A0 address D3~D0 data Data/Command mode Def. Power reset default bold forms, namely mode commands. these, indicates command mode successive commands have been issued, command mode except first command will omitted. source tone frequency time base/WDT clock frequency derived from 32.768kHz crystal oscillator external 32kHz clock. Calculation frequency based system frequency sources stated above. recommended that host controller should initialize HT16270 after power reset, power reset fail, which turn leads malfunctioning HT16270.
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Mapping Controller Operating voltage: 2.7V~5.2V External Crystal

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