(Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japane

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(Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japane

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HD66730/HD66731
(Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japanese Kanji, Korean Font Display)
HD66730/1 dot-matrix liquid crystal display controller (LCD) driver that displays Japanese characters consisting kanji, hiragana katakana according Japanese Industrial Standard (JIS) Level-1 Kanji Set. HD66730/1 incorporates following five functions single chip: display control function matrix LCD, (ii) display store character codes, (iii) fonts support kanji, (iv) liquid crystal driver, booster drive LCD. 6-character (HD66730) four 10-character (HD66731) kanji display easily achieved receiving character codes bytes/character) from MPU. font includes 2,965 kanji from Level-1 Kanji Set, non-kanji characters, half-size alphanumeric characters symbols. Full-size fonts such Japanese kanji half-size fonts such alphanumeric characters displayed together. addition, display control equivalent full mapping performed through horizontal vertical dot-by-dot smooth scroll functions each display line. help make systems more compact, three-line clock synchronous serial transfer method adopted addition 8-bit interfacing with microcomputer.
Features
Dot-matrix liquid crystal display controller/driver supporting display kanji according Level-1 Kanji Large character generator ROM: kbits Kanji according Level-1 Kanji dots): 2,965-character font non-kanji dots): 524-character font Half-size alphanumeric characters symbols dots): 128-character font Display dots full-size fonts consisting kanji kana, dots half-size fonts alphanumeric characters symbols same display 2-line 6-character full-size font display with single chip (HD66730) 4-line 10-character full-size font display with single chip (HD66731) Expansion driver interface: maximum 2-line 20-character 4-line 10-character) display (HD66730) matrix font marks icons HD66731)
HD66730/HD66731
Various display control functions: horizontal smooth scroll units), vertical smooth scroll, white black inversion/blinking/white black inversion blinking character display, cursor display, display on/off Display data RAM: bytes (stores codes support characters full-size font) Character generator RAM: bytes (displays characters user font) 16-byte 96-segment Three-line clock synchronous serial bus, 8-bit interface Built-in double/triple liquid-crystal voltage booster circuit built-in oscillator (operating frequency adjusted through external resistors) Operating power supply voltage: 2.4V 5.5V; liquid crystal display voltage: 3.0V 13.0V HD66730: 1420-128 (0.5 pitch), bare-chip HD66731: TCP-171 (straight), TCP-206 (bent), chip with bump List Programmable Duty Cycles
Duty Drive Setting 1/14 1/27 1/40 1/53 Number Display Characters Full-Size Font HD66730 6-character 6-character HD66731 10-character 10-character Three 10-characters Four 10-characters Number Segments/Marks HD66730 71pcs 71pcs HD66731 96pcs 96pcs 96pcs 96pcs
Ordering Information
Type HD66730A00FS HCD66730A00 HD66731A00TA0L HD66731A00TB0L HCD66731A00BP HD66730A01FS HCD66730A01 HD66731A01TA0L HD66731A01TB0L HCD66731A01BP Package FP-128 Bare chip Straight Bending Au-bumped chip FP-128 Bare chip Straight Bending Au-bumped chip Number Display character 6-characters 6-characters Three 8-characters Four 10-characters Four 10-characters 6-characters 6-characters Three 8-characters Four 10-characters Four 10-characters Korean font (A01) CGROM Level-1 Kanji (A00)
HD66730/HD66731
Block Diagram (HD66730)
OSC1 OSC2
Oscillation circuit (CPG) RESET* Index register address counter (RAR: System interface Serial Display data (DDRAM) bits 25-bit shift register Common driver Control register Timing generator
COM25/ COMD
COM1 COM24 COMS
RS/CS* E/SCLK RW/SID DB0/SOD
SEGD data register (RDR: Busy flag (BF) Address generator Character Character generator generator half-size full-size character font character font (HCGROM) (FCGROM) 9,216 bits 506,880 bits (704 (768 SEG1 SEG71 71-bit shift register 71-bit latch circuit Segment driver
buffer
V5OUT2
Segment (SEGRAM) bytes Booster
Character generator (CGRAM) bytes
drive voltage selector
V5OUT3
Display attribute control circuit Cursol control circuit Parallel/serial converter scroll control circuit
HD66730/HD66731
Arrangement (HD66730)
SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71
HD66730 (Top view)
RESET* OSC2 OSC1 SEGD RW/SID RS/CS* E/SCLK DB0/SOD V5OUT2 V5OUT3
SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COMS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25/COMD
HD66730/HD66731
Dimensions (HD66731TA0: Three 8-characters)
Driver Output
0.24p (141-1) 33.60mm
Dummy Dummy COM40 COM20 SEG96 SEG1 COMS COM1 COM19 Dummy Dummy
0.24mm pitch
0.80mm pitch
OSC2 OSC1 TESED RESET* RW/SID RS/CS* E/SCLK DB0/SOD V5OUT2 V5OUT3
0.8p (30-1) 23.2mm
I/O, Power Supply
Dummy Dummy COM53 COM45 COM20 SEG119
HD66730/HD66731
Dimensions (HD66731TB0: Four 10-characters)
0.20p (176-1) 35.0mm
0.8p (30-1) 23.2mm
I/O, Power Supply 0.80mm pitch 0.20mm pitch
Driver Output
OSC2 OSC1 TESED RESET* RW/SID RS/CS* E/SCLK DB0/SOD V5OUT2 V5OUT3 SEG1 COMS COM1 COM19 COM46 COM51 Dummy Dummy
HD66730/HD66731
Location Bonding Pads (HD66730)
HCD66730
HD66730 Type code
Chip size Coordinate: Origin: size
7.48 6.46 center Chip center
(unit:
Coordinate Function SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 -2602 -2984 -3263 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 -3522 3012 3012 3012 3012 2782 2582 2341 2161 1981 1801 1621 1440 1260 1030 -101 -281 -462 -642 -822 -1002 -1182 -1363 -1543 -1723 -1939
Coordinate Function SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 RESET* OSC2 OSC1 SEGD RW/SID RS/CS* E/SCLK DB0/SOD -3522 -3522 -3522 -3522 -3522 -3160 -2860 -2660 -2435 -2233 -2063 -1859 -1689 -1519 -1349 -1179 -975 -771 -567 -363 -146 1154 1371 1533 1730 -2183 -2364 -2544 -2774 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2959
Coordinate Function V5OUT2 V5OUT3 COM25/D COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 1896 2057 2219 2478 2782 3016 3253 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 3522 -2959 -2959 -2959 -2959 -2984 -2984 -2984 -2984 -2806 -2626 -2445 -2265 -2085 -1855 -1625 -1444 -1264 -1084 -854 -624 -443 -263 1178
HD66730/HD66731
Coordinate Function COM4 COM3 COM2 COM1 COMS SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 3522 3522 3522 3522 3522 3522 3522 3522 3522 3222 2942 2662 2332 1409 1639 1819 1999 2179 2410 2590 2819 3012 3012 3012 3012 3012 Coordinate Function SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 2152 1972 1791 1611 1431 1251 1071 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 Coordinate Function SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 -191 -371 -551 -731 -912 -1092 -1272 -1452 -1632 -1813 -1993 -2173 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012 3012
HD66730/HD66731
Location Bonding Pads (HD66731)
Chip size Coordinate Origin 7.48 6.46mm2 center
Chip center bumped distance 80µm (Min.) Bump size 100µm 50µm
SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 CON38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM53 Dummy2
Dummy18 Dummy17 Dummy16 Dummy15 Dummy14 Dummy13 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SRG32 SEG31 SEG30 SEG29 Dummy12 Dummy11 Dummy10 Dummy9 Dummy8 Dummy7 Dummy6
Dummy1
HD66731
Type Code
SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COMS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 CON10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM46 COM47 COM48 COM49 COM50 COM51 Dummy5
HD66731 (Top view)
OSC2 Dummy3 V5OUT2 V5OUT2 V5OUT2 V5OUT3 V5OUT3 OSC1 RW/SID E/SCLK DB0/SOD TESTD RESET* RS/CS*
Dummy4
HD66730/HD66731
Coordinate Function Dummy3 OSC2 OSC1 TESTD RESET* RW/SID RS/CS E/SCLK DB0/SOD V5OUT2 V5OUT2 V5OUT2 V5OUT3 V5OUT3 dummy4 dummy5 -3202 -2926 -2722 -2543 -2339 -2135 -1931 -1727 -1523 -1306 -1090 -873 -656 -439 -223 1053 1189 1325 1461 1597 1733 1869 2005 2141 2277 2413 2549 2685 2821 2957 3093 3229 3474 3474 3474 3474 3474 3474 3474 3474 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2984 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2971 -2699 -2563 -2427 -2291 -2155 -2019 -1883 Coordinate Function COM51 COM50 COM49 COM48 COM47 COM46 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMS SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 -1621 -1541 -1460 -1379 -1298 -1218 -1137 -1056 -975 -895 -814 -733 -652 -572 -491 -410 -329 -249 -168 1043 1124 1205 1286 1366 1447 1528 1609 1689 1770 1851 1932 2012 2093 2174 Coordinate Function SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 dummy6 dummy7 dummy8 dummy9 dummy10 dummy11 dummy12 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 3474 3474 3474 3474 3474 3474 3474 3474 3202 3066 2930 2794 2658 2522 2343 2262 2182 2101 2020 1939 1859 1778 1697 1616 1536 1455 1374 1293 1213 1132 1051 -160 -241 2255 2335 2416 2497 2578 2658 2739 3027 3027 3027 3027 3027 3027 3027 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963
HD66730/HD66731
Coordinate Function SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 dummy13 dummy14 dummy15 dummy16 dummy17 dummy18 dummy1 -322 -402 -483 -564 -645 -725 -806 -887 -968 -1048 -1129 -1210 -1291 -1371 -1452 -1533 -1614 -1694 -1775 -1856 -1937 -2017 -2098 -2179 -2260 -2340 -2522 -2658 -2794 -2930 -3066 -3202 -3474 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 2963 3027 3027 3027 3027 3027 3027 3027 Coordinate Function SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 COM20 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 2728 2647 2567 2486 2405 2324 2244 2163 2082 2001 1921 1840 1759 1678 1598 1517 1436 1355 1275 1194 1113 1032 Coordinate Function COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM53 dymmy2 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -179 -260 -340 -421 -502 -583 -663 -744 -825 -906 -986 -1067 -1148 -1229 -1309 -1390 -1471 -1552 -1632 -1713 -1794 -1875 -1955 -2036 -2169 -2305 -2441 -2577 -2713 -2984
HD66730/HD66731
Function (HD66730)
Table
Signal RESET*
Functional Number Pins Device Interfaced with Function Acts reset input pin. initialized during level. Refer Reset Function. Must reset after power-on. Selects interface mode with MPU; Low: Serial mode High: 8-bit mode Selects registers during mode: Low: Index register (write); Status register (read) High: Control register (write); data (read/write) Acts chip-select during serial mode: Low: Select (access enable) High: selected (access disable) Selects read/write during mode; Low: Write High: Read Inputs serial data during serial mode. Starts data read/write during mode; Inputs (Receives) serial clock during serial mode. Seven high-order bidirectional tristate data pins. Used data transfer between HD66730. used busy flag. Open these pins during serial mode since these signals used. lowest bidirectional data (DB0) during mode. Outputs (transmits) serial data during serial mode. Open this reading (transmission) performed. Display data output signals segment extension driver. Acts common output signal segment display. Used display icon marks beside character display. Acts common output signals character display. COM15 toCOM24 become non-selective waveforms when duty ratio 1/14. Acts common output sign (COM25) character display when EXT2 Acts common extension pulse signal (COMD) when EXT2 grounded after RESET input cleared. When this signal used COMD, must maintained.
RS/CS*
RW/SID
E/SCLK
DB0/
SEG1 SEG71 COMS
COM1 COM24 COM25/ COMD
LCD/ extension driver
HD66730/HD66731
Table
Signal
Functional Description (cont. HD66730)
Number Pins Device Interfaced with Extension driver Function Outputs latch pulse segment extension driver.Cam also used shift clock common extention driver. Exters tristate when both EXT1 EXT2 Outputs shift clock segment extension driver. also used common extension driver latch clock. Enters tristate when both EXT1 EXT2 Outputs data extension driver. Data after 72nd output. Enters tristate when EXT1 Acts alternating current signal extension driver. Enters tristate when both EXT1 EXT2 bits Power supply drive (max) VCC: +2.4V +5.5V, GND: When crystal oscillation performed, external resistor must connected. When input external clock, must input OSC1. Inputs voltage booster generate liquid crystal display drive voltage. reference voltage power supply booster. Vci: 1.0V 5.0V VCC. Voltage input boosted twice output. When voltage boosted three times, capacitor with same capacitance that C1-C2 should connected here. Voltage input boosted three times output.
Extension driver
SEGD VCC/GND OSC1/ OSC2
Extension driver Extension driver Power supply Power supply Oscillation resistor/ clock
V5OUT2
pin/ booster capacitor
V5OUT3 C1/C2
Booster capacitor External capacitor should connected here when using booster.
HD66730/HD66731
Function (HD66731)
Table
Signal RESET*
Functional Number Pins Device Interfaced with Function Acts reset input pin. initialized during level. Refer Reset Function. Must reset after power-on. Selects interface mode with MPU; Low: Serial mode High: 8-bit mode Selects registers during mode: Low: Index register (write); Status register (read) High: Control register (write); data (read/write) Acts chip-select during serial mode: Low: Select (access enable) High: selected (access disable) Selects read/write during mode; Low: Write High: Read Inputs serial data during serial mode. Starts data read/write during mode; Inputs (Receives) serial clock during serial mode. Seven high-order bidirectional tristate data pins. Used data transfer between HD66731. used busy flag. Open these pins during serial mode since these signals used. lowest bidirectional data (DB0) during mode. Outputs (transmits) serial data during serial mode. Open this reading (transmission) performed. Display data output signals segment extension driver. Acts common output signal segment display. Used display icon marks beside character display. Acts common output signals character display. COM14 acts same COMS when 1/14 duty. COM27 acts same COMS when 1/27 duty. COM40 acts same COMS when 1/40 duty. Unused common pins output non-selective waveforms. Acts common output signal segment display when 1/53 duty. waveform same coms. This COM53 outputs non-selective waveform when another duty.
RS/CS*
RW/SID
E/SCLK
DB0/
SEG1 SEG119 COMS
COM1 COM51
COM53
HD66730/HD66731
Table
Signal VCC/GND OSC1/ OSC2
Functional Description (cont. HD66731)
Number Pins Device Interfaced with Power supply Power supply Oscillation resistor/ clock Function Power supply drive (max) VCC: +2.4V +5.5V, GND: When crystal oscillation performed, external resistor must connected. When input external clock, must input OSC1. Inputs voltage booster generate liquid crystal display drive voltage. reference voltage power supply booster. Vci: 1.0V 5.0V VCC. Voltage input boosted twice output. When voltage boosted three times, capacitor with same capacitance that C1-C2 should connected here. Voltage input boosted three times output.
V5OUT2
pin/ booster capacitor
V5OUT3 C1/C2 TESTD Dummy1 Dummy18
Booster capacitor External capacitor should connected here when using booster. Test pin. Must left disconnected. Dummy pads. These pads electrically floating level.
HD66730/HD66731
Function System Interface HD66730/1 system interfaces: synchronized serial 8-bit bus. Both selected pin. HD66730/1 five types 8-bit registers: index register (IDR), status register (STR), various control registers, address register (RAR), data register (RDR). index register (IDR) selects control registers, address register (RAR) data register (RDR) performing data transfer. status register (STR) indicates internal state system. Various control registers store display control data here. address register (RAR) stores address data display data (DDRAM), character generator (CGRAM), segment (SEGRAM). data register (RDR) temporarily stores data written into DDRAM, CGRAM, SEGRAM. Data written into from automatically written into DDRAM, CGRAM, SEGRAM internal operations. also used data storage when reading data from DDRAM, CGRAM, SEGRAM. Here, when address information written into RAR, data read then stored into from DDRAM, CGRAM, SEGRAM internal operations. Data transfer between then completed when reads RDR. After this read, data DDRAM, CGRAM, SEGRAM stored next address sent next data read from MPU. These registers selected register select signal (RS) read/write signal (R/W) 8-bit interface, start-byte data synchronized serial interface. Busy Flag When busy flag HD66730/1 internal operation mode, only status register (STR) accessed. busy flag (BF) output from (DB7). Access other registers performed only after confirming that busy flag Address Counter (RAR) address counter (RAR) provides addresses accessing DDRAM, CGRAM, SEGRAM. When initial address value written into counter (RAR), automatically incremented decremented Note that control register specifies which (DDRAM, CGRAM, SEGRAM) select.
HD66730/HD66731
Table
Register Selection
Operation write read Control register write, address register (RAR) write, data register (RDR) write data register (RDR) read
HD66730/HD66731
Display Data (DDRAM) Display data (DDRAM) stores character codes display attribute codes displaying data. full-size font displayed using bytes, half-size font displayed using byte. Since capacity bytes, full-size characters half-size characters stored. DDRAM displays only that data stored within range corresponding number display columns. Data stored outside range ignored. Refer Combined Display Full-Size Half-Size characters details character codes stored DDRAM. relationship between DDRAM addresses display position depends number display lines line/2 lines/4 lines). Execution display-clear instruction writes H'A0 corresponding half-size character ,,space" throughout DDRAM. Note: HD66730/1 performs display reading character codes from DDRAM according number display columns control register. particular, reading from DDRAM begins position corresponding rightmost character maximum number display columns. This means that byte two-byte full-size character code should position exceeding maximum number display columns. example, write fullsize code bytes) 12th 13th byte when display characters. 1-line display (NL1/0 bytes consecutive addresses from H'00 H'4F allocated DDRAM addresses. When there fewer than display characters full size), only number display characters specified NC1/0 displayed starting from H'00 DDRAM. example, bytes addresses from H'00 H'0B used when 6-character display (NC1/0 performed using HD66730; addresses from H'0C ignored. this case, write full-size code into bytes H'0B H'0C because half-size character displayed. Figure 1-line display. 2-line display (NL1/0 first line DDRAM address displayed bytes addresses from H'00 H'27, second line displayed bytes addresses from H'40 H'67. When there fewer than display characters full size), only number display characters specified NC1/0 will displayed starting from leftmost address DDRAM. example, bytes addresses from H'00 H'0B H'40 H'4B used when 6-character display (NC1/0 performed using HD66730. Addresses from H'0C H'4C ignored. Figure 2-line display. 4-line display (NL1/0 first line DDRAM address displayed from H'00 H'13, second line from H'20 H'33, third line from H'40 H'53, fourth line from H'60 H'73. 6-character display (NC1/0 full-size), only bytes from leftmost address DDRAM displayed. Figure 4-line display.
HD66730/HD66731
6-character display setting (NC1/0 20-character display setting (NC1/0 40-character display setting (NC1/0 Display position DDRAM address
Display position DDRAM address
Display position DDRAM addres
Figure 1-Line Display (NL1/0
6-character display setting (NC1/0 Display position line DDRAM address line DDRAM address Display position line DDRAM address line DDRAM address Display position line DDRAM address line DDRAM address
10-character display setting (NC1/0
20-character display setting (NC1/0
Figure 2-Line Display (NL1/0
6-character display setting (NC1/0 Display position line DDRAM address line DDRAM address line DDRAM address line DDRAM address Display position line DDRAM address line DDRAM address line DDRAM address line DDRAM address
10-character display setting (NC1/0
Figure 4-Line Display (NL1/0
HD66730/HD66731
Character Generator Full-Size Font (FCGROM) character generator full-size font (FCGROM) generates 3,840 full-size character patterns from 12-bit character code. This includes 2,965 kanji according Level-1 Kanji non-kanji. Table shows relationship between character codes DDRAM full-size font patterns. Refer Combined Display Full-Size Half-Size Characters relationship between codes character codes DDRAM. Character Generator Half-Size Font (HCGROM) character generator half-size font (HCGROM) generates character patterns from 7-bit character codes. half-size font (alphanumeric characters symbols) displayed together with full-size font. Refer Combined Display Full-Size Half-Size Characters details. Character Generator (CGRAM) character generator (CGRAM) allows user display arbitrary full-size font patterns. display fonts. This also display double-size characters figures combining multiple CGRAM fonts. Specify character codes from H'000 H'007 full size character code when displaying font patterns stored CGRAM. Segment (SEGRAM) segment (SEGRAM) used control icons marks segment units user program. Bits SEGRAM corresponding segments displayed directly MPU, regardless contents DDRAM CGRAM. SEGRAM read displayed when COMS output selected. icons displayed using single HD66730. icons displayed expanding drivers segment side. SEGRAM data stored eight bits. lower bits control display each segment, upper bits control segment blinking. HD66731 display icons without expanding driver.
HD66730/HD66731
Timing Generator timing generator generates timing signals operation internal circuits such DDRAM, FCGROM, HCGROM, CGRAM, SEGRAM. read timing display internal operation timing access generated separately avoid interference. This prevents undesirable interferences, such flickering, areas other than display area when writing data DDRAM, example. timing generator HD66730 generates interface control signals CL1, CL2, COMD-output extension drivers extension configuration. Display Attribute Controller display attribute controller displays white/black inverse, blinking, white/black inverse blinking full size font FCGROM according attribute code DDRAM. Refer Display Attribute Designation details. Fonts CGRAM patterns SEGRAM control display attributes using upper bits (bits each display-pattern data. Cursor Control Circuit cursor control circuit used produce cursor displayed character corresponding DDRAM address address counter (RAR). Cursors chosen from three types: 12th raster-row cursor that displayed only 12th raster-row each font; blink cursor that periodically displays whole font black white black inverted cursor that periodically displays font white black (see Figure Note that when address counter (RAR) selecting CGRAM SEGRAM, cursor would generated that address, however, does have meaning. Note: display line consists raster-rows. Smooth Scroll Control Circuit smooth scroll control circuit used perform smooth-scroll units dots. When number characters displayed greater than that possible time liquid crystal module, this horizontal smooth scroll used display characters easy-to-read manner each line. Refer Horizontal Smooth Scroll details each line.
HD66730/HD66731
Liquid Crystal Display Driver Circuit liquid crystal display driver circuit HD66730 consists common signal drivers segment signal drivers. HD66731 common signal drivers segment signal drivers. When liquid crystal driver duty ratio program, necessary common signal drivers output drive waveforms remaining common drivers output non-selected waveforms. addition, drivers expanded common segment sides through register settings. Display pattern data sent serially through shift register latched when needed data arrived. latched data then enables driver generate drive waveform outputs. This serial data sent from display pattern that corresponds last address DDRAM latched when character pattern display data corresponding first address enters internal shift register. Booster booster outputs voltage that three times higher than reference voltage input from Vci. Since voltage generated from operation power supply, this circuit operate with single power supply. Refer Power Supply Liquid Crystal Display Drive details. Oscillator HD66730/1 performs oscillation adding single external oscillation resistor. oscillation frequency corresponding display size frame frequency adjusted changing oscillation resistor. Refer Oscillator details.
HD66730/HD66731
Table Relationship between Full-Size Character Code Kanji
Upper Lower
HD66730/HD66731
Table Relationship between Full-Size Character Code Kanji (cont)
Upper Lower
HD66730/HD66731
Table Relationship between Full-Size Character Code Kanji (cont)
Upper Lower
HD66730/HD66731
Table Relationship between Full-Size Character Code Kanji (cont)
Upper Lower
HD66730/HD66731
Table Relationship between Full-Size Character Code Non-Kanji
Upper Lower
HD66730/HD66731
Table Relationship between Half-Size Character Code Character Pattern (ROM Code: A00)
Upper bits) Lower bits)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
xxxx
(Space)
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
HD66730/731 Korean font 5601-1992 subset)
HD66730/HD66731
Relationship between Character Codes (DDRAM), CGRAM Addresses, Display Characters
Full size character codes H'000 H'007 used access character patterns CGRAM. Since each character pattern displayed dots, CGRAM patterns displayed immediately next each other right, left, top, bottom) without character spaces between them. Table shows correspondence between CGRAM addresses full-size character codes access CGRAM MPU. Table Relationship between Character Codes (DDRAM), CGRAM Addresses, Display Characters
Character Code CGRAM Data D7D6 D4D3 D2D1 D5D4D3D2D1D0
CGRAM Address
Character pattern
Character pattern
Character pattern
HD66730/HD66731
Notes: CGRAM selected when upper bits C11) full size character codes this case, lower bits character code correspond bits bits: types) CGRAM address. CGRAM address bits designate character pattern line position. 12th line cursor position display formed logical with cursor. CGRAM address (A0) corresponds left-half right-half full-size character pattern. character data stored with rightmost character element (LSB), shown table above. Pattern produced bits displayed raster-rows displayed together. Thus, arbitrary character pattern consisting dots displayed. CGRAM data corresponds display selection, non-selection. upper bits (AA) CGRAM data indicate display attribute lower 6-bit pattern. this case, display attributes specified DDRAM during full-size character display disabled. When these upper bits CGRAM pattern simply displayed set; when pattern reverses (black/white), when pattern blinks; when pattern reverses blinks.
HD66730/HD66731
Relationship between SEGRAM Addresses Display Patterns
SEGRAM data displayed when select level COMS output. Since SEGRAM data does depend character code data DDRAM, does undergo horizontal smooth scroll, used display icon marks. following shows relationship between SEGRAM addresses segment output pins. Table Relationship between SEGRAM Addresses Display Patterns
SEGRAM Address SEG1 SEG7 SEG13 SEG19 SEG25 SEG31 SEG37 SEG43 SEG49 SEG55 SEG61 SEG67 SEG73 SEG79 SEG85 SEG91
SEGRAM Data SEG2 SEG8 SEG14 SEG20 SEG26 SEG32 SEG38 SEG44 SEG50 SEG56 SEG62 SEG68 SEG74 SEG80 SEG86 SEG92 SEG3 SEG9 SEG15 SEG21 SEG27 SEG33 SEG39 SEG45 SEG51 SEG57 SEG63 SEG69 SEG75 SEG81 SEG87 SEG93 SEG4 SEG10 SEG16 SEG22 SEG28 SEG34 SEG40 SEG46 SEG52 SEG58 SEG64 SEG70 SEG76 SEG82 SEG88 SEG94 SEG5 SEG6
SEG11 SEG12 SEG17 SEG18 SEG23 SEG24 SEG29 SEG30 SEG35 SEG36 SEG41 SEG42 SEG47 SEG48 SEG53 SEG54 SEG59 SEG60 SEG65 SEG66 SEG71 SEG72 SEG77 SEG78 SEG83 SEG84 SEG89 SEG90 SEG95 SEG96
Blinking control
Pattern on/off
Notes: SEG1 SEG71 numbers segment output driver HD66730. SEG1 positioned left edge display. Segments from SEG72 displayed extension drivers. After display performed from SEG1 again. lower bits indicate display on/off each segment. setting selects display while selects display. Pattern blinking lower bits controlled upper bits SEGRAM data. When upper bits segments whose corresponding bits lower bits will blink display. When upper bits only bit-5 pattern blink. attempt upper bits (setting prohibited).
HD66730/HD66731
Register Functions
Outline Data written from internal control registers internal HD66730/1 8-bit interface serial interface. There five types internal control registers, follows (details described later): Index register: Selects designates which control register access Status register: Indicates internal state Control registers: Designates display control address register: Sets address accessing various RAMs data register: Receives transmits data from various RAMs
Table shows instruction list number execution cycles each instruction after performing register setting. Instructions that perform data transfer with data register tend used most. However, auto-incrementation auto decrementation internal HD66730/1 addresses after each data write lighten program load MPU. Note that when instruction being executed (internal operations being performed), only busy flag status register read. Since busy flag during execution, should check this value before accessing register. When accessing register without checking busy flag, interval longer than instruction execution time needed before next access. Refer Table Instruction Registers, instruction execution times. When rewriting DDRAM, character display will momentarily breakdown data (character codes) that being rewritten also being read system display. this reason, check display read line position (NF) display read raster-row position (LF) status register (SR), rewrite DDRAM line that being read displayed.
HD66730/HD66731
Functional Index Register (IR) index register (Figure designates control registers R7), address register (RAR: R8), data register (RDR: R9). register number must between addresses 0000 1001 binary digits. Note that address 1111 set, test register will selected. Addresses 1010 1110 ignored.
Figure Index Register
HD66730/HD66731
Status Register (ST) status register (Figure includes busy flag (BF), display line bits (NF1/0), display raster-row bits (LF0 LF3). instruction being executed, another instruction will accepted during this time. attempt write data register this time ignored. Rasters-rows driven time according specific timing perform liquid crystal display. Bits indicate display lines, bits indicate raster-row line. character display degenerates when rewriting DDRAM, rewrite only those display lines that currently being read system display. During segment display, next state last raster-row character display read out. Table
Display State According
Display State Displaying first line Displaying second line Displaying third line Displaying fourth line
Table
Display State According
Display State Displaying first raster-row Displaying second raster-row Displaying third raster-row Displaying fourth raster-row Displaying 13th raster-row
Figure Status Register
HD66730/HD66731
Entry Mode Register (R0) entry mode register (Figure includes bits I/D, RM1, RM0. I/D: Increments (I/D decrements (I/D DDRAM address when character code written into read from DDRAM. When DDRAM address incremented cursor blinking will also shift right. This applies both CGRAM SEGRAM. RM1/0: Selects DDRAM, CGRAM, SEGRAM access (Table 10). Table
Selection
Selected Display data (DDRAM) Character generator (CGRAM) Segment (SEGRAM)
Figure Entry Mode Register
HD66730/HD66731
Function Register (R1) function register (Figure includes bits BST, EXT2, EXT1, DT1, DT0, DCL. BST: When booster starts operate. When voltage external, stop operation internal booster. addition, consumption current suppressed stopping booster when entering standby mode without display. EXT2/1: Extends common driver segment driver HD66730. EXT2 extend driver common side duty ratio 1/40 1/53. Extend driver segment side setting EXT1 when displaying more digits full size) horizontal direction. DDRAM capacity bytes. When HD66731, these EXT2/1 bits must DT1/0: Selects duty ratio (Table 11). Although this separately from display line designation (NL1/0), duty ratio must selected that will smaller than number display lines. DCL: When display cleared writing code half-size space (H'A0) into DDRAM addresses. Then H'00 written into address counter (RAR) DDRAM selected. character code character code H'A0 must blank pattern when rewriting HCGROM used half-size characters. Cursor Control Register (R2) cursor control register includes bits CHM, CM1, CM0. CHM: When DDRAM selected, address counter (RAR) cursor home instruction executed. contents DDRAM change. cursor blinking moves left edge display (the left edge first line lines displayed). When cursor display turned cursor displayed position corresponding count value address counter (RAR). data RAR, index register (IDR) 1000 select modify data RAR. Note that address counter (RAR) automatically increments (decrements) when accessed, cursor will move accordingly. CM1/0: Selects cursor display mode (Table Figure blinking frequency (cycle) blink cursor white/black inverted cursor frames.
HD66730/HD66731
Table
Duty Drive Ratio
Duty Drive Ratio 1/14 duty drive 1/27 duty drive 1/40 duty drive 1/53 duty drive
Table
Cursor Mode Selection
Selected Cursor Mode 12th raster-row cursor Blink cursor White/black inverted cursor
EXT2 EXT1
Figure Function Register
Figure Cursor Control Register
HD66730/HD66731
Cursor Normal display example 12th-raster-row display example
Alternating display Blink display example
Alternating display iii) White/black inverted display example
Figure Cursor Display Examples
HD66730/HD66731
Display Control Register (R3) display control register (Figure includes bits When display control register enters standby mode. internal operation clock divided into Data cannot displayed panel, however, consumption current suppressed during standby mode. Note that register setting value data inside maintained. When character display turned When segment display turned selectively display marks. Display Control Register (R4) NC1/0: Selects display character horizontal direction. When performing horizontal smooth scroll, number display characters larger than actual number liquid crystal drive characters. When frame frequency (cycle) stable, operation frequency proportional display characters. Operation frequency must suppressed setting number display character small possible because consumption current proportional operation frequency. Refer Oscillator details. NL1/0: Sets number display lines. number display lines larger than duty drive ratio (DT1/0). these bits. Table indicates settings display lines. Table Display Control Register Setting
Display Characters: NC1/0 1-line characters 2-line characters 4-line characters 1-line characters 2-line characters Setting inhibited. 4-line characters 4-line characters 1-line characters 2-line characters
Display Lines NL1/0
Figure Display Control Register
Figure Display Control Register
HD66730/HD66731
Scroll Control Register (R5) scroll control register (Figure includes bits SN1, SN0, SL3, SL2, SL1, SL0. SN1/0: Selects starting line displayed. When SN1/0 shows display begins from first line. When SN1/0 shows display begins from second, third, fourth line, respectively. these bits within display line setting (NL1/0). used display smooth scroll DDRAM memory bank switching. SL3: Selects scroll starting raster-row line start display line (SL1/0). When these bits show 0000, display line starting from head raster-row (first raster-row) displayed 1100 (13th raster-row) showing last raster-row. vertical smooth scroll performed sequentially incrementing first raster-row. Refer Vertical Smooth Scroll details. Note that bits that value above 1100 will operate correctly. Scroll Control Register (R6) scroll control register (Figure includes bits PS1, PS0, SE4, SE3, SE2, SE1. PS1/0: Selects partial smooth scroll mode. When PS1/0 bits characters scroll horizontally across display. When bits PS1/0 only leftmost character fixed remaining characters perform horizontal smooth scroll display. When bits PS1/0 leftmost bits, when three leftmost characters fixed remaining characters perform horizontal smooth scroll Refer Partial Smooth Scroll details. SE4: These bits enable scroll display lines designated scroll control register (R7). When first line scrolled according scroll control register (R7). When second line scrolls independently, when third line scrolls independently, when fourth line scrolls independently. Scrolling multiple lines same time also possible.
Figure Scroll Control Register
Figure Scroll Control Register
HD66730/HD66731
Scroll Control Register (R7) scroll control register (Figure includes bits SQ5, SQ4, SQ3, SQ2, SQ1, SQ0. SQ5: These bits designate number dots horizontally scrolled left panel. Horizontal smooth scroll performed number dots between inclusive using non-display DDRAM area. When these bits 000000, scrolling performed. When these bits 110000, dots scrolled left. these bits value above 110000, dots still scrolled. Refer Horizontal Smooth Scroll details. Address Register (R8) address register (Figure15) initially contains address which incrementation (decrementation) starts. selection bits (RM1/0) entry mode register (R0) select which access (DDRAM/CGRAM/SEGRAM). When DDRAM (RM1/0 selected, address allocation differs according number display lines, cases most significant (RA7) ignored. During 1-line display (NL1/0 00), addresses H'00 H'4F allocated that line. During 2-line display, addresses H'00 H'27 allocated first line, addresses H'40 H'67 allocated second line. During 4-line display, addresses H'00 H'13 allocated first line, H'20 H'33 second H'40 H'53 third, H'60 H'73 fourth. Table When CGRAM (RM1/0 selected, addresses H'00 H'19 allocated first character addresses H'20 H'39 allocated second character, (Table 15). setting addresses between characters (example: H'1A H'1F) ignored here. When SEGRAM selected (RM1/0 11), addresses allocated upper four bits ignored (Table 16).
Figure Scroll Control Register
Figure Address Register
HD66730/HD66731
Table DDRAM Address Allocation
1-Line Display (NL1/0 H'00 H'4F 2-Line Display (NL1/0 H'00 H'27 H'40 H'67 4-Line Display (NL1/0 H'00 H'13 H'20 H'33 H'40 H'53 H'60 H'73
Displayed Lines First line Second line Third line Fourth line
Table
CGRAM Address Allocation
CGRAM Address H'00 H'19 H'20 H'39 H'40 H'59 H'60 H'79 H'80 H'99 H'A0 H'B9 H'C0 H'D9 H'E0 H'F9
Displayed Character First character Second character Third character Fourth character Fifth character Sixth character Seventh character Eighth character
Table
SEGRAM Address Allocation
SEGRAM Address
Displayed Segment SEG1 SEG6 SEG7 SEG12 SEG13 SEG18 SEG19 SEG24 SEG25 SEG30 SEG31 SEG36 SEG37 SEG42 SEG43 SEG48 SEG49 SEG54 SEG55 SEG60 SEG61 SEG66 SEG67 SEG72 SEG73 SEG78 SEG79 SEG84 SEG85 SEG90
SEG91 SEG96 Note: SEG72 SEG96 driven extension drivers.
HD66730/HD66731
Data Register (R9) This register (Figure stores 8-bit data that written read from DDRAM, CGRAM, SEGRAM address indicated address counter (RAC). selection (RM1/0) selects (DDRAM, CGRAM, SEGRAM). After said accessed, address automatically incremented (decremented) according bit. Note that selection bits (RM1/0) address register (R8) must before reading. not, first data read invalid. read instructions continue executed, however, data will read correctly from second read. Test Register (RF) This test register (Figure must H'00 times. This register automatically cleared (H'00) reset input; however, must cleared software after power-on reset used.
Figure Data Register
Figure Test Register
HD66730/HD66731
Table Instruction Registers
Code Description Execution Clock Cycle
Reg. Index (Hex) Register Index (IDR)
Designates register number instruction register access. 0000: 1001: Indicates busy flag (BF), display read line position (NF1/0), display read rasterrow position(NL0 NL3).
Status (STR)
Entry mode (EMR)
Designates address crementation decrementation (I/D) selection (RM1/0).
Function (FSR)
EXT2 EXT1
Clears display (DCL) initializes DDRAM address. Other: Selects duty drive ratio(DT1/0), enables extension driver (EXT2/1) sets booster operation
Cursor control (CCR)
Designates cursor-on cursor display mode(CM1/0). Executes cursor home (CHM) instruction. Designates standby mode (ST), character display (DC), segment display (DS).
Display control (DCR1)
Display control (DCR2) Scroll control (SCR1) Scroll control (SCR2) Scroll control (SCR3)
Sets number display characters(NC1/0) display lines(NL1/0). Sets display start line (SN1/0) start raster-row (ST0 ST3).
Designates partial scroll columns (PS1/0) scroll display line enable(SE1 SE4). Sets number dots scrolled (SQR0 SQR5).
HD66730/HD66731
Table Instruction Registers (cont)
Code Description Resets address address counter DDRAM/CGRAM/ SEGRAM. selected RM1/0. Writes reads data from DDRAM/CGRAM/ SEGRAM. selected RM1/0. This test register. this register. Execution Clock Cycle
Reg. Index (Hex) Register address (RAR)
data (RDR)
Test (TSR)
Note: execution time depends input oscillation frequency.
NF1/0: LF3: RM1/0: EXT2 EXT1 DT1/0: CM1/0: NC1/0: NL1/0: SN1/0: SL3: PS1/0: SE4: SQ5: RA7: RD7:
Internal processing being performed Position display read line Position display read raster-row Address increment Address decrement selection (00/01: DDRAM. (10: GGRAM, SEGRAM) Booster Common driver extension enable Segment driver extension enable Duty ratio (00: 1/14, 1/27, 1/40, 1/53) Executes display-clear instruction Executes cursor-home instruction Cursor Designates cursor mode (00: 12th raster-row, blinking, white/black inverse) Standby mode Character display Segment display Sets number display characters characters) Sets number display lines (00: line, lines, lines) Designates line start displaying (00: first line, second line, third line, fourth line) Designates scroll starting raster-row(0000: first raster-row, 1100: 13th raster-row) Designates partial scroll (00: columns scroll. leftmost column fixed, leftmost columns fixed, three leftmost columns fixed) Designates which line scroll enables first line scrolled, etc.) Number dots scroll dots) address data
HD66730/HD66731
Reset Function
HD66730/1 reset setting RESET level. During reset, system performs nextcontrol-register setting executes instructions. busy flag (BF) therefore indicates busy state this time, which means that only index register status register accessed. Display clear (DDRAM reset) performed automatically reset input. Since more than 1,000 clocks execution cycles needed initialize DDRAM, reset period must more than this number. Note that reset input conditions specified Electrical Characteristics satisfied, HD66730/1 will operate correctly, reset should performed software. Initialization Instruction Register Function Index Register: index register cannot initialized reset. After reset release, index register must access control register. Status register: Busy state Entry mode register: (incrementation) RM1/0 DDRAM selection Function register: Booster EXT2/1 Driver extension enable DT1/0 1/53 duty drive Display-clear execution Note: least 1,000 clock cycles execution time needed clear DDRAM.
HD66730/HD66731
Cursor control register: Cursor home execution Cursor display CM1/0 12th raster-row cursor display mode Display control register Standby mode clear Character display Segment display Display control register NC1/0 6-column display mode NL1/0 1-line display mode Scroll control register SN1/0 Starts displaying from first line. 0000: Starts displaying from first raster-row. Scroll control register PS1/0 Partial scroll release 0000: Disables scrolling lines. Scroll control register 000000: Number dots scrolled address register: address register automatically incremented during reset when display-clear executed. Note that after reset released, this register must reset software before accessing RAM.
HD66730/HD66731
Initial Setting Functions Bus/serial interface input level selects 8-bit serial interface. 8-bit interface, data written into index register read from status register according level R/W. Note that must held during this time. serial interface, data written into index register according R/W. Note that must during this time. During reset, only index register status register cannot accessed. driver output Since segment drivers (pins SEG1 SEG71/119) display-off state during reset, they output non-selective levels (V2/V3 level) during reset. this time, 4-line 6-character display alternates current. Common drivers (pins COM1 COM24/53 COMS) output non-selective levels (V1/V4 level) during reset, alternate current 4-line 6-character display. Note: Pins COM25/COMD HD66730 grounded (0V) during reset. When COM25 used without expanding drivers common side, display performed using liquid crystal drive voltage. this case, adjust liquid crystal voltage during reset. Extension driver interface output (HD66730) Since bits EXT2/1 during reset, extension performed both segment side common side. outputs oscillation (operation) frequency clock. Pins output signals cycle corresponding 4-line 6-character display size. addition, pins SEGD COM25/COMD output (ground level) since display turned off. Booster output operation internal booster stops because becomes during reset. Note: potential pins V5OUT2 V5OUT3 increases about +0.7 with respect level when booster stops. When using external polarized capacitors, make sure that reverse bias occurs.
HD66730/HD66731
Interfacing
HD66730/1 enters 8-bit interface mode when high. HD66730/1 interface with port. serial interface when there restraints wiring width. Instruction executed when data written into control register. this case, only status register read (busy check, etc.). this case, check busy flag when accessing (polling), insert interval considering execution time perform next access when internal process completely finished. instruction execution time depends HD66730/1 operation frequency. When using internal oscillation circuit HD66730/1, instruction time will change oscillation frequency does. Figure shows example 8-bit data transfer timing sequence. Figure shows example interface between HD66730/1 8-bit microcomputers.
Internal signal Internal operation (busy) Data Busy Busy Busy Data Control register write Busy flag check Busy flag check Busy flag check Index register write
Figure Example 8-bit Data Transfer Timing Sequence
H8/325
HD66730 HD66731
port interface
Figure Example Interfacing with 8-Bit Microcomputers
HD66730/HD66731
Transferring Serial Data
HD66730/1 enters serial interface mode when low. three-line clock-synchronous transfer method used. HD66730/1 receives serial input data (SID) transmits serial output data (SOD) synchronizing with transfer clock (SCLK) sent from master side. When HD66730/1 interfaces with several chips, chip select (CS*) must used. transfer clock (SCLK) input activated making chip select (CS*) low. addition, transfer counter HD66730/1 reset serial transfer synchronized making chip select (CS*) high. Here, since data which being sent reset cleared, restart transfer from first this data. minimum system where single HD66730/1 interfaces single MPU, interface constructed from transfer clock (SCLK) serial input data (SID). this case, chip select (CS*) should fixed low. transfer clock (SCLK) independent operational clock (CLK) HD66730/1. However, when several instructions continuously transferred, instruction execution time determined operational clock (CLK) (see Continuous Transfer) must considered since HD66730/1 does have internal transmit/receive buffer. Figure shows basic procedure transferring serial data. begin with, transfer start byte. receiving five consecutive bits (synchronizing string) beginning start byte, transfer counter HD66730/1 reset serial transfer synchronized. bits following synchronizing string bits) specify transfer direction (R/W bit) register select bit). sure transfer bit. After receiving start byte, instructions received data/busy flag transmitted. When transfer direction register select remain same, data continuously transmitted received. transfer protocol described detail following.
HD66730/HD66731
Serial data input (receiving) (input)
SCLK (input) (input)
Synchronizing string
Lower data byte
Upper data byte Instruction
Start byte
Serial data output (transmitting) (input)
SCLK (input) (input) (output) Synchronizing string Start byte
Lower data
Upper data
Status/data read
Figure Basic Procedure Transferring Serial Data
HD66730/HD66731
Receiving (write) After receiving start synchronizing string, start byte, 8-bit instruction received bytes: lower bits instruction placed first byte, higher bits instruction placed second byte. sure transfer following bits each byte. When instructions received with unchanged, continuous transfer possible (see Continuous Transfer following). Transmitting (read) After receiving synchronizing string, start byte, 8-bit read data transmitted from same receiving. When read data transmitted with unchanged, continuous transfer possible (see Continuous Transfer following). status register (SR) read when data read when after designating data register (R9) with index register (IR). Bits RM1/0 entry mode register (R0) select RAM. When reading data, interval longer than reading time must taken after start byte been accepted before first data been read out. During transmission (data output), input continuously monitored start synchronizing string (11111). Once this been detected, bits received. Accordingly, must always input when transmitting data continuously. Continuous Transfer When instructions received with unchanged, continuous receive possible without inserting start byte between instructions. After receiving last (the byte) instruction, system begins execute execute next instruction, instruction execution time HD66730/1 must considered. last (the byte) next instruction received during execution previous instruction, instruction will ignored. addition, next unit data read before read execution previous data completed data, normal data sent. transfer data normally, busy flag must checked. However, amount wiring used transmission needs reduced, burden polling needs lightened, transfer performed without reading busy flag. this case, insert transfer wait between instructions that current instruction time complete execution. Figure shows procedure continuous data transfer.
HD66730/HD66731
Continuous data write polling processing SCLK (input) (input) (output) Instruction execution time Continuous data write wait insert Wait SCLK (input) (input) Instruction byte byte Instruction byte byte Instruction execution time Wait Instruction byte byte Instruction execution time Instruction execution time
Start byte
Instruction byte byte
Start byte Busy read
Start byte
Instruction byte byte
Instruction waiting time (not busy state)
Start byte
iii) Continuous data write wait insert SCLK (input) (input) (output) data read time Wait Start byte Data read data read time Data read data read time Wait Wait
Figure Procedure Continuous Data Transfer
HD66730/HD66731
Combined Display Full-Size Half-Size Characters
HD66730/1 performs display from left edge display combining 12-dot full-size (character size: dots) 6-dot half-size characters (character size: dots). There will one-dot space between these fonts. most significant data bits) DDRAM allocated designation indicating fullsize half-size character. When this full-size character selected, when half-size character selected. When full-size character selected, bytes DDRAM linked used 16-bit code (Figure 22). this case, lower byte written into smaller DDRAM address. bits this 16-bit code used character codes. 4096 character codes specified. addition, remaining four bits allocated display-attribute code designate white/black inverted display individual characters (refer Display Attribute Designation). Table shows relationship between 16-bit designated code HD66730/1 12-bit character code. 8-bit data designating half-size characters used 8-bit code (Figure 23). Specifically, bits 8-bit half-size characters become character codes, that total characters displayed (alphanumeric characters symbols displayed half-size characters). User fonts displayed using CGRAM. Special symbols included internal CGROM Level-2 Kanji displayed needed. Since display font size CGRAM dots, CGRAM fonts displayed right, left, bottom, order used display doublesize characters graphics. Note that display-attribute code (A1/A0) designation that written into DDRAM ignored when CGRAM used. this case, bits CGRAM used display-attribute-code designation. Refer CGRAM details. Table Relationship between Codes HD66730 Character Codes
first byte code: bits) second byte code: bits) CGRAM address user fonts: bits)
Character Code Arrangement HD66730 Non-kanji Level kanji Level kanji User font
Upper byte
Lower byte
HD66730/HD66731
Full-size character format
Display attribute code
Upper byte Display attribute code: A1/A0 bits)
Upper character code
Character code: bits)
Lower character code
Lower byte
Figure Full-Size Character Codes
Half-size character format
Character code
Character code: bits)
Figure Half-Size Character Codes
HD66730/HD66731
example displaying full-size half-size characters together described here. Full-size character display conforms bits). Perform code conversion bits bits) according relationship between 16-bit code HD66730/1 12-bit character code write two-byte character data DDRAM (write lower byte smaller DDRAM address). example shown Table When displaying half-size character, refer Table HD66730/1 Halfsize Font List write one-byte character data into DDRAM. example shown Table Figure shows data DDRAM when performing 2-line display Figure shows resulting liquid crystal display. Table Example Full-Size Font Conversion
Code (First/Second Byte) 45/6C (Hex) 35/7E (Hex) 45/54 (Hex) 3E/2E (Hex) 4A/3F (Hex) 3B/54 (Hex) 4B/5C (Hex) 44/2E (Hex) 24/4E (Hex) Character Code (C11 (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex)
Displayed Character
Table
Example Half-Size Font Code
Character Code C11) (Hex) (Hex) (Hex) (Hex) (Hex) (Hex)
Display Character
HD66730/HD66731
Full-size designation Half-size designation
Address 1st-line data
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
1110 1100
0000 1010
1111 1110
0000 0010
1101 0100
0000 1010
0010 1110
0000 0111
0011 1111
0000 1101
1101 0100
0000 0101
Address 2nd-line data
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
(Hex)
1101 1100
0000 1101
0010 1110
0000 1010
1011 0001
0000 1110
0000 1010
1011 0010
1011 0000
1010 1100
1100 1101
1100 0011
Figure Example DDRAM Character Code (2-Line Display Mode)
Figure Example Liquid Crystal Display
HD66730/HD66731
Display Attribute Designation
HD66730/1 allocates bits full-size 16-bit code character abbreviated character code bits display-attribute code (Figure 26). White/black inverted display, blinking display, white/black inverted blinking display designated each full-size character (Table 21). Display attribute control performed matrix unit that includes full-size character column dots right dots bottom (Figure 27). blinking cycle blinking display white/black inverted blinking display frames. Blinking display performed changing display pattern every frames. Since 8-bit code designated half-size characters cannot accommodate display attribute, they will always displayed normally. Table
Display Attribute Designation
Display State Normal display White/black inverted display Blinking display White/black inverted blinking display
Attribute code
Upper character code
Lower character code
Figure Full-Size Code Format
HD66730/HD66731
Example normal display Normal display DDRAM code
1110 1100
0000 1010
Example white/black inverted display White/black inverted display DDRAM code
1110 1100
0010 1010
Example blinking display Blink display DDRAM code Alternates display frames
1110 1100
0100 1010
Example white/black inverted blinking display White/black inverted blinking display DDRAM code Alternates display frames
1110 1100
0110 1010
Figure Setting Codes DDRAM Display Examples
HD66730/HD66731
Horizontal Smooth Scroll
Data shown display scrolled horizontally left specified number dots (Figure 28). number dots scroll control register (SCR3: R7), display lines scrolled designated display line enable bits (SE1/SE2/SE3/SE4) scroll control register (SCR2: R6). Because number dots that scrolling here scrolling more than this number achieved shifting left four characters character code data DDRAM scroll display line question, rewriting characters, then scrolling again. When rewriting DDRAM while displaying characters, however, character output will momentarily breakdown, display flicker. this case, first check which display lines currently being displayed referring NF1/0 (line line display raster-rows (raster-row raster-row status register, then rewrite DDRAM line that being displayed. Keep mind that scroll display line enable bits (SE1 SE4) used designate those display lines which horizontal smooth scroll desired. partial scroll, three leftmost characters display specified partial scroll bits (PS1/0) scroll control register (SCR: fixed remaining characters undergo smooth scroll perform partial smooth scroll. When performing horizontal smooth scroll, number characters displayed (NC1/0: must least characters more than number characters actually displayed liquid crystal display. example, more display characters (NC1/0) single-chip 6-character display.
HD66730/HD66731
Performs shift SCR3 "00" (Hex)
Shifts left SCR3 "01" (Hex)
Shifts left dots SCR3 "02" (Hex)
Shifts left dots SCR3 "0A" (Hex)
Shifts left dots SCR3 "30" (Hex)
Figure Example Horizontal Smooth Scroll Display
HD66730/HD66731
Examples Register Setting
Index register designation) Enables scroll (scrolls only second line) Index register designation) Shifts second line left
Wait Shifts second line left dots
Wait Shifts second line left three dots
Wait
Shifts second line left dots*
Note: number dots that specified scrolling Scrolling more than this number achieved rewriting DDRAM data scrolling again from Note that number characters shown number scroll characters must less than number maximum display characters (1-line display mode: characters, 2-line display mode: characters, 4-line display mode: characters).
Figure Example Executing Smooth Scroll Left
HD66730/HD66731
Index register designation) Enables scroll (scrolls only second line) Index register designation) Shifts second line left dots*
Wait Shifts second line left dots
Wait
Shifts second line left
Wait Perform shift
Note: number dots that specified scrolling Rewrite dots characters) data inside DDRAM shift them right before scrolling. Scrolling more than this number achieved rewriting data DDRAM begin scrolling from again. Note that number characters shown number scroll characters must less than number maximum display characters (1-line display mode: characters, 2-line display mode: characters, 4-line display mode: characters).
Figure Example Executing Smooth Scroll Right
HD66730/HD66731
Partial Smooth Scroll
Partial smooth scroll displays three leftmost characters fixed while remaining ones undergo horizontal smooth scroll left right direction. Specifically, number leftmost characters fixed specified partial scroll bits (PS1/0) scroll control register (SCR2: R6). example, when bits PS1/0 leftmost characters fixed; when three leftmost characters fixed. Although half-size characters displayed fixed display area, they must displayed evennumbered groups two, four characters. Figure shows example smooth scroll performed display when bits PS1/0 leftmost characters displayed fixed, remaining four characters undergo smooth scroll.
Perform shift PS1/0 "10" SCR3 "00" (Hex)
Shifts left PS1/0 "10" SCR3 "01" (Hex)
Shifts left dots PS1/0 "10" SCR3 "02" (Hex)
Shifts left three dots PS1/0 "10" SCR3 "03" (Hex)
Shifts left dots PS1/0 "10" SCR3 "0A" (Hex)
Shifts left dots PS1/0 "10" SCR3 "20" (Hex)
Figure Example Partial Smooth Scroll Display
HD66730/HD66731
Vertical Smooth Scroll
Vertical smooth scroll down performed setting number display lines (NL1/0: value greater than actual number liquid crystal display lines, which duty drive ratio (DT1/0: 1/14 (1-line display), 1/27 (2-line display), 1/40 (3-line display), 1/53 (4-line display). display line setting (NL1/0: R4), which controls display, select 1-line display mode, 2-line display mode, 4-line display mode. example, perform normal vertical smooth scroll 3-line liquid crystal display with duty ratio 1/40, number display lines (NL1/0: lines. Note that vertical smooth scroll performed when number actual liquid display lines same number display lines, display line that scrolled display will appear again from bottom top) (this function called lap-around). 4-line crystal liquid display, only lap-around function performed. Vertical smooth scroll controlled incrementing decrementing display line (SN1/0), which indicates which line start from, display raster-row (SL0 SL3). example, when performing smooth scroll display raster-row (SL0 SL3) incremented from 0000 1100 order scroll raster-rows. Moreover, incrementing display line (SN1/0) then incrementing display raster-row from 0000 1100 again, total raster-rows scrolled. Since DDRAM only bytes, data must rewritten when performing continuous scroll exceeding this capacity.
HD66730/HD66731
Performs scroll SN1/0 "00" "0000"
1-line scroll SN1/0 "00" "0001"
2-line scroll SN1/0 "00" "0010"
7-line scroll SN1/0 "00" "0111"
12-line scroll SN1/0 "00" "1100"
Figure Example Vertical Smooth Scroll Display
HD66730/HD66731
Examples Register Setting (2-Line Liquid Crystal Drive: DT1/0 4-Line Display Mode: NL1/0
Index register designation) Scrolls raster-row (Begins display from second raster-row first line) Scrolls raster-rows (Begins display from third raster-row first line) Scrolls three raster-rows (Begins display from fourth raster-row first line)
Wait
Wait
Wait Scrolls raster-rows (Begins display from 13th raster-row first line) Scrolls raster-rows (Begins display from first raster-row second line displays second third lines) Scrolls raster-rows (Begins display from 13th raster-row second line) Scrolls raster-rows (Begins display from first raster-row third line displays third fourth lines)
Wait
Wait
Wait
Wait
Note: DDRAM bytes. 4-line display mode, 4-line 10-character/line display therefore performed. Although line raster-row scrolling designated desired, first raster-row first line will displayed after displaying raster-row line
Figure Example Performing Smooth Scroll
HD66730/HD66731
Index register designation) Scrolls raster-row down (Begins display from 13th raster-row fourth line) Scrolls raster-rows down (Begins display from 12th raster-row fourth line) Scrolls three raster-rows down (Begins display from 11th raster-row fourth line)
Wait
Wait
Wait Scrolls raster-rows down (Begins display from first raster-row fourth line) Scrolls raster-rows down (Begins display from third raster-row 13th line) Scrolls raster-rows down (Begins display from third raster-row first line)
Wait
Wait
Note: DDRAM bytes. 4-line display mode, 4-line 10-character/line display therefore performed. Although line raster-row scrolling designated desired, first raster-row first line will displayed after displaying raster-row line
Figure Example Performing Smooth Scroll Down
HD66730/HD66731
Extension Driver Interface (HD66730)
HD66730 interface with extension drivers using extension driver interface signals CL1, CL2, output from HD66730, increasing number display characters (Figure 35). Although liquid crystal driver voltage that drives booster HD66730 also used driver power supply extension drivers, output voltage drop booster increases load booster increases.
Single-chip operation Using extension driver
HD66730
SEG1 SEG71
COM1 COM25
2-line/6-character display
HD66730
SEG1 SEG71
COM1 COM25
2-line/12-character display
SEG1 SEG72
HD66002
Figure HD66730 Extension Driver Connection
HD66730/HD66731
Interfacing with Liquid Crystal Panel
connecting HD66730 extension drivers, display expanded 1-line/40-character, 2-line/20-character, 4-line/10-character display configuration. Bits DT1/0 duty drive ratio bits NC1/0 number characters line. addition, bits NL1/0 sets number display lines during display read control. Table shows relationship between number characters actually displayed liquid crystal panel corresponding number extension drivers needed. Table Relationship between Number Liquid Crystal Display Characters Extension Drivers
Number Display Characters Line Display Lines line lines lines lines Duty Characters Characters Characters Characters Characters Characters Drive (0/0) (0/0) (0/1) (0/1) (2/0) (2/0) (2/1) (2/1) (2/0) (2/0) Display disabled Display disabled (3/0) (3/0) Display disabled Display disabled (5/0) (5/0) Display disabled Display disabled (11/0) Display disabled Display disabled Display disabled 1/14 1/27 1/40 1/53
Notes: Numbers parentheses (number extension segment drivers/number common drivers) This example when using output extension drivers, when represents display characters extension driver outputs, number extension drivers needed generally calculated follows: [Number extension drivers] 1)/Nd] right-edge segment (space between characters) displayed 6-character 16character display. Horizontal smooth scroll cannot performed during 1-line/40-character, 2-line/20-character, 3-line/10-character, 4-line/10-character display.
HD66730/HD66731
Example Interfacing with 1-Line Display Panel
HD66730
COM1 COM2
COM12 COMS SEG1 SEG2
SEG12 SEG71 Note: rightmost dot-column space character cannot displayd.
Figure Example 1-Line/6-Character 71-Segment Display (Using 1/14 Duty)
HD66730
COM1 COM2
COM12 COMS SEG1 SEG2
SEG12 SEG71 COM14 COM15
COM25 Note: above figure shows liquid crystal panel arranged into 1-line/12-character display while operating HD66730 2-line/6-character display mode. Although duty ratio becomes high, extension drivers will needed. COM13 spaces between display lines will needed.
Figure Example 1-Line/12-Character 71-Segment Display (Using 1/27 Duty)
HD66730/HD66731
Example Interfacing with 2-Line Display Panel
HD66730
COM1 COM2
COM12 COM13 COM14
COM25 COMS SEG1 SEG2
SEG12
SEG71 Note: When performing vertical smooth scroll, displaying double-size characters graphic figures CGRAM, COM13 used spaces between lines. Display performed continuously vertically.
Figure Example 2-Line/6-Character 71-Segment Display (Using 1/27 Duty)
HD66730/HD66731
COMS COM1 COM2
COM19
HD66731
SEG1 SEG2
SEG12 SEG72 COM20
COM39 COM40
Note: COMS COM40 output same.
Figure Example 3-Line/6-Character 72-Segment Display (Using 1/40 Duty)
Input waveform timechart
(Shift clock)
DB4~DB7 DB0~DB3 OSC1
seg.240 seg.239 seg.238 seg.237
seg.3
seg.2
seg.1
OSC2
(Latch clock)
HD66730
com1 com2 com3
com24 com25
seg1 seg2 seg3
(+3V) HD66002 Y80, Y79,.Y2,
Open
HD66002
Open
seg226 seg227 seg228
(0V)
COM1 ~COM25 DB4~DB7 COMS DB0~DB3 SEG1 ~SEG71
19-character 2line panel (228 segments) 1/27 Duty
Interfacing between HD66730 HD66002
Open
Y80, Y79,.Y2,
D2R, TEST1 TEST2
Figure Example Display Extension Curcuit
(-7V)
HD66730/HD66731
Notes: resistance depends type panel used (Usually stabilize power supply, place 0.1-µF capacitors near each driver: between pins, other between VEE.
D2R, TEST1 TEST2
HD66730/HD66731
Oscillator
Figure shows optimal value oscillation frequency external clock frequency depends duty drive ratio setting (DT1/0), number display lines (NL1/0), number display characters (NC1/0) HD66730/1. oscillation frequency external clock frequency must adjusted according frame frequency liquid crystal drive.
When external clock used When internal oscillator used
Clock
OSC1
OSC1 OSC2 HD66730 HD66731
HD66730 HD66731
Note: oscillator frequency adjusted oscillator resistor (Rf). Refer Electrical Characteristics relationship between oscillator resistor (Rf) oscillator frequency. increased power supply voltage decreased, oscillator frequency decreases.
Figure Oscillator Connections
HD66730/HD66731
Relationship between Oscillation Frequency Liquid Crystal Display Frame Frequency Figures Tables show oscillation frequency external clock frequency various registor settings when frame frequency
1-line selection period COM1 frame (Number dots screen) frame (Number dots screen)
Figure Frame Frequency (1/14 Duty Cycle)
HD66730/HD66731
Table 1/14 Duty Drive
1-Line Display (00) characters (00) dots 1008 dots characters (01) dots 3360 dots characters (11) dots 6720 dots
Number Display Lines: (NL1/0 Value): Number display characters (NC1/0 value) 1-line selection period (dot) Number dots screen (dot) Oscillation frequency (kHz)*
Number Display Lines: (NL1/0 Value): Number display characters (NC1/0 value) 1-line selection period (dot) Number dots screen (dot) Oscillation frequency (kHz)* characters (00) dots 1008 dots
2-line Display (01) characters (01) dots 1680 dots characters (11) dots 3360 dots
Number Display Lines: (NL1/0 Value): Number display characters (NC1/0 value) 1-line selection period (dot) Number dots screen (dot) Oscillation frequency (kHz)* Note: characters (00) dots 1008 dots
4-Line Display (11) characters (01) dots 1680 dots
frequencies Table examples when frame frequency Adjust oscillation frequency that optimum frame frequency obtained.
HD66730/HD66731
1/27 Duty Cycle (DT1/0 2-Line Drive)
1-line selection period COM1 frame (Number dots screen) frame (Number dots screen)
Figure Frame Frequency (1/27 Duty Cycle) Table 1/27 Duty Drive
2-Line Display (01) characters (00) dots 1944 dots characters (01) dots 3240 dots characters (11) dots 6480 dots
Number Display Lines: (NL1/0 Value): Number display characters (NC1/0 value) 1-line selection period (dot) Number dots screen (dot) Oscillation frequency (kHz)*
Number Display Lines: (NL1/0 Value): Number display characters (NC1/0 value) 1-line selection period (dot) Number dots screen (dot) Oscillation frequency (kHz)* Note: characters (00) dots 1944 dots
4-Line Display (11) characters (01) dots 3240 dots
frequencies Table examples when frame frequency Adjust oscillation frequency that optimum frame frequency obtained.
HD66730/HD66731
1/40 Duty Cycle (DT1/0 3-Line Drive)
1-line selection period COM1 frame (Number dots screen) frame (Number dots screen)
Figure Frame Frequency (1/40 Duty Cycle) Table 1/40 Duty Drive
4-Line Display (11) characters (00) dots 2880 dots characters (01) dots 4800 dots
Number Display Lines: (NL1/0 value): Number display characters (NC1/0 value) 1-line selection period (dot) Number dots screen (dot) Oscillation frequency (kHz)* Note:
frequencies Table examples when frame frequency Adjust oscillation frequency that optimum frame frequency obtained.
HD66730/HD66731
1/53 Duty Cycle (DT1/0 4-Line Drive)
1-line selection period COM1 frame (Number dots screen) frame (Number dots screen)
Figure Frame Frequency (1/53 Duty Cycle) Table 1/53 Duty Drive
4-line Display (11) (00) characters (00) dots 3816 dots (01) characters (01) dots 6360 dots
Number Display Lines: (NL1/0 Setting Value): Number display characters (NC1/0 setting value) 1-line selection period (dot) Number dots screen (dot) Oscillation frequency (kHz)* Note:
frequencies Table examples when frame frequency Adjust oscillation frequency that optimum frame frequency obtained.
HD66730/HD66731
Power Supply Liquid Crystal Display Drive
HD66730/1 incorporates booster raising voltage three times that reference voltage input below (Figure 48). three times boosted voltage obtained externally attaching three 1-µF capacitors. panel large needs large amount drive current, values bleeder resistors that generate potential made smaller. However, load current booster voltage drop increases this case. recommend setting resistance value each bleeder larger than hold down load current using booster circuit. external power supply should supply voltage load current exceeds (Figure 49). Refer Electrical Characteristics showing relationship between load current booster voltage output. Table shows duty factor bleeder resistor value power supply liquid crystal display drive. Table Duty Factor Bleeder Resistor Value Power Supply Liquid Crystal Display Drive
Data 1/14 1/4.7 Note: R*0.7 1/27 1/6.2 R*2.2 1/40 1/7.3 R*3.3 1/53 1/8.3 R*4.3
Item Drive lines (DT1/0 setting value) Duty factor Bias Bleeder resistance value
changes depending size liquid crystal panel. Normally, must Adjust optimum value with consumption current display picture quality.
Figure Example Power Supply Liquid Crystal Display Drive (with External Power Supply)
HD66730/HD66731
(Double boosting)
(Triple boosting)
Thermistor
V5OUT2 V5OUT3
Thermistor
V5OUT2 V5OUT3
Notes: reference voltage input (Vci) must below power supply (VCC). Current that flows into reference voltage input (Vci) times larger than load current flowing through bleeder resistors. Note that reference voltage drop occurs current flowing into input when reference voltage (Vci) generated resistor division. amount output voltage (V5OUT2/V5OUT3) drop booster circuit also increases load current flowing through bleeder resistors increases. Thus, bleeder resistance large possible (4.7 greater) without affecting display picture quality. Adjust reference voltage input (Vci) according fluctuation booster characteristics because output voltage (V5OUT2/V5OUT3) drop depends load current, operation temperature, operation frequency, capacitance external capacitors, manufacturing tolerance. Refer Electrical Characteristics details. Adjust reference voltage input (Vci) that output voltage (V5OUT2/V5OUT3) after boosting will exceed absolute maximum rating liquid crystal power supply voltage (15V). Make sure that connect polarized capacitors correctly.
Figure Example Power Supply Liquid Crystal Display Drive (with Internal Booster)
HD66730/HD66731
V5OUT2 V5OUT3 V5OUT2 V5OUT3
4.7k
0.1µF 0.5µF Example power supply
Example normal power supply
Figure Example Power Supply Power Consumption
V5OUT2
V5OUT2 V5OUT3
V5OUT2 V5OUT3
V5OUT3
Figure Example Temperature Compensation Circuit
HD66730/HD66731
Absolute Maximum Ratings (HD66730)*
Item Power supply voltage Power supply voltage Input voltage Operating temperature Storage temperature Note: Symbol VCC-V5 Topr Tstg Value -0.3 +7.0 -0.3 +17.0 -0.3 +125 Unit Notes
used above these absolute maximum ratings, become permanently damaged. Using within following electrical characteristic limits strongly recommended normal operation. these electrical characteristic conditions also exceeded, will malfunction cause poor reliability.
Absolute Maximum Ratings (HD66731)*
Item Power supply voltage Power supply voltage Input voltage Operating temperature Storage temperature Note: Symbol VCC-V5 Topr Tstg Value -0.3 +7.0 -0.3 +17.0 -0.3 +110 Unit Notes
used above these absolute maximum ratings, become permanently damaged. Using within following electrical characteristic limits strongly recommended normal operation. these electrical characteristic conditions also exceeded, will malfunction cause poor reliability.
HD66730/HD66731
Characteristics (VCC +75°C*3)
Item Input high voltage (except OSC1) Input voltage (except OSC1) Input high voltage (OSC1) Input voltage (OSC1) Output high voltage (D0-D7) Output voltage (D0-D7) Output high voltage (except D0-D7) Output voltage (except D0-D7) Driver resistance (COM) Driver resistance (SEG) leakage current Pull-up current (RESET* pin) Power supply current Symbol VIH1 VIL1 0.7V -0.3 -0.3 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 RCOM RSEG 0.7V 0.75V 0.8V 0.2V 0.2V 0.2V 0.2V Unit 0.04 0.04 0.05 VLCD 0.05 VLCD oscillation, external clock Sleep mode VCC-V5 3.0V 4.5V Test Condition Notes
voltage
VLCD
15.0
HD66730/HD66731
Booster Characteristics
Item Output voltage (V5OUT2 pin) Symbol VUP2 Unit Test Condition 4.5V, 0.25 kHz, 25°C 2.7V, 0.25 kHz, 25°C Notes*
Output voltage (V5OUT3 pin)
VUP3
Input voltage
Characteristics (VCC 2.4V 5.5V, +75°C*3)
Clock Characteristics +75°C*3)
Item External clock operation External clock frequency Symbol External clock duty External clock rise time External clock fall time oscillation Clock oscillation frequency (HD66730) Clock oscillation frequency (HD66731) Duty Unit Test Condition Notes*
2.7V 5.5V
HD66730/HD66731
System Interface Timing Characteristics (VCC 2.4V 4.5V, +75°C*3)
Write Operation
Item Enable cycle time Enable pulse width (high level) Enable rise/fall time Address hold time Data set-up time Data hold time Symbol CYCE PWEH Address set-up time (RS, Unit Test Condition Figure 3.0V 4.5V Figure
Read Operation
Item Enable cycle time Enable pulse width (high level) Enable rise/fall time Address hold time Data delay time Data hold time Symbol CYCE PWEH 1000 Unit Test Condition Figure
Address set-up time (RS,
Serial Interface Operation
Item Serial clock cycle time Serial clock (high level width) Serial clock (low level width) Serial clock rise/fall time Chip select set-up time Chip select hold time Serial input data set-up time Serial input data hold time Serial output data delay time Serial output data hold time Symbol SCYC SISU Unit Test Condition Figure
HD66730/HD66731
System Interface Timing Characteristics (VCC 4.5V 5.5V, +75°C*3)
Write Operation
Item Enable cycle time Enable pulse width (high level) Enable rise/fall time Address hold time Data set-up time Data hold time Symbol CYCE PWEH Unit Test Condition Figure
Address set-up time (RS,
Read Operation
Item Enable cycle time Enable pulse width (high level) Enable rise/fall time Address hold time Data delay time Data hold time Symbol CYCE PWEH Unit Test Condition Figure
Address set-up time (RS,
Serial Interface Sequence
Item Serial clock cycle time Serial clock (high level width) Serial clock (low level width) Serial clock rise/fall time Chip select set-up time Chip select hold time Serial input data set-up time Serial input data hold time Serial output data delay time Serial output data hold time Symbol SCYC SISU Unit Test Condition Figure
HD66730/HD66731
HD66730 Segment Extension Signal Timing Characteristics (VCC 2.4V 5.5V, +75°C*3)
Item Clock pulse width High level level Clock set-up time Data set-up time Data hold time delay time COMD set-up time Clock rise/fall time COMD Symbol -1000 1000 Unit Test Condition Figure
Pins except COMD
Reset Timing Characteristics (VCC 2.4V 5.5V, +75°C*3)
Item Reset low-level width Symbol Unit Test Condition Figure
HD66730/HD66731
Electrical Characteristics Notes
voltage values referred used above absolute maximum ratings, become permanently damaged. Using within electrical characteristic strongly recommended ensure normal operation. these electrical characteristic exceeded, malfunction exhibit poor reliability. must maintained. When COM25/COMD used extention driver interface signal (COMD), must maintained. products, specified 75°C. products, specified shipment specification. following four circuits configurations except liquid crystal display output.
Input Pin: E/SCLK, RS/CS*, RW/SID, PMOS Input Pins: RESET* PMOS PMOS Output Pins: CL1, CL2, SEGD (HD66730) TESTD (HD66731) PMOS
(Pull-up MOS) NMOS NMOS NMOS
Pins: DB0/SOD (Pull-up MOS) PMOS (Input circuit) PMOS Input enable
NMOS NMOS PMOS
Output enable Data
NMOS (Output circuit: tristate)
Applies input pins pins, excluding OSC1 pin. Applies pins. Applies output pins HD66730. Current flowing through pull-up MOSs, excluding output drive MOSs.
HD66730/HD66731
Input/output current excluded. When input intermediate level with CMOS, excessive current flows through input circuit power supply. avoid this from happening, input level must fixed high low. Applies only external clock operation.
Oscillator OSC1
Open
OSC2
Duty 100%
Applies only internal oscillator operation using oscillation resistor
Recommended registor value OSC1 OSC2 150k±2% (When 180k±2% (When Since oscillation frequency varies depending OSC1 OSC2 terminal capacitance,wiring length these pins should minimized.
fOSC (kHz)
(typ.) (typ.)
HD66730/HD66731
RCOM resistance between power supply pins each common signal (COM0 COM25/COM53). RSEG resistance between power supply pins (VCC, each segment signal (SEG1 SEG71/SEG119). following graphs show relationship between operation frequency current consumption (referential data).
(mA) typ.(Sleep mode) (mA) typ.(Normal display) typ.(Sleep mode) typ.(Normal display)
fOSC (kHz)
fOSC (kHz)
Applies OSC1 pin. Each output voltage within ±0.15V voltage when there load. TEST must fixed ground, must also connected ground. Booster characteristics test circuits shown below.
(Double boosting) (Triple boosting)
V5OUT2
Rload
V5OUT2
Rload
V5OUT3
V5OUT3
HD66730/HD66731
VUP2=VCC -V5OUT2
VUP2,VUP3 Boosting twice typ. Boosting three times
VUP3=VCC -V5OUT3
VUP2(V)
VUP3(V)
typ.
Test condition Vci=VCC, fcp=140kHz, Ta=25°C
Test condition Vci=VCC, fcp=140kHz, Ta=25°
(ii) VUP2, VUP3 Boosting twice
Boosting three times typ.
VUP2(V)
VUP3(V)
typ.
(°C)
Test condition Vci=VCC=4.5V, Rf=180k IO=0.1mA
(°C)
Test condition Vci=VCC=2.7V, Rf=150k IO=0.1mA
(iii) VUP2, VUP3 Capacitance Boosting twice typ. Boosting three times typ.
VUP2(V)
(µF)
VUP3(V)
(µF)
Test condition Vci=VCC=4.5V,Rf=180k IO=0.1mA
Test condition Vci=VCC=2.7V, Rf=150k IO=0.1mA
(iv) VUP2, VUP3 Boosting twice (mA) typ. Boosting three times
VUP2(V)
VUP3(V)
typ.
(mA)
Test condition Vci=VCC=4.5V,Rf=180k Ta=25°C
Test condition Vci=VCC=2.7V, Rf=150k Ta=25°C
must maintained.
HD66730/HD66731
Load Circuits
Characteristics Test Load Circuits
Data bus: DB7,
Segment extension signals: CL1, CL2, SEGD, COMD Test point
Test point
HD66730/HD66731
Timing Characteristics
VIH1 VIL1 VIH1 VIL1
VIL1 PWEH
VIL1
VIH1 VIL1
VIH1 VIL1
VIL1
VIH1 VIL1
Valid data tCYCE
VIH1 VIL1
Figure Write Operation
VIH1 VIL1
VIH1 VIL1
VIH1 PWEH
VIH1
VIL1
VIH1
VIH1
VIL1
VIL1
VOH1 VOL1
Valid data tCYCE
VOH1 VOL1
Figure Read Operation
HD66730/HD66731
tSCYC VIL1 tCSU tSCr tSCH tSCf tSCL VIL1
SCLK
VIH1 VIL1
VIL1 tSISU VIH1 VIL1 tSOD
VIH1 VIL1 tSIH VIH1 VIL1
VIL1
VIH1
tSOH VOH1 VOL1 VOH1 VOL1
Figure Serial Interface Timing
VOH2 VOH2 VOH2
VOH2 VOL2
VOL2
VOL2
SEGD VOH2 COMD VOL2
Figure Interface Timing with Extension Driver
HD66730/HD66731
tRES RESET*
VIL1
VIL1
Figure Reset Timing
2.7V/4.5V*2 0.2V trcc trcc 0.2V tOFF*1 tOFF 0.2V
Notes: tOFF compensates power oscillation period caused momentary power supply oscillations. Specified 4.5V 5-volt operation, 2.7V 3-volt operation.
Figure Power Supply Sequence

(Dot-Matrix Liquid Crystal Display Controller/Driver Supporting Japane

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