Harris Multimedia Author: Steven Martin HMP8154EVAL1 Encoder
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AN9743
Harris Multimedia
Author: Steven Martin
HMP8154EVAL1 Encoder Evaluation Platform
Features
HMP8154 Video Encoder Digital Parallel ITU-R BT.656 Input Pin, Dual Receptacle Analog Output Formats Composite Composite (SCART) NTSC Operation ITU-R BT.601 Square Pixel Operation board includes encoder, voltage references decoupling, analog output filters, connectors. board's primary input receptacle. used wiring board into existing system. connector provides access encoder's digital signals. board outputs analog video four coax connectors. board output composite video signal either S-Video second composite signal, component video. board also accepts digital parallel BT.656 data stream. Translators convert input levels drive encoder. encoder converts data embedded timing information into analog video. non-default operation, encoder must programmed bus. Application software drive parallel port provided with evaluation kit.
Description
HMP8154EVAL1 encoder evaluation platform small (index card size) printed circuit board designed demonstrate capabilities performance HMP8156 HMP8154 HMP8170-73 NTSC/PAL encoders.
Board Block Diagram
HMP8154 ENCODER DATA BT.656 CONNECTOR
SWITCH
ANALOG OUTPUTS
RECONSTRUCTION FILTERS
MAIN RECEPTACLE
SYNCS HOST COMPENSATION REFERENCE VOLTAGE
ANALOG COMP/REF
I/O, PARALLEL PORT
CLOCKS
POWER GROUND CONNECTIONS SHOWN
Copyright
Harris Corporation 1997
Application Note 9743 Operating Modes
HMP8154EVAL1 board main operating modes. installed mother board daughter card connected with other system components stand-alone board. Stand-Alone BT.656 Operation stand-alone mode, HMP8154EVAL1 connected external power supplies, BT.656 signal generator, parallel port, monitor measurement equipment. interconnections shown Figure
-5.2V DUAL POWER SUPPLY 5.0V, 300mA 5.2V, 150mA
+5V,
-5V, GND, GND,
FIGURE POWER SUPPLY CONNECTIONS
Daughter Card Operation
BT.656 VIDEO TEST PATTERN GENERATOR
HMP8154 EVAL1 BOARD
MONITOR AND/OR VM700
HMP8154EVAL1 board pin, receptacle which allows connection into existing system. main connector provides access encoder's digital inputs outputs. daughter card uses output connectors stand-alone mode. When installed mother board, daughter card's BT.656 interface must disabled. switch opened installing jumper shunt board location JP6. switch also opened asserting disable signal main connector HMP8156EVAL2 Harris designed mother board HMP8154EVAL1. mother board standard size card with interface application software. HMP8156EVAL2 complete system which allows demonstrating encoder's operating modes. analog video inputs composite, S-video, component signals. analog signals converted/decoded digital domain input daughter card. board also provides megabyte video image capture display BT.656 connector interface.
(PARALLEL PORT)
FIGURE STAND-ALONE INTERCONNECTIONS
test pattern generator that generates digital parallel YCbCr video ITU-R BT.656 (formerly CCIR-656) standard. BT.656 interface uses differential signals with logic levels. includes bits data 27.0MHz clock. best results, linear power supply with isolated dual outputs. power required 5.0V 300mA -5.2V ±10% 150mA. board grounds tied together power supplies' should power supply connections shown Figure connections should made with 20-24 twisted pair wires. stand-alone BT.656 mode, encoder must programmed non-default operation. board includes header which provides access encoder's host interface bus. header designed interface with standard parallel port. then used program encoder interface. Application software included with evaluation used program encoder. described Application Software section below. high quality monitor used observe encoder's performance. encoder supports NTSC displays that have composite, S-Video, component inputs. oscilloscope video measurement equipment also useful. cases, board's outputs should terminated with load.
Application Software
stand-alone BT.656 mode, encoder must programmed non-default operation. board includes header which provides access encoder's host interface bus. header designed interface with standard parallel port. Application software provided control parallel port. board must connected printer port clock source order application software operate correctly. pixel clock driven from main connector (P1), BT.656 connector (J1), clock connector, (J2). Without active clock, encoder will respond commands. evaluation includes software applications program encoder observe internal registers. program with simple command line interface which will other windows program which will only using Win95TM.
Windowsis copyright Microsoft Corporation.
Application Note 9743
TABLE EXAMPLE DCIIC COMMANDS FUNCTION Reset DCIIC USAGE EXAMPLE COMMAND OUTPUT
dciic
c:\hmp8154> dciic c:\hmp8154> c:\hmp8154> dciic bt656.cfg dciic: bt656.cfg loaded. c:\hmp8154> c:\hmp8154> dciic dciic: read: 0x40,0X00 0x54 c:\hmp8154> c:\hmp8154> dciic 0x1c dciic: wrote: 0x40,0X02 0x1c c:\hmp8154> c:\hmp8154> dciic usage: dciic [options] [file.cfg reads writes registers. options: [-r] chip reset <port_adrs>] printer port base address <slv_adrs>] device slave address <regAdrs> [<data>]] c:\hmp8154>
Load Configuration
dciic filename
Read Register
dciic sub-address
Write Register
dciic sub-address value
Help
dciic
DCIIC Application Program DCIIC (Daughter card I2C) simple program written program allows user Assert encoder's RESET signal initialize part default operating state, Load encoder's programmable registers from configuration file, Read and/or write encoder's programmable registers individually. default, program writes parallel port located space address 0x378. board connected port which located default address, then option must included with other command line arguments. Other common locations parallel port addresses 0x3bc 0x278. When dciic starts, searches encoder reading product register register sub-address slave addresses 0x40 0x42. encoder does respond, program prints error message exits. slave address from command line using option. from command line, program does read product register. dciic configuration files ASCII files which edited with text editor. They have same format those used HMP8156EVAL2 MMVideoEval software application. However, dciic only supports subset commands namely SetReg command. other commands silently ignored. dciic SetReg command consists case-sensitive keywords "SetReg CHMP8154" followed register subaddress value. numeric values follow usual conventions decimal, octal, hexadecimal bases. example command below: SetReg CHMP8154 0x28 different encoder used board, then part number should substituted second keyword, i.e. "CHMP8156" instead "CHMP8154" Although written standard ANSI dciic program written compilation using Microsoft Visual C++, version 1.52. source code included with evaluation kit. MMEncEval Win95 Application Program MMEncEval application program Win95 complete this time. When complete, interface will very similar MMVideoEval application program used with HMP8156EVAL2 frame grabber evaluation platform.
Application Note 9743 Physical Interfaces
STAND-ALONE POWER SUPPLY CONNECTIONS ENCODER SLAVE ADDRESS SELECT JUMPER ANALOG OUTPUTS JACKS
INTERFACE HEADER
BT.656 INPUT FEMALE D-SUB
BT.656 TRANSLATORS
RSET BT.656 INPUT SWITCH REFERENCE VOLTAGE SELECT JUMPER MAIN CONNECTOR RECEPTACLE BOTTOM)
CLOCK JACK RECONSTRUCTION FILTERS
Interface Connectors HMP8154EVAL1 board's interface connectors listed Table table, column titled "Board Part Number" lists manufacturer part number connector component installed board. some boards, equivalent components substituted. "Mating Part Number" column lists typical connector which will interconnect correctly with component installed board. connectors have standard numbers. numbers locations shown Figure signals each listed Tables
Application Note 9743
TABLE INTERFACE CONNECTOR DEFINITION INTERFACE NAME Main, I2C, CONNECTOR STYLE pin, Dual pin, Single BOARD PART NUMBER Receptacle 2-635585-1 Header, Molex 22-23-2051 MATING PART NUMBER Header 2-102973-5 Receptacle housing, Molex 22-01-3057; Contacts, Molex 08-55-0102 Pins, 747912-2 Plug, Johnson Components 142-0403-011 Plug, Amphenol 68175 COMMENTS Industry standard receptacle header using 0.025 inch square posts with spacing. Header receptacle keyed include locking ramp. Some Molex documentation defines opposite ends header housing.
BT656, CLK,
pin, D-Subminiature Coaxial
Sockets, 745967-7 Jack, Johnson Components 142-0701-211 Jack, Amphenol 31-5329
Connectors pinout defined ITU-R BT.656 standard. clock interface bidirectional. connector must driven when BT656 interface active when Main connector clock driven. Terminate each analog output with load from center conductor cable shield best results.
Analog Outputs, J3-J6 Power, J7-J10
Coaxial
Plated thru-holes
Stranded Wire,
When powered main connector, board wired external power supplies.
TOP, COMPONENT SIDE
BOTTOM, SOLDER SIDE
VIEW, LOOKING THROUGH BOARD
CONNECTOR, POSITION HEADER MAIN CONNECTOR, POSITION RECEPTACLE, 0.100 INCH SPACING, 2-535585-1 0.100 INCH SPACING, MOLEX 22-23-2051
SCALE
FIGURE MAIN CONNECTOR LOCATIONS.
Application Note 9743
TABLE MAIN CONNECTOR PINOUT SIGNAL PIX<23> PIX<22> PIX<21> PIX<20> PIX<19> PIX<18> PIX<17> PIX<16> -BT656_ENA (VCC) PIX<15> PIX<14> PIX<13> SIGNAL PIX<12> PIX<11> PIX<10> PIX<9> PIX<8> -VSYNC_ENC -HSYNC_ENC PIX<7> PIX<6> PIX<5> PIX<4> PIX<3> PIX<2> SIGNAL PIX<1> PIX<0> -BLANK_ENC FIELD_ENC SCLK SDATA -RESET_A PIXCLK VIDCLK
TABLE CONNECTOR PINOUT (NOTE BOARD HEADER NUMBER (NOTE RECEPTACLE HOUSING NUMBER (NOTE PARALLEL PORT NUMBER
NAME Reset
COMMENTS reset signal active low. should asserted least four cycles following board powerup. serial data signal (and encoder's SDATA pin) driven when output enable signal asserted. Otherwise, pulled high board resistor. Signal return path. encoder, serial data bidirectional; only input. encoder SCLK signal. encoder pixel clock signal must also toggle interface operate.
Output Enable
Ground Serial Data
Serial Clock
NOTES: Different versions Molex documentation board header shows either connector. documentation receptacle housing shows opposite chosen header. Therefore, pins reversed that when connected, header aligns with housing. standard parallel port uses D-subminiature connector with sockets. cable connector which will interconnect with part 747912-2 from AMP.
Application Note 9743
Moveable Jumpers board uses several movable jumpers control operation connectivity. jumpers functions they control described Table
TABLE JUMPER FUNCTIONS FUNCTION NAME Clock Slave Address JP3, Ground External Reference BT.656 NOTES: Jumper hardwired should changed. Default position shunted. relation between reference voltage output current described encoder's data sheet. Default position open. BT.656 driver enable signal also connected main connector resistor ground. Encoder responds slave address 0x40. Encoder uses internal reference voltage. OPEN SHUNTED connected CLK2 Encoder responds slave address 0x42. Digital analog grounds connected. Encoder reference voltage driven board's reference circuit. NOTES
Schematics Layout
board schematics shown Figures 5-11. Notes schematics indicate assembly options. parts list follows HMP8154EVAL1 Evaluation Board Parts List. board consists four layers laid optimize performance encoder. bottom layers signal trace layers. inner layers used power ground planes. work board shown Figures 12-16. power plane split into three sections VEE, VCC, VAA. powered main connector external supplies. connected single ferrite bead. Each section power plane includes bulk area capacitors ground decoupling. ground plane split into sections digital analog grounds. Although isolated their planes, ground areas electrically distinct. ground planes connected solid wire point. Harris customers part schematics layout. Electronic versions also available.
BT.656 clock BT.656 clock data drivers data drivers disenabled. abled.
Adjustable Components board uses single potentiometer, RSET value thus encoder's full scale output current. resistor should adjusted that output voltage measured load 1.0VPP from sync white level. resistor factory correct video levels when driving board reconstruction filter external terminator. adjustable resistor needed when filter load fixed. adjustment provided board only allow flexibility support different, changeable, loads. shown encoder's data sheet, variability output levels small. They remain within video tolerances when using fixed tolerance resistor.
COMPENSATION CAPS
3D1> VAA3
0.1µ 10%, CR1206
0.1µ 10%, CR1206
5D6> 5D2> PIX<23.0> RSET: DETERMINES DAC's FULLSCALE OUTPUT CURRENT PIX23 PIX22 PIX21 PIX20/M1 PIX19/M0 PIX18/OL2 PIX17/OL1 PIX16/OL0 MQFP 0.5W, 10%, 0.1W CR1206
EXTERNAL VOLTAGE REFERENCE
3D1> VAA3
Application Note 9743
HMP8154EVAL1 Evaluation Board Schematic Diagrams
3C1> AGND3
FIGURE ENCODER
VREF 5A6> 5A6> -RESET SCLK SDATA SADRS 5A6> SDATA SADRS 5A6> (REF) CLK2 (PIX) HMP8154 SCLK RESERVED RESET FIELD VSYNC HSYNC BLANK VREF PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 Y_ENC 2D8< C_ENC 2C8< NP1_ENC 2B8< NP2_ENC 2A8<
PIX15 PIX14 PIX13 PIX12 PIX11 PIX10 PIX9 PIX8 3C1> AGND3
6.8K 10%, 0.1W CR1206 VREF_EXT
3D1> VAA3
6.8K 10%, 0.1W CR1206
3C1> AGND3 FIELD_ENC 5B6> -VSYNC_ENC 5A6> 6B8< -HSYNC_ENC 5A6> 6B8< -BLANK_ENC 5A6> 6C2< 0.01µ CR1206
4.7µ 10%, THTANT
ICL8069DCZR TO92
3C1> AGND3
SLAVE ADDRESS SELECT JUMPER
5A6> VIDCLK 5D2> 5B2> 5A6> PIXCLK
Application Note 9743 HMP8154EVAL1 Evaluation Board Schematic Diagrams
1B4> Y_ENC 1.0µ 10%, CR1210 2.2µ 10%, CR1210 DUMMY 10%, CR1206 330P 10%, CR1206 2.2µ 10%, CR1210 DUMMY 10%, CR1206 330P 10%, CR1206 2.2µ 10%, CR1210 DUMMY 10%, CR1206 330P 10%, CR1206 2.2µ 10%, CR1210 DUMMY 10%, CR1206 330P 10%, CR1206 330P 10%, CR1206 DUMMY 10%, CR1206 10%, 0.1W CR1206 330P 10%, CR1206 1.0µ 10%, CR1210 10%, CR1206 DUMMY 10%, CR1206 10%, 0.1W CR1206 1.0µ 10%, CR1210 330P 10%, CR1206 1.0µ 10%, CR1210 10%, CR1206 DUMMY 10%, CR1206 10%, 0.1W CR1206 NP1_OUT 330P 10%, CR1206 1.0µ 10%, CR1210 10%, CR1206 DUMMY 10%, CR1206 10%, 0.1W CR1206 1.0µ 10%, CR1210 10%, CR1206
(Continued)
Y_OUT
BNCST J3-1
75.0 0.1W CR1206
10%, CR1206 DUMMY 10%, CR1206 1.0µ 10%, CR1210
3C1> AGND3
YOUT_RET
1B4> C_ENC
C_OUT
BNCST J4-1
75.0 0.1W CR1206
10%, CR1206 DUMMY 10%, CR1206 1.0µ 10%, CR1210
3C1> AGND3
COUT_RET
1B4> NP1_ENC
BNCST J5-1
75.0 0.1W CR1206
10%, CR1206 DUMMY 10%, CR1206
3C1> AGND3
NP1O_RET
1B4> NP2_ENC
NP2_OUT
BNCST J6-1
75.0 0.1W CR1206
10%, CR1206 DUMMY 10%, CR1206
3C1> AGND3
NP2O_RET
NOTE: Caps valued "dummy" populated. Components added/changed test alternate reconstruction filter circuits. FIGURE ANALOG OUTPUTS
Application Note 9743 HMP8154EVAL1 Evaluation Board Schematic Diagrams
FERRITE_BEAD TOL, 10%, THTANT 3D1> VAA3 10%, THTANT 0.1µ 10%, CR1206
(Continued)
VAA3 1B2< 1B8< 1D7< 3B4< 3C4< 0.01µ 10%, CR1206 AGND3 1A3< 1A6< 1A8< 1B3< 2A8< 2B8< 2C8< 3B4<
3C1> AGND3
0.1µ 10%, CR1206
0.01µ 10%, CR1206
0.1µ 10%, CR1206
CC47 0.01µ 10%, CR1206
0.1µ 10%, CR1206
0.01µ 10%, CR1206
3D1> VAA3
3C1> AGND3
0.1µ 10%, CR1206
0.01µ 10%, CR1206
0.1µ 10%, CR1206
0.01µ 10%, CR1206
0.1µ 10%, CR1206
0.01µ 10%, CR1206
0.1µ 10%, CR1206
0.1µ 10%, CR1206
0.1µ 10%, CR1206
0.1µ 10%, CR1206
0.1µ 10%, CR1206
3C7>
4.7µ 10%, THTANT
4.7µ 10%, THTANT
0.1µ 10%, CR1206
0.1µ 10%, CR1206
0.1µ 10%, CR1206
VCC\R 4H30 GND\R 4H30 GND\R 4H30 VEE\R 3A8< 5B7< 6A5< 6B5< 6C5< 4H30
FIGURE POWER/GND
DSUB25ST J1-M1 DSUB25ST J1-13 CR1206 10%, 0.1W
DSUB25ST J1-M2
BT_SHIELD
DSUB25ST J1-1
DSUB25ST BT656_CLK 5D4< DSUB25ST J1-15 CR1206 10H125 PLCC J1-2 BT_RET
10%, 0.1W CR1206
10%, 0.1W
DSUB25ST J1-14
DSUB25ST J1-18 10H125 -BT<7> DSUB25ST J1-22 DSUB25ST J1-5 BT<7> DSUB25ST J1-9 10H125
PLCC
PLCC
BT<3> -BT<3>
PLCC 10H125
Application Note 9743
HMP8154EVAL1 Evaluation Board Schematic Diagrams
FIGURE BT.656 INPUT
DSUB25ST J1-6 DSUB25ST J1-19 10H125 -BT<6> BT<6> 10H125 DSUB25ST J1-20 -BT<5> DSUB25ST J1-7 PLCC BT<5> PLCC 10H125 10H125 DSUB25ST J1-21 DSUB25ST J1-8 PLCC BT<4> -BT<4> PLCC 10H125
PLCC
DSUB25ST J1-10 DSUB25ST J1-23
BT<2> -BT<2>
PLCC 10H125
DSUB25ST J1-3
BT<9>
(Continued)
DSUB25ST J1-16
-BT<9>
DSUB25ST J1-11 DSUB25ST J1-24
BT<1> -BT<1>
PLCC 10H125
DSUB25ST
J1-4
BT<8>
DSUB25ST J1-17
-BT<8>
DSUB25ST J1-12 DSUB25ST J1-25
BT<0> -BT<0>
PLCC 10H125
BT656_PIX <9.0> 5D4< TERMINATORS SHOWN FIGURE
Application Note 9743 HMP8154EVAL1 Evaluation Board Schematic Diagrams
(Continued)
PIXEL DATA HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 P1-5 P1-6 P1-7 P1-8 P1-9 P1-10 P1-11 P1-12 P1-15 P1-16 P1-17 P1-18 P1-19 P1-20 P1-21 P1-22 P1-29 P1-30 P1-31 P1-32 P1-33 P1-34 P1-35 P1-36
PIX<23.0> 5D2> 1C6< 6D8< 4D6> BT656_CLK 4A1> BT656_PIX<9.0>
BT.656 INPUT ISOLATION SWITCH4
SOIC QS3384
PIXCLK 5A6> 5B2> 1A6< PIX<23.0> 5D6> 1C6< 6D8<
5B6> -BT656_EN
6.8K 10%, 0.1W CR1206
POWER GROUND HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 P1-1 P1-25 P1-26 P1-37 P1-50 P1-2 P1-13 P1-24 P1-27 P1-38 P1-49
PCLK_SMA SMAST J2-1 10%, 0.1W CR1206
PIXCLK 5A6> 5D2> 1A6< 10%, 0.1W CR1206 330P 10%, CR1206
-BT656_EN 3C7> 5C4<
HDR2X25 P1-14 HDR2X25 P1-4
10%, 0.1W CR1206
CONTROL HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 HDR2X25 P1-41 P1-28 P1-23 P1-40 P1-47 P1-48 P1-44 P1-43 P1-46 P1-3 FIELD_ENC 1A4> -HSYNC_ENC 1A4> 6B8< -VSYNC_ENC 1A4> 6B8< -BLANK_ENC 1A4> 6C2< PIXCLK 5B2> 5D2> 1A6< VIDCLK 1A6< 6A8< SDATA 1A6< 7C7< SCLK 1A6< 7C7< -RESET 1B6< 7C7< 1B6<
ALTERNATE CLOCK INPUT OUTPUT. USED OUTPUT, VERY LIMITED DRIVE STRENGTH.
DIFFERENCES BETWEEN EVAL1 EVAL2 CONNECTORS Field EVAL2 BT656 Disable Field HERE
CONNECTS HDR2X25 P1-39 HDR2X25 P1-42 HDR2X25 P1-45
FIGURE EVM1 CONNECTOR CLOCKS
BT<9.0> BT<9.0> -BT<9.0> 3C7> COMMON R-PACK TSIP10 0.1W COMMON R-PACK TSIP10 0.1W 3C7> COMMON COMMON -BT_CLK -BT_CLK 3C7> R-PACK TSIP10 0.1W R-PACK TSIP10 0.1W COMMON -BT<9.0> R-PACK ISIP10 0.1W
6.8K 10%, 0.1W CR1206 5A6> 1A4> -BLANK_ENC
PIX<23.0> 5D6> 5D2>
R-PACK TSIP10 0.1W
R-PACK ISIP10 0.1W
Application Note 9743
HMP8154EVAL1 Evaluation Board Schematic Diagrams
FIGURE PUP/PUD TERMINATIONS
COMMON
5A6> 1A4> -VSYNC_ENC -HSYNC_ENC 5A6> 1A4>
R-PACK TSIP10 0.1W
INLINE RESISTORS DIFFERENTIAL TERMINATIONS, VALUE REQUIRED DEPENDS PULL DOWN RESISTOR DRIVER, APPROXIMATE VALID RANGE TYPICAL 1/25 SHOULD ALSO CLOSE IMPEDANCE CABLE.
(Continued)
5A6> VIDCLK
PULL PULL DOWN RESISTORS PREVENT ENCODER'S UNDRIVEN INPUTS FROM FLOATING.
PULL DOWN TSIP R-PACKS POPULATED. ONLY INSTALL THEM DATA SOURCE DOES INCLUDE PULL DOWN RESISTORS DRIVERS. INCLUDING PUDS THIS BOARD DEGRADE ENCODER'S PERFORMANCE.
10%, 0.1W CR1206 6.8K 10%, 0.1W CR1206
6.8K 10%, 0.1W CR1206
5A6> -RESET
MXKK5 MXKK5 MXKK5 MXKK5 MXKK5
PC_DOE
PC_RET
5A6> SDATA
5A6> SCLK
Application Note 9743
HMP8154EVAL1 Evaluation Board Schematic Diagrams
FIGURE INTERFACE
10%, 0.1W CR1206 10%, 0.1W CR1206 CR1206 TRANSISTOR OPEN COLLECTOR USED THREE-STATE DRIVER. HIGH OUTPUT ENABLE FORCES DATA LINE LOW. OTHERWISE, FLOATS HIGH.
6.8K 10%, 0.1W
2N3704 TO92C
(Continued)
CONNECTOR MOLEX HEADER, PART NUMBER 22-23-2051. MATING TERMINAL HOUSING CABLE PART NUMBER 22-01-3057. HOUSING REQUIRES CONTACTS TOO. AVAILABLE FROM DIGI-KEY. CAUTION: SOME MOLEX DOCUMENTATION SHOWS HEADER ALIGNED WITH HOUSING.
PARALLEL TERMINATION (R14 R25) SCLK STANDARD SPEC. (SPEC REQUIRES 4-10kW VCC.) USING THIS TERMINATION INCREASE DATA TURN TIME SCLK CAUSED VERY LARGE CAPACITANCE CABLE DRIVER. REQUIRES DRIVE. INCREASING RESISTOR VALUES LOWERS CURRENT REQUIRED INCREASES CABLE BOARD IMPEDANCE MISMATCH NOISE.
Application Note 9743 HMP8154EVAL1 Evaluation Board Parts List
ITEM REFERENCE DESIGNATOR C21, C31, C34, C36, C46, C47, C22, C23, C32, C33, C35, C37-C39, C48, C49, C51, C53C55, C58, C12, C16, C17, C25, C40, C41, C43, C10, C18, C27, C14, C29, C11, C13, C15, C19, C26, C28, C30, C42, C45, C20, J3-J6 J7-J10 PART NAME CAPACITOR_CR1206-0.01µ, 25V, MANUFACTURER VARIOUS PART NUMBER
CAPACITOR_CR1206-0.1µ, 25V, VARIOUS
CAPACITOR_CR1206-330P, 25V,
VARIOUS
CAPACITOR_CR1206-39P, 25V, VARIOUS CAPACITOR_CR1206-82P, 25V, VARIOUS CAPACITOR_CR1206-DUMMY, 25V, POLARCAP_THTANT-15µ, 15V, POPULATED
KEMET
T350E156K016AS T350B475K016AS ICL8069DCZR 31-5329 142-0701-201 ARTWORK 745967-7 206514-1 69190-402 65474-010
POLARCAP_THTANT-4.7µ, 15V, KEMET DIODE_TO92-ICL8069DCZR COAX_BNCST COAX_SMAST EPOINT_4H30 HARRIS AMPHENOL-RF JOHNSON COMPON. PLATED THRU-HOLE
JP2, JP5, JP2, JP1, JP3, L7-L9, L12, L10,
JCONNECTOR_DSUB25S LOCKING_POST JUMPER2 JUMPER_SHUNT ULOOP HEAVY GAUGE WIRE INDUCTOR_CR1210-1.0µ, 30Q, INDUCTOR_CR1210-2.2µ, 30Q, INDUCTOR_THFERRITE_BEAD,5A,TOL JCONNECTOR_HDR2X25 POST_MXKK5 HMP815X_EVAL1 NPNBJT_TO92C-2N3704 POTENTIOM_TH-200, 0.5W, RESISTOR_CR1206-0, 0.1W, RESISTOR_CR1206-100, 0.1W, RESISTOR_CR1206-470, 0.1W, RESISTOR_CR1206-51, 0.1W,
BERG ELECTRONIC BERG ELECTRONIC DALE DALE DEXTER MAGNET MOLEX NATIONAL SEMI DALE VARIOUS VARIOUS VARIOUS VARIOUS
IMC1210-1.0UH-10 IMC1210-2.2UH-10 2743001111
R10-R12, R16, R22-R24
2-102973-5 22-23-2051 T93YA-200-10
Application Note 9743 HMP8154EVAL1 Evaluation Board Parts List
ITEM REFERENCE DESIGNATOR R15, R17, R18, R20, R21, R13, U6-U8 (Continued) MANUFACTURER PART NUMBER
PART NAME
RESISTOR_CR1206-6.8K, 0.1W, VARIOUS
RESISTOR_CR1206-820, 0.1W, ESISTOR_CR1206-93.1, 0.1W, 10H125_PLCC HMP8154_MQFP
VARIOUS VARIOUS MOTOROLA HARRIS
MC10H125FN HMP8156CN HMP8154CN QS3384SO
U11-U13 U1-U3
QS3384_SOIC RESISTOR_ISIP10-100, 0.1W, RESISTOR_TSIP10-10K, 0.1W, RESISTOR_TSIP10-560, 0.1W,
QUALITY SEMI VARIOUS VARIOUS VARIOUS
HMP8154EVAL1 Evaluation Board Layout
FIGURE SILK SCREEN
Application Note 9743 HMP8154EVAL1 Evaluation Board Layout
(Continued)
FIGURE LAYER COMPONENT SIDE
FIGURE LAYER GROUND
Application Note 9743 HMP8154EVAL1 Evaluation Board Layout
(Continued)
FIGURE LAYER VEE, VCC,
FIGURE BOTTOM LAYER SOLDER SIDE
Application Note 9743 HMP8154EVAL1 Evaluation Board Layout
(Continued)
FIGURE SILK SCREEN BOTTOM
Harris Semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
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