Harris Digital Interfacing Harris CDP68HC05 Microcontrollers with
|
|
|
Top Searches for this datasheet
AN9704.1
Harris Digital
Interfacing Harris CDP68HC05 Microcontrollers with Serial EEPROMs
Author: Christopher Mazzanti
Introduction
world embedded controls, 8-bit microcontrollers controlling everything from engine management units coffee makers. Manufacturers products using these microcontrollers constantly search most cost effective solution their design. most, this usually means small, inexpensive mask-ROM microcontroller such Harris CDP68HC05J4B. However, there need times microcontroller store data such security access codes text strings readable/writable, non-volatile memory such EEPROM. Since number port lines available microcontrollers limited, conventional EEPROMs like 28C64 simply question. Fortunately, there alternative serial EEPROMs. These small, inexpensive simple devices available from several semiconductor manufacturers. Often, chip solution Harris mask-ROM 68HC05 second party serial EEPROM cheaper than microcontroller with EEPROM. There main types serial EEPROMs those with wire interface (such 24LC65) those with compatible three wire interface (such 93LC56). This Application Note will cover basics interfacing Harris 68HC05 microcontrollers with serial EEPROMs.
Advantages three-wire interface include direct compatibility with controller available Harris CDP68HC05C4B, CDP68HC05C8B CDP68HC05C16B microcontrollers fast (2MHz max.) rates. Drawbacks many (four minimum) more lines needed interface EEPROM. Memory size interface should, course, decided such factors price, availability, code size, performance ease use.
Wire Interface
This application note describes interface between Harris 68HC05 microcontroller 24LC65 64kBit (arranged serial EEPROM using protocol developed Phillips Corporation. This interface standard used most two-wire interface EEPROMs such 24AA01/02, 24AA16, 24LC16B, 24C32, etc. Since full implementation protocol defined Phillips beyond scope this application note, only described much detail needed interface EEPROMs. This application note assumes user read technical specifications Harris CDP68HC05 microcontroller EEPROM being used. Interface interface protocol developed Phillips Corporation support multiple masters multiple slaves tied together wire bus. wires this called (Serial DAta) (Serial CLock). Data transmitted synchronously line according clock line. When data being transmitted, said "idle" lines logic level (5VDC this application note). facilitate multiple devices connected same bus, each device should actively pull transmit passively release transmit "1". With pull-up resistors each line, negetive logic wire-OR connection created. master defined device that start data transmission. During this transmission, master either transmit data (master-transmitter) receive data (masterreceiver). cases, master ALWAYS generates clock pulses line. slave defined device that receives data from master (slave-receiver)
What Kind EEPROM
Serial EEPROMs available various memory sizes ranging from 1kbit (128 64kbit beyond. interface, both two-wire three-wire interfaces have their pros cons. biggest advantage two-wire interface number port pins needed interfacing. it's name implies, two-wire interface requires only pins. additional benefit that multiple two-wire EEPROMs easily placed increased storage without other hardware modifications. Since each device "address" that sent over beginning each transmission, there need chip select lines that take valuable space. Drawbacks two-wire interface slow access speeds complexity interface software when compared that three-wire interface.
Copyright
Harris Corporation 1997
Application Note 9704
transmits data master (slave-transmitter). cases data transmission started master. When reading data from EEPROM, 68HC05 acts masterreceiver 24LC65 acts slave-transmitter. When writing data EEPROM, 68HC05 acts mastertransmitter 24LC65 acts slave-receiver. Other protocol aspects follows: Idle both lines high. Start Condition line pulled from high device while line high, this referred START condition. data transmissions must initiated start condition. (See Figure Stop Condition line goes from high while high, this referred STOP condition. data transmissions must with STOP condition. (See Figure Data Transmission Data transmitted synchronously with respect clock pulses being generated master. When line high, line allowed change. Data considered valid during this time. When data change next bit. must stable when goes high again. transition while high interpreted either start stop condition slave. (See Figure Acknowledge Data transmitted line byte time. each byte transmission, receiving device must generate "acknowledge" transmitting device. receiving device does this pulling line after last byte transmitted while master generates clock. This means that clocks required transmit byte data. device generating acknowledge must sure that line stable does change during high period ninth clock pulse. (See Figure Message Format Standard protocol sets specific format data transferred along bus. data transmission must started master only when idle. this application note, assume that 68HC05 only master thus idle unless driven 68HC05. start transmission, master generates start condition follows this with address slave being addressed. Phillips defines types address protocol 10-bit long address format 7-bit short address format. Since serial EEPROMs concerned with 7-bit format, 10-bit protocol will discussed. Once start condition been generated, master shifts slave address bus, most significant first (all data transmissions occur first). eighth transmitted READ/WRITE bit. this high, then slave knows prepare transmit data. this low, slave knows receive data. START conditions should followed address byte. slave being addressed available communications, slave will acknowledge pulling during ninth clock pulse (See previous discussion). After START condition generated address byte sent, master slave transfer unlimited number data bytes between them. Each byte transmitted followed acknowledge. When transmission complete, master must generate STOP condition signify that data transmission over. should noted that master generate start condition middle data transmission sequence (between bytes); this known repeated start condition. further discussion protocol, complete specifications from Phillips/Signetics (document number 98-8080-575).
Implementation
mentioned before, bus, devices hang common each device address. When master wishes start communication with slave device, that master must first generate start condition followed address bits 24LC65 used this example). While this protocol adds overhead makes timing data transmission more complex, does have advantage that devices added without additional hardware. 24LCxx series serial EEPROMs available PDIP SOIC packages (See pin-out diagram below). tell from package outline, there three external pins (A2,
START CONDITION
DATA VALID
DATA CHANGE
ACKNOWLEDGE
STOP CONDITION
FIGURE PROTOCOL DEFINITIONS
Application Note 9704
setting address device. upper four bits address 1010b This allows maximum 23=8 24LCxx devices same bus. case 24LC65, this results full 64kB (512kbits) external EEPROM. Also, other devices such converters, parallel ports drivers also connected same bus.
however, that setting drives clearing puts onto bus. Several locations need allocated these routines. Some these, like i2c_reg used most level routines some high level routines. Other locations user choose combine with those main program. locations used these routines follows: i2c_reg control register. Bits within this location (ack, bus_busy, error) used status control level subroutines. This location removed. dataHi High byte EEPROM data pointer, used high level subroutines accessing EEPORM memory. dataLo byte EEPROM data pointer, used conjunction with dataHi point addresses EEPROM memory. i2ctemp, i2cTemp1, counter temporary storage locations used both high level subroutines preserve value accumulator. These combined with temp values user program provided that data locations will destroyed when EEPROM subroutine called. software routines included below derived from basic subroutines developed 68HC05. These routines have been altered from their full versions they support 10-bit addressing, arbitration multiple masters. These subroutines (SendStart, SendStop, SendByte, SendAddr, GetByte I2CInit) generic routine that used kind (albeit with limitations described above) referred this document "low level" subroutines. Other subroutines interfacing specifically 24LC65 included "high level" routines such eeWrite, eeRead, incData decData. general, main program will ever call "low-level" routines (with exception I2CInit) these will accessed only "high-level routines". explanation these subroutine included below along with small sample program that used test them. Level Subroutines i2cInit This routine used interface within microcontroller. first thing that done clear status control registers. Then, bits cleared, releasing bus. Next, logic "0"s written into port latches. Notice here that cannot BCLR BSET instruction altering these bits. This because BCLR BSET instructions read-modify-write operations that read data, with mask write modified data back. This fine when port output because read port reads data latches. However, when port input, read reads input write writes data latches. port data latch written input mode, read that will return "1". BCLR BSET done another same port, will read that location (since it's reading input pulled high through
FIGURE 24LCxx SERIAL EEPROM
HARDWARE basic hardware setup this application note includes Harris CDP68HC05J4B microcontroller 24LC65 serial EEPROMs. shown schematic below (Figure have connected 24LC65s CDP68HC05J4B bus. address bits devices tied 001, giving them slave addresses 1010000 1010001.
CDP68HC05J4B
24LC65
SERIAL DATA SERIAL CLOCK
24LC65
FIGURE SERIAL EEPROM INTERFACE HARRIS CDP68HC05J4B
SOFTWARE busis active-low, passive-high negative logic wire-OR bus. Devices must pull transmit release pulled high through pull resistors transmit "1". Since port outputs most 68HC05 microcontrollers CMOS push-pull outputs, port output transmission. can, however, simulate write port data latches port pins manipulating associated bits turn outputs off. When set, it's port becomes output logic driven onto bus. When clear, port becomes input pulled high through external resistor. Thus, manipulation done setting clearing bits. Keep mind,
Application Note 9704
resistor), with mask write back port register, destroying that there. What when clearing port data read port, with special mask write back. After this done, port bits cleared their DDRs input. line then tested make sure other device transmitting. This step left over from general purpose routines needed assuming this application note) 68HC05 only master bus. SendStart this routine used send start condition onto bus. This first thing that done when transmission begins. This routine also used sending repeated start conditions. DELAY subroutine used here many other places level transmission routines necessary make sure that high, low, free other timing specifications met. 68HC05 operation 4MHz, subroutine call return take between 5.5µs 6µs, much longer than necessary 100kHz protocol. speeds higher than 4MHz, necessary some more delay DELAY routine. SendStart routine assumes that high (released) when called. bus_busy flag upon return. SendStop this routine used send stop condition onto bus. This last thing that must done transmission. This routine, like SendStart, calls DELAY. bus_busy flag cleared upon return. SendByte this main routine used send address data from 68HC05 EEPROMs. This routine assumes that SendStart already been called 68HC05 current master bus. byte data transmitted must passed this routine accumulator. sending bits onto SendByte will generate ninth clock pulse look slave acknowledgment. slave acknowledges, "ack" i2c_reg register will set, otherwise will cleared. GetByte this main routine used 68HC05 receive data master-receiver (i.e., 68HC05 will generate clock pulses). "ack" i2c_reg register, GetByte will send acknowledgment slave-transmitter, otherwise none will sent. Delay this main timing delay routine used most low-level routines. This routine listing file CDP68HC05J4B operating 4MHz. 4MHz, entire routine simply RTS. call immediate return will between 5.5µs 6µs, well within timing specification 100kHz protocol. 68HC05 speeds higher than 4MHz, more delay need added this routine. Calls this subroutine replaced with NOPs calling routines increased speeds. High Level Subroutines high level subroutines software listing below written that EEPROM memory space continous 64kB. Since each 24LC65 memory, this means that there eight 24LC65 devices together. Since EEPROM memory space separate from regular 68HC05 memory (for obvious reasons), writes EEPROMs cannot addressed program counter 68HC05. high-level routines therefore separate EEPROM data pointer locations (dataHi:dataLo). Whatever data written read from EEPROMs will done from 16-bit address created concatenating contents these locations. incData this simple routine increment EEPROM data pointer RAM. Since 68HC05 does have 16-bit increment instruction, incrementing these locations takes several instructions. high byte data pointer masked total EEPROM memory mask value that will "rollover" appropriate value. decData this simple routine decrement EEPROM data pointer RAM. high byte data pointer masked total EEPROM memory mask value that will "rollunder" appropriate value. eeWrite eeWrite routine used write single byte data contained accumulator EEPROMs address contained EEPROM data pointer dataHi:dataLo. address EEPROM separated this routine upper three bits used last three bits EEPROMs address this particular example using 24LC65s, that rest used address within each device. This routine also uses address "mask" values this routine memMask devMask. These masks, beginning program, used make sure non-valid address values accessed. devMask value used mask data upper limit physical memory available within each device should equal upper byte highest address available within chip. 24LC65 used example program have physical memory space each, their upper address limit $1FFF. Thus devMask 24LC65 $1F. Values above $1FFF would masked those within $0000$1FFF. This way, invalid addresses (i.e. $2500) sent EEPROMs. memMask value used mask data pointer upper limit available memory. This value should equal upper byte highest address available when EEPROM memory ranges added together. Since several devices once, this value will need each specific application. this application note there 24LC65 EEPROMs bus, each containing memory space. Thus total available EEPROM memory available 16kB memMask (since $3FFF highest available memory location). This mask removed from subroutines, data pointer incremented above
Application Note 9704
available EEPROM memory, accesses these addresses will result negative acknowledge. drawbacks this convention that devices different memory sizes (like 24LC65 24LC01) used same bus. 24LC65 does issue acknowledge (i.e., middle write cycle), "error" will return. write successful "error" will return cleared. calling routine must monitor status "error" i2c_reg register determine write successful. eeRead This routine compliment eeWrite routine described above. this routine byte data read from location pointed EEPROM data pointer returned accumulator. eeWrite subroutine, slave EEPROM does acknowledge byte transmission, routine will return with "error" set, otherwise will cleared. This routine could used test whether EEPROM finished with write cycle. Sample Program example program includes subroutines described above plus little program show they used together. beginning listing shows what locations setup subroutines. purpose this program take bytes data from locations $60-$67, write them EEPROM memory, read same bytes back from EEPROMs write them locations $70-$77. program starts setting EEPROM data pointer address (this where data will written inside EEPROMs). Notice that value ctlByte upper four bits address specifically designated 24LC65 serial EEPROM.
Conclusion
Serial EEPROMs small, inexpensive solutions problem CDP68HC05 microcontrollers without chip EEPROM. Often times chip solution will cheaper than purchasing 68HC05 variant with EEPROM. These serial EEPROMs easy require little external support circuitry. should noted many serial EEPROMs have additional capabilities beyond single byte read write detailed here. Depending upon device it's manufacturer, other functions such block reads, block writes security options also available. Check technical datasheet EEPROM manufacturer more information about other capabilities serial EEPROMs. more information Harris CDP68HC05 microcontrollers, including technical datasheets free CDP68HC05 software development tools, visit sight
Application Note 9704
HARRIS Semiconductor (c)1990 1996 68HC05 Assembler Version Filename: SEEPROM.LST Source Created: 01/13/97, 00:30 Assembled: 01/13/97, 00:30:01 00001 00002 aaaaaaaaaaaa 00003 rH""""HHHH""""Hr 00004 HHHH COPYRIGHT 1995,1996,1997 00005 HARRIS SEMICONDUCTOR 00006 00007 ssss 00008 HHHH 00009 "HHHHHHHHHHHH" 00010 00011 File: seeprom.s 00012 00013 Version: 00014 00015 Author: Christopher Mazzanti 00016 00017 Date: 01-07-96 00018 00019 Description: 00020 following file subroutines created inter00021 afacing 68HC05 with 24LC65 type serial EERPOM. 00022 small main program used testing these routines 00023 meant with in-circuit emulator like 68HC05ICE. 00024 This program takes eight bytes from $60-$67, writes them 00025 eeproms, reads them back puting read data $70-$77. 00026 This program access 24LC65's total eeprom 00027 address space 16kB. EEPROM addresses written read 00028 from from $1FFC $2003, thus testing device boundary 00029 switching devices. 00030 00031 #include c:\6805\j4b.s START INCLUDE C:\6805\J4B.S -00001 #nolist 00125 #list INCLUDE C:\6805\J4B.S -00032 00033 Define Statements: following constants must defined 00034 proper operation EEPROM interface 00035 subroutines: 00036 where lines connected 00037 position connection port 00038 position connection port 00039 ctlByte upper four bits address common 24LC65's 00040 memMask used mask upper byte TOTAL EEPROM memory space 00041 devMask used mask upper byte individual EEPROM memory 00042 00043 $0000 00044 $0001 00045 $0004 ddra ;i2c port DDRA 00046 $00A0 ctlByte ;control byte 24LC65 00047 $003F memMask ;total EEPROM address mask (mask 16k) 00048 $001F devMask ;EEPROM device address mask 24LC65) 00049 00050 00051 Variables: following locations must allocated 00052 serial EEPROM interface subroutines. 00053 i2c_reg status/control register used routines 00054 dataHi/dataLo used contain 16-bit EEPROM memory address 00055 i2cTemp, i2cTemp1, counter scratch locations routines
Application Note 9704
00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 00119 00120 00121 0050 0050 $0000 $0001 $0002 $0003 0051 0052 0053 0054 0055 $005F $0070 0100 0100 0101 0102 0104 0106 0108 010A 010D 010F 0111 0113 0115 0118 011A 011B 011D 011F 0121 0123 0126 0128 012A 012B 012D A620 B751 A603 B752 CD01CF AE08 writeLoop 1550 E65F AD42 0450F7 AD28 26F2 AD12 readLoop 1550 AD6D 0450F9 E770 AD07 A308 26F0 break 012F 20FE ;loop continously bclr brset incx error,i2c_reg eeRead error,i2c_reg,readLoop dataIn,x incData #$08 readLoop ;clear error ;read data ;check error ;store data byte ;increment data pointer bclr brset decx error,i2c_reg data,x eeWrite error,i2c_reg,writeLoop decData writeLoop incData ;increment data pointer ;clear error flag set) ;get data byte ;wrtie memory ;check error ;decrement data pointer ;dec loop counter i2c_reg rw_bit bus_busy error dataHi dataLo i2ctemp i2ctemp1 counter data dataIn section ramVars, ;I2C control register ;read/write (bit ;bus status flag ;bus error flag ;slave acknowledge ;High byte EEPROM data pointer ;Low byte EEPROM data pointer ;scratch location ;general purpose counter ;used test program ;used test program
section code, $100 ;mask interrupts ;reset stack pointer ;set data pointer ;EEPROM location $2003
#$20 dataHi #$03 dataLo i2cInit #$08
;setup interface ;set loop counter
incData This routine increments data pointer dataHi:dataLo next location. after incrementing, high byte exceeds eeprom memory available (determined memMask) data pointer masked physical eeprom memory. Returns: ACCA-unchanged, IX-unchanged Calls: none Altered: dataHi, dataLo, i2ctemp1 incData 0131 3C52 dataLo ;inc byte counter
Application Note 9704
00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 00183 00184 00185 00186 00187 0133 0135 0137 0139 013B 013D 013F 0141 260C 3C51 B754 B651 A43F B751 B654 doneInc decData This routine decrements data pointer dataHi:dataLo previous location. After decrementing, high byte poniter will masked physical eeprom memory. Returns: ACCA-unchanged, IX-unchanged Calls: none Altered: dataHi, dataLo, i2cTemp1 decData 0142 0144 0146 0148 014A 014C 014E 0150 0152 0154 0156 B754 B652 A001 B752 2408 3A51 B651 A43F B751 doneDec B654 i2cTemp1 ;restore ACCA i2cTemp1 dataLo #$01 dataLo doneDec dataHi dataHi #memMask dataHi ;preserve ACCA ;dec byte doneInc dataHi i2cTemp1 dataHi #memMask dataHi i2cTemp1 ;end dataLo carry, high byte ;preserve ACCA ;mask physical eeprom
;restore ACCA
carry, quit carry, high byte ;mask physical eeprom
eeWrite This routine take value ACCA writes EEPROM location specified data pointers dataHi:dataLo upper three bits this address used address EEPROM. This routine returns carry clear write sucessful write failed. This routine will fail eeprom middle write cycle. Returns: ACCA-unchanged, IX-unchanged Calls: sendStart, sendByte, getByte, sendStop Altered: i2cTemp, i2cTemp1, i2c_reg eeWrite 0157 0159 015C 015F 0161 0163 0164 0165 0166 0167 0169 016B 016E 0171 0173 0175 B754 CD01EF 04502D B651 A43F A4FE ABA0 CD020B 07501B B651 A41F CD020B brset lsra lsra lsra lsra brclr i2cTemp1 sendStart error,i2c_reg,abrtWrite dataHi #memMask ;preserve ACCA ;send start condition error flag set, abort ;make address ;mask Address physical
#$FE #ctlByte sendByte ack,i2c_reg,abrtWrite dataHi #devMask sendByte
;clear ;add control byte ;send address acknowledge, abort ;send high byte data ;mask device physical
Application Note 9704
00188 00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 00233 00234 00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 00249 00250 00251 00252 00253 0178 017A 017D 0180 0182 0185 0188 018A 018C 018E B652 07500F CD020B B654 CD020B 075004 1550 EndWrite 2072 abrtWrite 1450 20FA bset error,i2c_reg endWrite sendStop brclr brclr bclr dataLo ack,i2c_reg,abrtWrite sendByte i2cTemp1 sendByte ack,i2c_reg,abrtWrite error,i2c_reg ;send byte data acknowledge, abort
;send data acknowledge, abort
eeRead This routine reads byte EEPROM from address specified dataHi:dataLo returns ACCA. upper three bits this address used address EEPROM. This routine returns carry clear read sucessful read failed. This routine will fail eeprom middle write cycle. Returns: ACCA-byte read, IX-unchanged Calls: sendStart, sendByte, getByte, sendStop Altered: i2cTemp1, i2c_reg, ACCA eeRead 0190 0192 0195 0197 0199 019A 019B 019C 019D 019F 01A1 01A3 01A5 01A8 01AA 01AC 01AE 01B1 01B3 01B5 01B8 01BA 01BC 01BE 01C0 01C3 01C5 01C7 01C9 01CB 01CD AD5D 045036 B651 A43F A4FE ABA0 B754 AD66 075023 B651 A41F AD5D 07501A B652 AD56 075013 AD35 B654 AA01 AD4B 075008 1750 AD71 1550 exitRead 2033 abrtRead 1450 20FA bset error,i2c_reg exitRead sendStop ;send stop condition brset lsra lsra lsra lsra brclr brclr brclr brclr bclr bclr sendStart error,i2c_reg,abrtRead dataHi #memMask ;send start condition error flag set, abort ;make address ;mask Address physical
#$FE #ctlByte i2cTemp1 sendByte ack,i2c_reg,abrtRead dataHi #devMask sendByte ack,i2c_reg,abrtRead dataLo sendByte ack,i2c_reg,abrtRead repeatStart i2cTemp1 #$01 sendByte ack,i2c_reg,abrtRead ack,i2c_reg getByte error,i2c_reg
;clear ;add control byte ;send address acknowledge, abort ;send high byte data ;mask device physical acknowledge, abort ;send byte data acknowledge, abort ;repeated start condition ;set ;send control byte acknowledge, abort master byte only) ;get byte from eeprom ;clear error return
Initialization, i2cInit This routine sets 6805 interface bus. successful, released.
Application Note 9704
00254 00255 00256 00257 00258 00259 00260 00261 00262 00263 00264 00265 00266 00267 00268 00269 00270 00271 00272 00273 00274 00275 00276 00277 00278 00279 00280 00281 00282 00283 00284 00285 00286 00287 00288 00289 00290 00291 00292 00293 00294 00295 00296 00297 00298 00299 00300 00301 00302 00303 00304 00305 00306 00307 00308 00309 00310 00311 00312 00313 00314 00315 00316 00317 00318 00319 bus_busy flag status register will return another master detected transmitting. Returns: ACCA-unchanged, IX-unchanged Calls: delay Altered: i2c_reg i2cInit 01CF 01D1 01D3 01D5 01D7 01D9 01DB 01DD 01E0 01E2 01E4 01E5 01E7 01EA 01EC 01EE B753 3F50 1104 1304 B600 A4FC B700 000005 1250 B653 Init1 AD7D 000002 1250 Init2 B653 i2cTemp brset bset delay scl,i2c-4,init2 bus_busy,i2c_reg ;delay free time ;make sure high ;SCL low, busy bclr bclr brset bset i2cTemp i2c_reg scl,i2c sda,i2c i2c-4 #~(2!sda+2!scl) i2c-4 scl,i2c-4,Init1 bus_busy,i2c_reg i2cTemp ;preserve ACCA ;clear status register release lines ;make sure high ;SCL high, must busy ;restore ACCA
Send Start SendStart, repeatStart These routines send either start condition repeated start condition onto bus. this routine called from SendStart, this routine will quit busy flag set. called from repeatStart, busy flag ignored. successful, held upon return. Returns: ACCA-unchanged, IX-unchanged Calls: delay Altered: i2c_reg SendStart repeatStart 01EF 01F1 01F3 01F5 01F7 01F9 01FB 01FD 1304 1104 AD6F 1204 AD6B 1004 1250 bclr bclr bset bset bset sda,i2c scl,i2c delay sda,i2c delay scl,i2c bus_busy,i2c_reg ;release line ;release line ;call delay, free time tbuf ;pull while high ;start cond. setup time ;pull ;set busy flag
Send Stop This routine sends stop condition onto bus. successful, released. line should calling this routine. busy flag cleared upon return. Returns: ACCA-unchanged, IX-unchanged Calls: delay Altered: i2c_reg SendStop 01FE 0200 0202 1204 AD62 1104 bset bclr sda,i2c delay scl,i2c ;pull line ;call delay, free time tbuf ;release
Application Note 9704
00320 00321 00322 00323 00324 00325 00326 00327 00328 00329 00330 00331 00332 00333 00334 00335 00336 00337 00338 00339 00340 00341 00342 00343 00344 00345 00346 00347 00348 00349 00350 00351 00352 00353 00354 00355 00356 00357 00358 00359 00360 00361 00362 00363 00364 00365 00366 00367 00368 00369 00370 00371 00372 00373 00374 00375 00376 00377 00378 00379 00380 00381 00382 00383 00384 00385 0204 0206 0208 020A AD5E 1304 1350 bclr bclr delay sda,i2c bus_busy,i2c_reg ;start cond. setup time ;and release ;set busy flag
Send Byte, SendByte This routine sends byte data contained ACCA This routine will check slave acknowledge i2c_reg register accordingly. This routine will abort ERROR set. Returns: ACCA-unchanged, IX-unchanged Calls: delay Altered: i2c_reg, i2cTemp, counter SendByte 020B 020D 020E 0210 0212 0214 0216 0218 021A 021C 021E 0220 0222 0224 0226 0228 022A 022C 022E 0230 0233 0235 0237 B753 A608 B755 B653 bytLoop 3853 1204 2402 1304 sendbit 1104 AD44 1004 AD40 3A55 26EC getAck 1304 1104 AD36 1750 020002 1650 doneByte 1004 bset scl,i2c ;pull bclr bclr bclr brset bset sda,i2c scl,i2c delay ack,i2c_reg sda,i2c-4,doneByte ack,i2c_reg ;release ;release ;call thigh delay ;clear flag SDA=1, ;set flag bclr bset scl,i2c delay scl,i2c delay counter bytLoop ;release ;pull ;use only >4MHz bset bclr i2ctemp sda,i2c sendbit sda,i2c ;get next ;pull ;release i2ctemp counter i2cTemp ;store copy address ;clear carry ;set counter ;restore
Byte, GetByte This routine gets byte data master transmitter returns byte ACCA. This routine will gen; erate acknowledge set. This routine assumes that low. Returns: ACCA-unchanged, IX-unchanged Calls: delay Altered: i2c_reg, i2cTemp, counter GetByte 0238 0239 023B 023D 023F 0241 0243 0245 3F53 1304 A608 B755 bytLoop2 AD21 1104 AD1D bclr delay scl,i2c delay ;send high ;Thigh bclr i2ctemp sda,i2c counter ;mask interrupts ;store copy address ;release ;set counter
Application Note 9704
00386 00387 00388 00389 00390 00391 00392 00393 00394 00395 00396 00397 00398 00399 00400 00401 00402 00403 00404 00405 00406 00407 00408 00409 00410 00411 00412 00413 00414 00415 00416 00417 00418 00419 00420 00421 00422 00423 00424 00425 00426 0247 0248 024B 024C 024E 0250 0252 0254 0256 0259 025B 025D 025F 0261 0263 030001 shiftByte 3953 1004 3A55 26ED AD0E 075002 1204 noAck 1104 AD05 1004 B653 bclr bset scl,i2c delay scl,i2c i2cTemp ;release ;ninth clock pulse bset brclr bset i2cTemp scl,i2c counter bytLoop2 delay ack,i2c_reg,noAck sda,i2c ;rotate byte through carry ;pull ;decriment byte counter ;Tlow ;check acknowledgment ;send brclr ;clear carry shifting sda,i2c-4,shiftByte
Delay This delay routine timing transitions bus. length this delay controlled crystal speed, should ~6000ns. 100kHz protocol, thigh 4000ns tlow 4700ns. this routine called bsr, total execution time will 6000ns. called JSR, total execution time will 5500ns. crystal speeds higher than 4MHz, extra delay will need added. Delay 0264
3FF4 3FF4 3FF6 3FF8 3FFA 3FFC 3FFE
0100 0100 0100 0100 0100 0100
section vectors, $1FF4 $0100 $0100 $0100 $0100 $0100 $0100
Harris Semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Harris Semiconductor products sold description only. Harris Semiconductor reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Harris believed accurate reliable. However, responsibility assumed Harris subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Harris subsidiaries.
Sales Office Headquarters
general information regarding Harris Semiconductor products, call 1-800-4-HARRIS NORTH AMERICA Harris Semiconductor 883, Mail Stop 53-210 Melbourne, 32902 TEL: 1-800-442-7747 (407) 729-4984 FAX: (407) 729-5321 EUROPE Harris Semiconductor Mercure Center 100, Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Harris Semiconductor Ltd. Tannery Road Cencon #09-01 Singapore 1334 TEL: (65) 748-4200 FAX: (65) 748-0400
Other recent searches
TS393 - TS393 TS393 Datasheet
TPS51117 - TPS51117 TPS51117 Datasheet
SN74LS42 - SN74LS42 SN74LS42 Datasheet
MX887D - MX887D MX887D Datasheet
MTV016 - MTV016 MTV016 Datasheet
ISL9219 - ISL9219 ISL9219 Datasheet
BU208D - BU208D BU208D Datasheet
508D - 508D 508D Datasheet
508DFI - 508DFI 508DFI Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
