Harris Wireless Products Hardware/Software Interface Description

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Harris Wireless Products Hardware/Software Interface Description

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AN9617.1
Harris Wireless Products
Hardware/Software Interface Description PRISMRadio Design with Example Using AM79C930 Media Access Controller
Authors: John Fakatselis Mike Paljug
Introduction
Hardware Configuration
block diagram Figure intended show level view basic hardware devices comprising radio design. detailed list signal interfaces required between Physical Layer (PHY) PRISM radio listed Table this document.
This document includes description HW/SW interface IEEE802.11 target radio architecture based Harris PRISMchip Media Access Controller (MAC) AM79C930 processor. information includes necessary interface requirements that used control PRISM radio with other controller processor that does necessarily target IEEE802.11. design example, though, addresses special design issues interfacing with AM79C930.
List Signals
Table summarizes signals that required control radio operations. first column lists signal name, second column indicates whether signal output input MAC, next column contains brief description each listed signal last columns indicate component part number connection each listed signals both ends.
RSSI ANTENNA CHANNEL FILTER
OPTIONAL RSSI INPUT
TX_RX SWITCH
HFA3624 CONVERSION
HFA3724 CONVERSION
HSP3824 DSSS BASEBAND PROCESSOR
ENGINE
CARD INTERFACE
HFA3925 POWER
HFA3524 DUAL SYNTHESIZER/VCO PA_PE
CONTROL TX_PE CONTROL RX_PE CONTROL
FIGURE PRISMCHIPSET SYSTEM BLOCK DIAGRAM
PRISMand PRISMlogo trademarks Harris Corporation. Copyright Harris Corporation 1997
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Application Note 9617
Summary List MAC-PHY Interface Signals
TABLE MAC-PHY INTERFACE SIGNALS FROM/ NUMBER AM79C930 (102) (101) (126) (142) (126) (142) (132) (141) (131) (121) (115) (91) (122) (95) (123) (124) (107) (105) (103) (101) (102) (96) (118) (131) MAC(92)
SIGNAL NAME SYNTH_DATA SYNTH_CLK SYNTH_LE RX_PE TX_PE RX_PE TX_PE SEL0 SEL1 TX_PE_BB TXCLK TX_RDY RX_PE_BB MD_RDY RXCLK SCLK SDATA RESET PA_PE OSC_START RADIO_PE
DESCRIPTION Serial Data (Synthesizer) Serial Control Clock (Synthesizer) Load Enable (Synthesizer) Receive Power Enable (RF/IF Converter) Transmit Power Enable (RF/IF Convt.) Receive Power Enable (Qmodem) Transmit Power Enable (Qmodem) Pass Filter Control (Qmodem) Pass Filter Control (Qmodem) Transmit Power Enable (transmit port) Transmit Data (Transmit Port) Transmit Clock (Transmit Port) Transmit Data Ready (Transmit Port) Receiver Power Enable (Receive Port) Data Ready (Receive Port) Receive Data (Receive Port) Receive Clock (Receive Port) Chip Select (Control Port) Address Strobe (Control Port) Read/write Strobe (Control Port) Serial Control Clock (Control Port) Bi-directional Serial Data (Cnt. Port) Clear Channel Assessment Master Reset Transmit Amplifier Power Enable (RFPA) Enable Circuit Radio Power Enable.
PART/PIN NUMBER HFA3524 (12) HFA3524 (11) HFA3524 (13) HFA3624 (28) HFA3624 (15) HFA3724 (21, HFA3724 (22, HFA3724 (17) HFA3724 (16) HSP3824 HSP3824 HSP3824 HSP3824 HSP3824 (33) HSP3824 (34) HSP3824 (35) HSP3824 (36) HSP3824 HSP3824 (23) HSP3824 HSP3824 (24) HSP3824 (25) HSP3824 (32) HSP3824 (28) HFA3925 (11,18, Startup Circuit RADIO
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Application Note 9617
Interface Signal Description
Table Consists functional description each signals that part HW/SW interface.
TABLE MAC-PHY INTERFACE SIGNALS SIGNAL NAME SYNTH_DATA SYNTH_CLK SYNTH_LE SIGNAL DESCRIPTION Binary serial data input used configure frequency synthesizer (HFA3524). Data entered first. single data transfer 22-bits wide. This high impedance CMOS input PHY. This clock SYNTH_DATA. data clocked appropriate synthesizer register rising edge SYNTH_CLK. This high impedance CMOS input PHY. Load enable frequency synthesizer (HFA3524). When signal goes active (High), data stored shift register loaded synthesizer operational registers defined control bits which LSBs SYNTH_DATA. Digital control input PHY. Selects four programmed frequencies both receive transmit channels analog baseband LPF. Tuning speed from cutoff another less than 1ms. IEEE802.11 8.8MHz cutoff frequency used. SEL1 SEL0 Cutoff Frequency SEL1 SEL0 Cutoff Frequency 2.2MHz 8.8MHz 4.4MHz 17.6MHz Transmit Channel Power Enable Control Input. compatible input. Enable logic level High. This signal controls several IF/RF components transmit chain. driving total inputs components HFA3634 HFA3724. Receive Channel Power Control Input. compatible input. Enable logic level High.This signal controls several IF/RF componets PHY. driving total inputs components HFA3624 HFA3724. TX_PE_BB input from Media Access Controller (MAC). rising edge TX_PE_BB will start internal transmit state machine digital modem falling edge will inhibit state machine. TX_PE velopes transmit data. input, used transfer serial Data Preamble/Header information bits from digital modem (HSP3824). data received serially with first. data clocked HSP3824 falling edge TXCLK. TXCLK clock output used receive data from digital modem (HSP3824), synchronously. Transmit data clocked into falling edge. When HSP3824 configured generate Preamble Header information internally, TX_RDY output external network processor indicating that Preamble Header information been generated that HSP3824 ready receive data packet from network processor over serial bus. TX_RDY returns inactive state when TX_PE goes inactive indicating data transmission. TX_RDY active high signal. This signal meaningful only when HSP3824 generates Preamble. Clear Channel Assessment (CCA) output used signal that channel clear transmit. algorithm user programmable makes decision function RSSI, Energy detect (ED), Carrier Sense (CRS) watch timer. algorithm programmable features described data sheet HSP3824 component. Logic Channel clear transmit. Logic Channel clear transmit (busy). NOTE: This polarity programmable inverted. output transferring demodulated Header information data serial format. data sent serially with first. data frame aligned with MD-RDY. RXCLK output clock MAC. This clock used transfer Header information data through serial MAC. This clock reflects rate use. RXCLK will held logic state during acquisition process PHY. RXCLK becomes active when enters data demodulation mode, mediately following signal acquisition. This occurs once sync declared valid signal quality estimate made, when comparing programmed signal quality thresholds. MD_RDY output signal MAC, indicating data packet ready transferred MAC. MD_RDY active high signal envelopes data transfer over serial bus. MD_RDY returns inactive state when there more receiver data, when programmable data length counter reaches value when link been interrupted. MD_RDY remains inactive during preamble synchronization. MD_RDY programmed become active after detection protocol after check field Header.
SEL0, SEL1
TX_PE
RX_PE TX_PE_BB
TXCLK TX_RDY
RXCLK
MD_RDY
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Application Note 9617
TABLE MAC-PHY INTERFACE SIGNALS (Continued) SIGNAL NAME RX_PE_BB SIGNAL DESCRIPTION When active, digital modem receiver configured operational, otherwise digital modem receiver (HSP3824) standby mode. This active high input signal. serial bi-directional data which used transfer address data to/from internal registers digital modem. ordering 8-bit word first. first 8-bits during transfers indicate register address immediately followed more bits representing data that needs written read from that register. SCLK clock serial digital modem. data clocked rising edge. SCLK input clock digital modem (HSP3824). maximum rate this clock 10MHz. address strobe used envelope Address data digital modem. This input signal digital modem (HSP3824) Logic envelopes address bits. Logic envelopes data bits. input digital modem (HSP3824) used change direction when reading writing data bus. must prior rising edge SCLK. high level indicates read while level write. chip select digital modem activate serial control port. This input signal PHY. doesn't impact other interface ports signals, i.e., ports interface signals. This active signal. When inactive SCLK, become "don't care" signals. Master reset digital modem (HSP3824). When active, functions disabled. RESET kept HSP3824 goes into power standby mode. RESET does alter configuration register values does preset registers into default values. device requires programming upon power-up. RESET either active inactive during programming device. Enable power amplifier (HFA3925) start transmission. This digital interface. Logic enables transmission. Enable Startup Circuit. going pulse ±10µs required activate after programming synthesizer. Enable power regulators clocks driving PHY. logic enables operation, logic puts complete power down mode.
SCLK
RESET
PA_PE OSC_START RADIO_PE
HW/SW Interfaces
There four primary HW/SW interfaces that used configuration during normal operation device. interfaces power initialization, transmit mode operation, receive mode operation power shut down mode. These interfaces summarized follows Initialization Control Interface, which used configure, write and/or read status physical layer digital modem synthesizer. This interface required configure programmable portions during power coming certain power down modes. This interface also used during operations real time reconfiguration parameters reading status. Interface, which used control transmit data transfers between physical layer. also used control devices transmit chain radio. Interface, which used control receive data transfers between physical layer. also used control devices receive chain radio. Power Down Interface, which used physical layer into three power savings modes.
INITIALIZATION CONTROL INTERFACE
This HW/SW interface used configure monitor programmable registers PHY. There devices that contain programmable registers: digital modem frequency synthesizer. This interface required configure radio upon power initialization monitor status during normal operation. This interface also used select switch frequency channel required transmit receive operations. Digital Modem Interface signals necessary accomplish functions this interface are: Chip select Address strobe R/W: Read Write strobe Serial Data. SCLK: Serial Data Clock. This HW/SW interface required configure digital modem registers performs read write operations from digital modem. serial control interface used serially write read data to/from digital
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Application Note 9617
modem. This serial interface operate 10MHz rate maximum sampling clock rate (whichever lower). sampling master clock physical layer designated MCLK must running during programming. This interface used program read internal registers. first 8-bits always represent address followed immediately data bits that register. serial transfers accomplished through serial data signal (SD). bi-directional serial data bus. Address Strobe (AS), Chip Select (CS), Read/Write (R/W) also required handshake signals this interface. clock used conjunction with address
CONTROL PORT READ TIMING
SCLK FIRST ADDRESS FIRST DATA
data SCLK. This clock provided PHY. timing relationships these signals illustrated Figure active high during clocking address bits. high when data read, when written. must active (low) during entire data transfer cycle. selects device. serial control interface operates asynchronously from interfaces accomplish data transfers independent activity other digital analog interfaces. does effect operation device; impacting only operation Control interface.
ADDRESS
DATA
CONTROL PORT WRITE TIMING
SCLK
ADDRESS
DATA
FIGURE DIGITAL MODEM CONTROL INTERFACE
Modem Configuration modem internal registers that configured through control interface. These registers listed Table below. table lists configuration register number, brief name describing register, address access each registers. type indi-
cates whether corresponding register Read only Read/Write (R/W). Some registers bytes wide indicated table (high bytes). Table indicates proper modem register configuration implement IEEE802.11 requirements JULY proposed draft.
TABLE CONFIGURATION CONTROL REGISTER LIST CONFIGURATION REGISTER REGISTER ADDRESS REGISTER DATA
NAME MODEM CONFIG. MODEM CONFIG. MODEM CONFIG. MODEM CONFIG. INTERNAL TEST REGISTER INTERNAL TEST REGISTER
TYPE
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Application Note 9617
TABLE CONFIGURATION CONTROL REGISTER LIST (Continued) CONFIGURATION REGISTER CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR19 CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR30 CR31 CR32 CR33 CR34 CR35 CR36 CR37 CR38 CR39 CR40 CR41 CR42 CR43 REGISTER ADDRESS REGISTER DATA
NAME INTERNAL TEST REGISTER MODEM STATUS REGISTER MODEM STATUS REGISTER DEFINITION REGISTER RSSI VALUE REGISTER ADC_CAL_POS REGISTER ADC_CAL_NEG REGISTER TX_SPREAD SEQUENCE (HIGH) TX_SPREAD SEQUENCE (LOW) SCRAMBLE_SEED SCRAMBLE_TAP CCA_TIMER_TH CCA_CYCLE_TH RSSI_TH RX_SPREAD SEQUENCE (HIGH) RX_SPREAD SEQUENCE (LOW) RX_SQ1_ACQ (HIGH) THRESHOLD RX_SQ1_ACQ (LOW) THRESHOLD RX_SQ1_ACQ (HIGH) READ RX_SQ1_ACQ (LOW) READ RX_SQ1_DATA (HIGH) THRESHOLD RX_SQ1_DATA (LOW) THRESHOLD RX_SQ1_DATA (HIGH) READ RX_SQ1_DATA (LOW) READ RX_SQ2_ACQ (HIGH) THRESHOLD RX_SQ2_ACQ (LOW) THRESHOLD RX_SQ2_ACQ (HIGH) READ RX_SQ2_ACQ (LOW) READ RX_SQ2_DATA (HIGH) THRESHOLD RX_SQ2_DATA (LOW) THRESHOLD RX_SQ2_DATA (HIGH) READ RX_SQ2_DATA (LOW) READ RX_SQ_READ FULL PROTOCOL RESERVED RESERVED UW_TIME_OUT_LENGTH SIG_DBPSK FIELD SIG_DQPSK FIELD
TYPE
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Application Note 9617
TABLE CONFIGURATION CONTROL REGISTER LIST (Continued) CONFIGURATION REGISTER CR44 CR45 CR46 CR47 CR48 CR49 CR50 CR51 CR52 CR53 CR54 CR55 CR56 RX_SER_FIELD RX_LEN FIELD (HIGH) RX_LEN FIELD (LOW) RX_CRC16 (HIGH) RX_CRC16 (LOW) (HIGH) (LOW) TX_SER_F TX_LEN (HIGH) TX_LEN (LOW) TX_CRC16 (HIGH) TX_CRC16 (LOW) TX_PREM_LEN REGISTER ADDRESS REGISTER DATA
NAME
TYPE
Synthesizer Interface following signals required accomplish functions this interface: Synth_Data: Serial Synthesizer Data Synth_Clk: Synthesizer Data Clock Synth_LE: Synthesizer Load Enable These signals utilized configure frequency synthesizer. synthesizer tunes radio appropriate receive transmit channels. Figure illustrates required timing write appropriate frequency synthesizer.
DATA
N20:MSB (R20:MSB)
(R19)
(R8)
(R7) (R6)
(R1)
CONTROL BIT:LSB CONTROL BIT:LSB
CLOCK
FIGURE SYNTHESIZER SERIAL DATA INTERFACE
following Data patterns required initialize synthesizer IEEE802.11 operation. should noted that register order important with first followed Also note that when powering coming Power Down Mode (see page 10). registers should written twice. This because device sections should enabled before configuring pairs; this effectively occurs values below written twice order. Also note that OSC_START signal must follow synthesizer programming cycle.
SYNTH_DATA SYNTH_DATA SYNTH_DATA SYNTH_DATA SYNTH_DATA SYNTH_DATA
16,1801h 16,4118h 6,04h 16,1801h 6,68h
Counter register initialization. Counter register initialization. Counter register initialization.
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Harris_Freq_Table holds 22-bit values synthesizer Counter control register. Each entry comprised three bytes. Eight bits first byte serially shifted synthesizer (MSBit first), followed 8-bits second byte (MSBit first), followed finally MSBits third byte (MSBit first). LSBits third byte each entry ignored. synthesizer configuration each IEEE802.11 channels shown below. Harris_Freq_Table label byte 02h, 011h, 04Ch 02h, 011h, 09Ch 02h, 011h, 0ECh 02h, 018h, 03Ch 02h, 018h, 08Ch 02h, 018h, 0DCh 02h, 019h, 02Ch 02h, 019h, 07Ch 02h, 019h, 0CCh 02h, 020h, 01Ch 02h, 020h, 06Ch 02h, 021h, 0CCh ;Channel ;Channel ;Channel ;Channel ;Channel ;Channel ;Channel ;Channel ;Channel ;Channel ;Channel ;Channel
INTERFACE
signals required control transmit functions radio are: TX_PE_BB: Transmit power enable digital modem TXD: Transmit digital data TXCLK: Transmit data clock TX_RDY: Transmit data ready TX_PE: Transmit power enable sections PA_PE: Power amplifier transmit enable 0,1: Selection appropriate baseband CCA: Clear channel assessment indicator from initiate transmit operation generates TX_PE. Preamble Header then generated PHY. Finally, when cued, delivers data packet transmission. transmit data digital interface transfers data that needs transmitted serially PHY. data modulated transmitted soon received from MAC. serial digital data input through using falling edge TXCLK clock PHY. TXCLK output from PHY. timing diagram transmit signal sequence shown Figure
TXCLK
TX_PE_BB PA_PE DON'T CARE DATA PACKET DUMMY BITS CLEAR PATH
TX_RDY
TX_PE PA_TR RX_PE_BB
RX_PE LOGIC LOGIC
SEL0 SEL1
MD_RDY LOGIC RESET RADIO_PE
FIGURE TRANSMIT TIMING DIAGRAM
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Application Note 9617
preamble header transmission always 1Mbps (BPSK) data rate. header data that follows either 1Mbps (BPSK) 2Mbps (QPSK). avoid rate switching within single transmission between MAC-PHY interface, TXCLK will always higher rate 2Mbps. This implies that each BPSK symbols needs coming into twice. needs send same BPSK symbol twice rate 2Mbps this action will make equivalent required BPSK symbol rate 1Mbps. QPSK data bits follow header, they will sent from only once 2Mbps rate. initiates transmit sequence asserting TX_PE. Then TX_PE_BB envelopes transmit data packet TXD. responds generating TXCLK input serial data TXD. TXCLK will until TX_PE_BB goes back inactive state indicating data packet. addition Figure illustrates state receive signals while transmitting well power enable, reset, filter select proper signal states. supports possible data transfer scenarios, where preamble header fields generated within where generates preamble header fields. scenario described herein assumes that generates preamble header. During this mode will immediately start transmitting preamble header internally generated. Data available upon assertion TX_PE_BB would ignored. When internally generated preamble header finished asserts TX_RDY. This signals begin sending data packet. TX_RDY assertion timing programmable Configuration Register (CR) timing diagram this scenario, where preamble header generated internal PHY, illustrated Figure other signal that used assist transmit decisions part interface Clear Channel Assessment (CCA) signal which output from PHY. provides indication that channel clear energy transmission will subject collisions. monitored assist deciding when initiate transmissions. indication bypassed ignored without impacting physical layer operations. state does effect transmit operation PHY. TX_PE TX_PE_BB will always initiate transmit state independent state CCA. timing shown timing diagram Figure since optional signal does influence transmit operations. Signals TX_RDY, TX_PE_BB TXCLK individually, programming CR9, either active high active signals. avoid increasing throughput delays critical that timing TX_PE RX_PE close complementary each other possible. When first attempting transmit upon power-up, PA_PE must stay least 10ms after RADIO_PE goes high.
INTERFACE
signals that control receive functions radio are: RX_PE_BB: Receive power enable digital modem MD_RDY: data ready, enveloping data packet from RXD: Receive serial baseband data RXCLK: Receive data clock RX_PE: Receive power enable section radio 0,1: Receive frequency select Timing diagram, Figure illustrates relationships between various signals required control during receive operations. receive data interface digital modem (RXD) serially outputs demodulated data MAC. data output soon demodulated PHY. RX_PE RX_PE_BB must their active state throughout receive operation. When RX_PE, RX_PE_BB inactive receive functions, including acquisition,. will stand mode. timing relationships between RX_PE RX_PE_BB, well state transmit signals, power enable signals, reset filter select signal states illustrated Figure receive operation during reception single packet. RXCLK output from clock serial demodulated data RXD. MD_RDY output from envelopes valid data RXD. MD_RDY programmable asserted either after Start Frame Delimiter field been detected immediately after field header been checked. MD_RDY programmed through CR3, bit-7 select when will asserted. also programmed ignore error detection during check header fields. programmed ignore errors device continues output demodulated data entirety regardless check result. This option programmed through CR2, bit-5. preamble header always received 1Mbps (BPSK) data rate. header data that follows either Mbps (BPSK) Mbps (QPSK). avoid rate switching within single packet reception between MAC-PHY interface, RXCLK will always higher rate Mbps. This implies that each BPSK symbols coming twice. sends same BPSK symbol twice rate Mbps this action will make equivalent required BPSK symbol rate 1Mbps. QPSK data bits follow header, they will sent from only once Mbps rate. rate switching issue controller (MAC) then HSP3824 configured rate switch within packet. HSP3824 automatically switch from BPSK QPSK rate appropriate time.
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Application Note 9617
Note that RXCLK become active after acquisition, well before MD_RDY asserted. MD_RDY returns inactive state under following conditions: number data symbols, defined length field protocol, been received output through entirety (normal condition). tracking lost during demodulation. RX_PE_BB deactivated MAC. MD_RDY configured through CR9, bit-6 active low, active high. avoid increasing throughput delays critical that timing TX_PE RX_PE close complementary each other possible.
RXCLK
RX_PE PROCESSING PREAMBLE/HEADER
MD_RDY
DATA
RX_PE_BB TX_PE PA_TR TX_PE_BB PA_PE LOGIC SEL0 LOGIC SEL1 LOGIC RESET RADIO_PE
FIGURE RECEIVE TIMING DIAGRAM
POWER DOWN MODES
power consumption modes controlled following control signals: Receiver Power Enable (RX_PE RX_PE_BB), which disable radio receiver when inactive. Transmitter Power Enable (TX_PE TX_PE_BB PA_PE), which disable radio transmitter when inactive. Reset (RESET), which puts digital receiver sleep mode when asserted least MCLK's after RX_PE inactive state. RADIO_PE, which disables power regulators digital clocks PHY. addition radio synthesizer programmable maximum power savings mode. Utilizing availability signals above there three power savings modes defined:
Power Down mode During this mode current consumption radio estimated 38mA. radio receive transmit when configured this mode. When this mode, takes 25µs. return radio operational mode. when this mode, maintains configuration data. There need reprogram radio register values. activate Power Down mode following signals need states shown below: RX_PE: RX_PE_BB: TX_PE: TX_PE_BB: PA_PE: RESET: RADIO_PE: HIGH
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Application Note 9617
Power Down mode During this mode current consumption radio estimated 23mA. radio cannot receive transmit when configured this mode. When this mode, takes 2ms. return radio operational mode. During this mode synthesizer programmed into power savings mode. When this mode, maintains configuration data. There need reprogram radio register values. However, Synthesizer needs reprogrammed according Synthesizer Interface Section page activate Power Down mode following signals need shown below: RX_PE: RX_PE_BB: TX_PE: TX_PE_BB: PA_PE: RESET: RADIO_PE: HIGH addition Synthesizer needs programmed synthesizer configuration interface shown below: SYNTH_DATA 16,1801h SYNTH_DATA 6,0h SYNTH_DATA 16,0C118h SYNTH_DATA 6,04h Counter register initialization. Counter register initialization. SYNTH_DATA 16,1801h SYNTH_DATA 6,68h SYNTH_DATA 16,8211h SYNTH_DATA 6,4Ch Counter register initialization. Counter register initialization.
Power Down mode During this mode current consumption radio estimated 1ma. radio receive transmit when configured this mode. When this mode, takes 15ms. return radio operational mode. When this mode, does maintain register configuration. radio register values need reprogrammed resume operation. This holds both digital modem (HSP3824) frequency synthesizer (HFA3925). activate Power Down mode following signals need shown below: RX_PE: Don't Care RX_PE_BB: TX_PE: Don't Care TX_PE_BB: PA_PE: RESET: RADIO_PE: When first attempting transmit upon power-up, PA_PE must stay least 10ms after RADIO_PE goes high.
Appendix
Control Register Values Single Antenna Acquisition
REGISTER ADDRESS
REGISTER CR10 CR11 CR12
NAME MODEM CONFIG. MODEM CONFIG. REG#2 MODEM CONFIG. REG#3 MODEM CONFIG. REG#4 INTERNAL TEST REGISTER#1 INTERNAL TEST REGISTER INTERNAL TEST REGISTER#3 MODEM STATUS REGISTER MODEM STATUS REGISTER DEFINITION REGISTER RSSI VALUESTATUS REGISTER ADC_CAL_POS REGISTER ADC_CAL_NEG REGISTER
TYPE
QPSK
BPSK
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Application Note 9617 Appendix
Control Register Values Single Antenna Acquisition
(Continued) REGISTER ADDRESS
REGISTER CR13 CR14 CR15 CR16 CR17 CR18 CR19 CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR30 CR31 CR32 CR33 CR34 CR35 CR36 CR37 CR38 CR39 CR40 CR41
NAME TX_SPREAD SEQUENCE (HIGH) TX_SPREAD SEQUENCE (LOW) SCRAMBLE_SEED SCRAMBLE_TAP CCA_TIMER_TH CCA_CYCLE_TH RSSI_TH RX_SPREAD SEQUENCE (HIGH) RX_SREAD SEQUENCE (LOW) RX_SQ1_ IN_ACQ(HIGH) THRESHOLD RX-SQ1_ IN_ACQ(LOW) THRESHOLD RX-SQ1_ OUT_ACQ(HIGH) READ RX-SQ1_ OUT_ACQ (LOW) READ RX-SQ1_ IN_DATA (HIGH) THRESHOLD RX-SQ1-SQ1_ IN_DATA (LOW) THRESHOLD RX-SQ1_ OUT_DATA (HIGH) READ RX-SQ1_ OUT_DATA (LOW) READ RX-SQ2_ IN_ACQ (HIGH) THRESHOLD RX-SQ2- IN-ACQ (LOW) THRESHOLD RX-SQ2_ OUT_ACQ (HIGH) READ RX-SQ2_ OUT_ACQ (LOW) READ RX-SQ2_IN_DATA (HIGH) THRESHOLD RX-SQ2_ IN_DATA (LOW) THRESHOLD RX-SQ2_ OUT_DATA (HIGH) READ RX-SQ2_ OUT_DATA (LOW) READ RX_SQ_READ; FULL PROTOCOL80211 RESERVED RESERVED UW_TIME_OUT_LENGTH
TYPE
QPSK
BPSK
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Application Note 9617 Appendix
Control Register Values Single Antenna Acquisition
(Continued) REGISTER ADDRESS
REGISTER CR42 CR43 CR44 CR45 CR46 CR47 CR48 CR49 CR50 CR51 CR52 CR53 CR54 CR55 CR56 SIG_DBPSK Field SIG_DQPSK Field RX_SER_Field RX_LEN Field (HIGH) RX_LEN Field (LOW) RX_CRC16 (HIGH) RX_CRC16 (LOW) -(HIGH) _(LOW) TX_SER_F TX_LEN (HIGH) TX_LEN(LOW) TX_CRC16 (HIGH) TX_CRC16 (LOW) TX_PREM_LEN
NAME
TYPE
QPSK
BPSK
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Harris Wireless Products Hardware/Software Interface Description

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