Harris Wireless Products Programming HSP3824 Author: John Fa

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Harris Wireless Products Programming HSP3824 Author: John Fa

Datasheet Thumbnail

Top Searches for this datasheet

AN9616
Harris Wireless Products
Programming HSP3824
Author: John Fakatselis
Introduction
Test Port Configuration These configuration registers include configuration selection internal HSP3824 signals and/or data become available Test Port pins. These signals useful during debugging, regulatory compliance testing well design enhanced external algorithms improve overall radio performance. Threshold Settings These configuration registers include number configurable threshold settings. They cover, Received Signal Strength Indication Clear Channel Assessment threshold parameters, well received signal quality thresholds used during acquisition data tracking. setting these acquisition tracking thresholds, user define desired modem performance i.e. probability detection probability false alarm ratio. Calibration These configuration registers include configuration data activate level adjustment circuit HSP3824. This circuit designed maximize utilization dynamic range. This programmable circuit tries keep A/Ds close saturation. Modem Status These configuration registers include information that represent both control status registers (read-only). status components indicate real time state modem operation. Signal Status These configuration registers include information that represent modem parameter (read-only) registers. These modem status components updated real time. They used design external algorithms improve overall modem performance. addition this registers provide information link protocol (header) that presently use.
This application note serves firmware designers manual PRISMHSP3824 baseband processor. note groups programmable registers their content function. This note serve quick reference code development system test modification function.
Overview
HSP3824 offers flexibility various system configurations through programmable features. Among other user many options control synchronization time, link protocol formats, data rates, performance thresholds, visibility internal modem parameters status. Preamble/Header These configuration registers include preamble generation, transmit header modes receive header modes. Preamble header either generated internally from HSP3824 received from external source i.e. network processor. Modem Configuration These configuration registers include configuration transmitter receiver modem. transmit receive symbol rates, scrambler configuration, code configuration antenna selection also programmed through these registers. Configuration These configuration registers include configuration active signal levels (polarity) HSP3824 signals other miscellaneous signal parameters. This provide flexibility minimize glue logic external circuits there signal polarity issue.
PRISMand PRISMlogo trademarks Harris Corporation. Copyright Harris Corporation 1996
7-66
Application Note 9616 Description Configuration Register Assignments Function.
following paragraphs describe configuration register (CR) content programmable HSP3824 registers. bits within that define particular function data also indicated. description references below broken primary HSP3824 programmable functional groups which are: Preamble/ header. Modem configuration configuration Test Port configuration Threshold settings calibration Modem status Signal status This serve quick reference program modify registers function. Refer also HSP3824 data sheet description hardware algorithms appropriate sections. example default also attached this note. Start Frame Delimiter Value CR41<7:0> This control register contains number symbol periods demodulator search receive header before returning acquisition mode. Data Field Counter Enable CR0<1:1> This control used enable/disable counting number data bits length field embedded header. HSP3824 returns acquisition mode count defined "Length" field header. This only used header modes Check Enable CR2<5:5> This control used enable/disable CRC16 check received Header. Start Frame Delimiter Definition CR49<7:0> CR50<7:0> These control registers contain Start Frame Delimiter used both Transmit Receive header. This field address field each individual receiver within network. Start Frame Delimiter Timer Enable CR0<2:2> This control used enable Start Frame Delimiter timer. timer expires before been detected, HSP3824 returns acquisition mode. search time defined start frame delimiter value registers.
Preamble/Header
Preamble Generation CR3<2:2> This control used select origination Preamble/Header information. preamble header either generated internally HSP3824 from external source. Transmit Mode CR0<4:3> These control bits used select four Preamble Header modes transmitting data. four modes contain different combinations fields. CR0<4:3> Header Contents SFD, field CRC16, fields SFD, Length CRC16, fields SFD, Signal, Length CRC16, fields
Modem Configuration
TRANSMIT CONFIGURATION
Chips Symbol CR3<6:5> These control bits used select number chips symbol used transmit paths. CR3<6:5> Chips/Symbol
Rate Divisor CR3<4:3> These control bits used select divide ratio required achieve required data rate (refer HSP3824 data sheet). CR3<4:3> Divisor
Receive Mode CR2<1:0> These control bits used select four Preamble Header modes receiving data. CR2<1:0> Header Contents CRC16 SFD, Length CRC16 SFD, Signal, Length CRC16
Antenna Select CR0<7:7> This control used select transmit antenna (halfduplex mode only). Modulation CR3<1:1> This control used select signal modulation type transmit packet. Spread Sequence CR13<7:0> CR14<7:0> These control registers contain spreading code transmit paths.
Transmit Preamble Length CR56<7:0> This control register defines Preamble length field value.
7-67
Application Note 9616
RECEIVE CONFIGURATION
Chips Symbol CR2<7:6> These control bits used select number chips symbol used receive paths. CR2<7:6> Chips/Symbol These control bits used define number clocks before first data that TX_RDY will asserted.
ACTIVE SIGNAL LEVELS
These components allow user invert sense certain signals available pins HSP3824. Data Ready (MD_RDY) CR9<6:6> This control used select active level MD_RDY signal. Clear Channel Assessment (CCA) CR9<5:5> This control used select active level signal. Energy Detect (ED) CR9<4:4> This control used select active level signal. Carrier Sense (CRS) CR9<3:3> This control used select active level signal. Transmit Data Ready (TX_RDY) CR9<2:2> This control used select active level TX_RDY signal. Transmit Power Enable (TX_PE) CR9<1:1> This control used select active level TX_PE signal.
Rate Divisor CR2<4:3> These control bits used select divide ratio required desired receive data rate. CR2<4:3> Divisor
Antenna Select CR0<6:6> This control used select receive antenna (single antenna mode only). Modulation CR3<0:0> This control used select signal modulation type receive packet. Spread Sequence CR20<7:0> CR21<7:0> These control registers contain despreading code receive paths. Scrambler Taps CR16<6:0> This control register contains configuration transmit scrambler receive descrambler. Scrambler Seed CR15<6:0> This control register contains seed value transmit scrambler receive descrambler. Antenna Operation CR0<5:5> This control used select between full duplex half duplex operation. Antenna Mode CR2<2:2> This control used select single dual antenna mode.
Test Port Configuration
Test Mode CR4<7:0> HSP3824 provides capability access number internal signals and/or data through test port pins TEST TEST_CLK. TEST_CLK selected given data that clocked from TEST port. TX_CLK intended used clock TEST data from HSP3824. Normal Operation Mode <7:7> Carrier Sense (CRS) <6:6> Energy Detect (ED) <5:3> Reserved <2:2> Initial Detect <1:0> Reserved TEST_CLK Internal Clock chip rate) Correlator Test Mode <7:0> Correlator Magnitude correlator) TEST_CLK Internal Clock chip rate) Frequency Test Mode <7:0> Frequency offset Register TEST_CLK Subsample Clock symbol rate)
Configuration
Allow Microprocessor Rate Change CR1<7:7> This control used enable/disable constant data rates external processor that receives demodulated data from HSP3824. Rate changes from DBPSK DQPSK within same packet programmed transparent external processor. Invert Transmit Clock Phase CR9<0:0> This control used select phase transmit output clock. Assert TX_RDY Clock Count CR1<6:2>
7-68
Application Note 9616
Phase Test Mode <7:0> Phase (instantenous I,Q) TEST_CLK Subsample Clock symbol rate) Test Mode <7:0> Phase Accum Register most significant bits) TEST_CLK Subsample Clock symbol rate) Test Mode <7:0> Signal Quality (SQ) Phase Variance most significant bits) TEST_CLK Load Signal Quality Signal Sync Test Mode <7:0> Sync Accum TEST_CLK Internal Clock Sync Test Mode <7:0> Sync Reference Data most significant bits) TEST_CLK Load Signal Test Mode <7:7> Carrier Sense (CRS) <6:6> Energy Detect (ED) <5:5> Reserved <4:0> Calibrate TEST_CLK (Internal Clock) signal must above this programmable value declared valid. Receive Phase Variance (Acquisition/Data) CR30<7:0> CR31<7:0> These control registers used specify phase variance quality threshold used acquisition data. typical values HSP3824 data sheet. received signals phase variance less than this programmable value declared valid signal.
Calibration
Reference Value CR1<1:1> This control used select whether internal calibration circuit active not, sets reference mid-scale. Last Value CR1<0:0> This control used select whether internal calibration circuit held most recent value. Positive Increment Adjust CR11<7:0> This control register contains value used positive increments level adjusting circuit reference. These positive increment steps define fast will driven saturation. Negative Increment Adjust CR12<7:0> This control register contains value used negative increments level-adjusting circuit reference. These negative increments define back step size from when reaches saturation.
Threshold Settings
Received Signal Strength Indication (RSSI) CR19<5:0> These control bits used specify RSSI threshold measuring generating energy detect (ED) signal. When RSSI exceeds this threshold, declared. Clear Channel Assessment Timer CR17<7:0> This control register used configure period time-out threshold watchdog timer. Clear Channel Assessment Cycle CR18<7:0> This control register used configure many times timer allowed reach maximum count before declares that channel clear (independent actual energy measured channel). Enable CR5<6:6> Chip Adjust During Acquisition/Data
Modem Status
Transmit Ready (TX_RDY) CR7<7:7> This status indicates status TX_RDY output pin. only used when Preamble/Header generated internally within HSP3824. Antenna CR7<6:6> This status indicates antenna selected device (status ANTSEL pin) during antenna diversity. Clear Channel Assessment (CCA) CR7<5:5> This status indicates status Clear Channel Assessment output pin. Carrier Sense (CRS) CR7<4:4> This status indicates status Carrier Sense lock). RSSI Threshold CR7<3:3> This status indicates whether RSSI signal above below threshold energy detect (ED)).
This control used enable/disable chip timing adjustments during acquisition data. default chip adjustments. Receive Synch CR22<7:0> CR23<7:0> Amplitude (Acquisition/Data)
These control registers used specify synch amplitude quality threshold used acquisition data. typical values HSP3824 data sheet.The received
7-69
Application Note 9616
Data Ready (MD_RDY) CR7<2:2> This status indicates status MD_RDY output pin. signals that valid Preamble/Header been received that next available will first data packet bit. Transmit Power Enable (TX_PE) CR7<1:1> This status indicates whether external device acknowledged that channel clear transmission status TX_PE pin). Valid CRC16 CR7<0:0> This status indicates whether valid CRC16 been calculated Header information. CRC16 does cover preamble bits data packet. Packet Status CR8<7:7> This status indicates whether valid packet been received. This meaningful only when device operates under full protocol (mode Start Frame Delimiter Search Timer CR8<6:6> This status indicates status search timer. Phase Variance Acquisition CR32<7:0> CR33<7:0> Modulation Type CR8<5:5> This status indicates modulation type data packet. Preamble Header data always 1MBPS. These status registers contain measured phase variance signal quality during acquisition. Phase Variance Data CR36<7:0> CR37<7:0> CRC16 Field CR47<7:0> CR48<7:0> These status registers indicate received CRC16 received header.
SIGNAL FIELD
BPSK CR42<7:0> This control register contains 8-bit value indicating that data packet modulation DBPSK. QPSK CR43<7:0> This control register contains 8-bit value indicating that data packet modulation DQPSK.
RECEIVE SIGNAL QUALITY INDICATORS
Synch Amplitude Acquisition CR24<6:0> CR25<7:0> These status registers contain measured synch amplitude signal quality during acquisition. Synch Amplitude Data CR28<6:0> CR29<7:0> These status registers contain measured synch amplitude signal quality during data tracking.
Signal Status
TRANSMIT PREAMBLE INFORMATION
Service Field CR51<7:0> This control register contains value service field transmitted Header. Length Field CR52<7:0> CR53<7:0> These control registers contain value length field transmitted. indicates number bits transmitted data packet. CRC16 Field CR54<7:0> CR55<7:0> These status registers indicate calculated CRC16 transmitted header.
These status registers contain measured phase variance signal quality during data tracking. RSSI Value CR10<5:0> These status bits contain value RSSI analog input signal from on-chip ADC. This register updated chip rate divided Receive Signal CR38<7:0> Quality Best Antenna Dwell
This status register contains synch amplitude signal quality measurement derived from Synch signal quality stored CR28-29 registers HSP3824. This value result signal quality measurement best antenna dwell antenna diversity mode. DEFAULT CONFIGURATION Table contains default configuration values that used QPSK BPJK modulation. These values initially used systems test then modified appropriate, each application. default configuration table followed detail description available registers HSP3824.
RECEIVE PREAMBLE INFORMATION
Service Field CR44<7:0> This status register contains value service field received Header. Length Field CR45<7:0> CR46<7:0> These status registers contain value length field received packet. indicates number bits transmitted data packet.
7-70
Application Note 9616
TABLE CONTROL REGISTER VALUES SINGLE ANTENNA ACQUISITION ADDR
REGISTER CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR19 CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR30
NAME MODEM CONFIG. MODEM CONFIG. MODEM CONFIG. MODEM CONFIG. INTERNAL TEST REGISTER INTERNAL TEST REGISTER INTERNAL TEST REGISTER MODEM STATUS REGISTER MODEM STATUS REGISTER DEFINITION REGISTER RSSI VALUESTATUS REGISTER ADC_CAL_POS REGISTER ADC_CAL_NEG REGISTER TX_SPREAD SEQUENCE(HIGH) TX_SPREAD SEQUENCE (LOW) SCRAMBLE_SEED SCRAMBLE_TAP CCA_TIMER_TH CCA_CYCLE_TH RSSI_TH RX_SPREAD SEQUENCE (HIGH) RX_SREAD SEQUENCE (LOW) RX_SQ1_ IN_ACQ (HIGH) THRESHOLD RX-SQ1_ IN_ACQ (LOW) THRESHOLD RX-SQ1_ OUT_ACQ (HIGH) READ RX-SQ1_ OUT_ACQ (LOW) READ RX-SQ1_ IN_DATA (HIGH) THRESHOLD RX-SQ1-SQ1_ IN_DATA (LOW) THRESHOLD RX-SQ1_ OUT_DATA (HIGH)READ RX-SQ1_ OUT_DATA (LOW) READ RX-SQ2_ IN_ACQ (HIGH) THRESHOLD
TYPE
QPSK
BPSK
7-71
Application Note 9616
TABLE CONTROL REGISTER VALUES SINGLE ANTENNA ACQUISITION (Continued) ADDR
REGISTER CR31 CR32 CR33 CR34 CR35 CR36 CR37 CR38 CR39 CR40 CR41 CR42 CR43 CR44 CR45 CR46 CR47 CR48 CR49 CR50 CR51 CR52 CR53 CR54 CR55 CR56
NAME RX-SQ2- IN-ACQ (LOW) THRESHOLD RX-SQ2_ OUT_ACQ (HIGH) READ RX-SQ2_ OUT_ACQ (LOW) READ RX-SQ2_IN_DATA (HIGH)THRESHOLD RX-SQ2_ IN_DATA (LOW) THRESHOLD RX-SQ2_ OUT_DATA (HIGH) READ RX-SQ2_ OUT_DATA (LOW) READ RX_SQ_READ; FULL PROTOCOL RESERVED RESERVED UW_Time Out_LENGTH SIG_DBPSK Field SIG_DQPSK Field RX_SER_Field RX_LEN Field (HIGH) RX_LEN Field (LOW) RX_CRC16 (HIGH) RX_CRC16 (LOW) -(HIGH) _(LOW) TX_SER_F TX_LEN (HIGH) TX_LEN(LOW) TX_CRC16 (HIGH) TX_CRC16 (LOW) TX_PREM_LEN
TYPE
QPSK
BPSK
7-72
Application Note 9616 Control Registers, Address Location Specification
following tables describe function each control register along with associated bits each control register.
CONFIGURATION REGISTER ADDRESS (0h) MODEM CONFIGURATION REGISTER This selects transmit antenna, controlling output ANT_SEL pin. only used half duplex mode. (Bit Logic Antenna Logic Antenna single antenna operation this used output ANT_SEL pin. dual antenna mode this ignored. Logic Antenna Logic Antenna This control used select between full duplex half duplex operation. full duplex operation, ANT_SEL reflects setting when TX_PE active reflects receiver's choice when TX_PE inactive. full duplex operation, ANT_SEL always reflects receiver's choice antenna. Logic full duplex. Logic half duplex. These control bits used select four input Preamble Header modes transmitting data. preamble header DBPSK modes operation. Mode followed DBPSK data. modes 1-3, data configured either DBPSK DQPSK. This "don't care" header generated externally. MODE MODE DESCRIPTION Preamble with Field. Preamble with SFD, CRC16. Preamble with SFD, Length, CRC16. Full preamble header.
This control used enable (Start Frame Delimiter) timer. time expires before been detected, HSP3824 will return acquisition mode. Logic Enables timer start counting once acquisition been achieved. Logic Disables Timer. This control enables counting number data bits length field embedded header. Only used header modes Then according count returns processor into acquisition mode count. length field 0000h, modem will reset regardless this setting. Logic Enable Length Time Out. Logic Disabled. Unused don't care. CONFIGURATION REGISTER ADDRESS (04h) MODEM CONFIGURATION REGISTER
When active this maintains RXCLK TXLK rates constant preamble data transfers even data modulated DQPSK. This used external processor accommodate rate changes. This active high signal. rate used QPSK rate BPSK header bits double clocked. These control bits used define binary count from This count used assert TX_RDY clocks (TXCLK) before beginning first data bit. this zero, then TX_RDY will asserted immediately after last Preamble Header. When active internal calibration circuit sets reference mid-scale. When inactive then calibration circuit adjusts reference voltage real time optimize levels. Logic Reference mid-scale (fixed). Logic Real time reference adjustment. When active calibration circuit held last value. Logic Reference held most recent value. Logic Real time reference level adjustment.
7-73
Application Note 9616
CONFIGURATION REGISTER ADDRESS (08h) MODEM CONFIGURATION REGISTER These control bits used select number chips symbol used paths receiver matched filter correlators (see table below).
CHIPS SYMBOL
This control used disable CRC16 check. When this set, processor will accept received packet packet error checks have detected externally. HSP3824 will remain receive mode until either carrier lost network processor resets device acquisition mode, modes length times out. Logic Disable receiver error checks. Logic Enable receiver checks. These control bits used select divide ratio demodulators receive chip clock timing.The value determined following equation: Symbol Rate MCLK/(N Chips symbol).
MASTER CLOCK/N
This control sets receiver into single dual antenna mode. Preamble acquisition processing length whether modem scans antennas controlled this bit. single antenna mode, ANT_SEL reflects otherwise reflects receiver's choice antenna. Logic Acquisition processing dual antenna acquisition. Logic Acquisition processing single antenna acquisition. These control bits used indicate four Preamble Header modes receiving data. Each modes includes different combinations Header fields. Users choose mode with fields that more appropriate their networking requirements. Header fields that combined form various modes are: field CRC16 field Data length field (indicates number data bits that follow Header information) Full protocol Header INPUT MODE RECEIVE PREAMBLE HEADER FIELDS Preamble, with Field Preamble, with SFD, CRC16 Preamble, with Length, CRC16 Preamble, with Full Protocol Header
7-74
Application Note 9616
CONFIGURATION REGISTER ADDRESS (0Ch) MODEM CONFIGURATION REGISTER Reserved (must "0"). These control bits combined used select number chips symbol used transmit paths (see table below). CHIPS
These control bits used select divide ratio transmit chip clock timing. NOTE: value determined following equation: Symbol Rate MCLK/(N Chips symbol) MASTER
This control used select origination Preamble/Header information. Logic HSP3824 generates Preamble Header internally formatting programmed header information generating TX_RDY indicate beginning data packet. Logic Accepts Preamble/Header information from externally generated source. This control used indicate signal modulation type transmitted data packet. When configured mode header, mode external header, this ignored. Register bits Logic DBPSK modulation data packet. Logic DQPSK modulation data packet. This control used indicate signal modulation type received data packet Used only with header modes register 2-bits Logic DBPSK. Logic DQPSK. CONFIGURATION REGISTER ADDRESS (10h) INTERNAL TEST REGISTER
These control bits used direct various internal signals test port output pins. These internal signals monitored fault isolate device manufacturing testing. During normal operation, value recommended. This will result following signals becoming available output test pins device: (TEST7): Carrier Sense (CRS), Logic indicates lock. (TEST6): Energy Detect (ED), Logic indicates that there energy detected channel. goes active when RSSI exceeds threshold level programmed user. (TEST_CK): clock. CONFIGURATION REGISTER ADDRESS (14h,18h) INTERNAL TEST REGISTER
Bits
These bits need programmed They used manufacturing test only. CONFIGURATION REGISTER ADDRESS (1Ch) MODEM STATUS REGISTER
This indicates status TX_RDY output pin. TX_RDY used only when HSP3824 generates Preamble/Header data internally. Logic Indicates that HSP3824 completed transmitting Preamble header information ready accept data from external source (i.e. MAC) transmit. Logic Indicates that HSP3824 process transmitting Preamble Header information. This status indicates antenna selected device. Logic Antenna selected. Logic Antenna selected.
7-75
Application Note 9616
CONFIGURATION REGISTER ADDRESS (1Ch) MODEM STATUS REGISTER (Continued) This status indicates present state clear channel assessment (CCA) which output being asserted result channel energy monitoring algorithm that function RSSI, carrier sense, time counters that monitor channel activity. This status bit, when active indicates Carrier Sense, lock. Logic Carrier present. Logic Carrier Sense. This status indicates whether RSSI signal above below programmed RSSI 6-bit threshold setting. This signal referred Energy Detect (ED). Logic RSSI above programmed threshold setting. Logic RSSI below programmed threshold setting. This indicates status output control MD_RDY (pin 34). signals that valid Preamble/Header been received that next available will first data packet bit. Logic Envelopes data packet becomes available (TXD). Logic data packet serial bus. This status indicates whether external device acknowledged that channel clear transmission. This same input signal TX_PE Logic Acknowledgment that channel clear transmit. Logic Channel clear transmit. This status indicates that valid CRC16 been calculated. CRC16 calculated Header information. CRC16 does cover preamble bits. Logic Valid CRC16 check. Logic Invalid CRC16 check. CONFIGURATION REGISTER ADDRESS (20h) MODEM STATUS REGISTER This status meaningful only when device operates under full protocol mode. Errors imply errors header fields. Logic Valid packet received. Logic Errors received packet. This used indicate status search timer. device monitors incoming Header SFD. timer, times HSP3824 returns signal acquisition mode looking detect next Preamble Header. Logic found, return signal acquisition mode. Logic time during search. This status used indicate modulation type data packet. This signal generated header detection circuitry receive interface. Logic DBPSK. Logic DQPSK. Unused, don't care. Unused, don't care. Unused, don't care. Unused, don't care. Unused, don't care. CONFIGURATION REGISTER ADDRESS (24h) DEFINITION REGISTER This register used define phase clocks other interface signals. This needs always logic This control selects active level MD_RDY output Logic MD_RDY active Logic MD_RDY active
7-76
Application Note 9616
CONFIGURATION REGISTER ADDRESS (24h) DEFINITION REGISTER This control selects active level Clear Channel Assessment (CCA) output Logic active Logic active This control selects active level Energy Detect (ED) output which output test port, Logic active Logic active This control selects active level Carrier Sense (CRS) output which output test port, Logic active Logic active This control selects active level transmit ready (TX_RDY) output Logic TX_RDY active Logic TX_RDY active This control selects active level transmit enable (TX_PE) input Logic TX_PE active Logic TX_PE active This control selects phase transmit output clock (TXCLK) Logic Inverted TXCLK. Logic NON-Inverted TXCLK CONFIGURATION REGISTER ADDRESS (28h) RSSI VALUE REGISTER Bits This read only register reporting value RSSI analog input signal from chip 6-bit ADC. This register updated (chip rate/11). Bits used Logic Example: BITS (0:7) RSSI_STAT 76543210 00000000 00111111 (Min) (Max) RANGE
CONFIGURATION REGISTER ADDRESS (2ch) REGISTER Bits This 8-bit control register contains binary value used positive increment level adjusting circuit reference. larger step faster level reaches saturation. CONFIGURATION REGISTER ADDRESS (30h) REGISTER Bits This 8-bit control register contains binary value used negative increment level adjusting reference A/D. number programmed value wanted since negative number. CONFIGURATION REGISTER ADDRESS (34h) SPREAD SEQUENCE (HIGH) Bits This 8-bit register programmed with upper byte transmit spreading code. This code used both signalling paths transmitter. This register combined with lower byte TX_SPREAD(LOW) generates transmit spreading code programmable 16-bits. Code lengths permitted Right justified first.
7-77
Application Note 9616
CONFIGURATION REGISTER ADDRESS (38h) SPREAD SEQUENCE (LOW) Bits This 8-bit register programmed with lower byte transmit spreading code. This code used signalling paths transmitter. This register combined with higher byte TX_SPREAD(HIGH) generates transmit spreading code programmable 16-bits. example below illustrates positioning 11-bit Barker codes. Example: Transmit Spreading Code 11-Bit Barker Word Right Justified First. TX_SPREAD(HIGH) TX_SPREAD(LOW) 11-bit Barker code
CONFIGURATION REGISTER ADDRESS (3Ch) SCRAMBLER SEED Bits This register contains 7-bit (seed) value transmit scrambler which used preset transmit scrambler known starting state. position unused must programmed Logic example below illustrates positioning seed. CONFIGURATION REGISTER ADDRESS (40h) SCRAMBLER Bits This register used configure transmit scrambler with 7-bit polynomial configuration. transmit scrambler 7-bit shift register, with configurable taps. logic respective position enables that particular tap. used Logic example below illustrates register configuration polynomial F(x) X-4+X-7. Each clock shift left Bits (0:7) 76543210 XZ-7Z-6Z-5Z-4Z-3Z-2Z-1 Scrambler Taps F(x) X-4+X-7 01001000
CONFIGURATION REGISTER ADDRESS (44h)CCA TIMER THRESHOLD Bits This 8-bit register used configure period time-out threshold watchdog timer. channel busy timer counts until reaches programmed value that point declares that channel clear independent actual energy measured within channel. This register programmable 8-bits. 5632 Time (ms) 1000 where programmable value CR17. Chip Rate example, chip rate MCPS desired timeout ~11ms, 2ch. Bits (0:7) 76543210 00000010 CCA_TIMER_TH 11111111 (Min) (Max)
CONFIGURATION REGISTER ADDRESS (48h) CYCLE THRESHOLD Bits This 8-bit register used configure many times timer allowed reach maximum count before channel declared clear transmission independent actual energy channel. This outer counter loop timer. Each increment represents time timer. value time timer counts. Bits (0:7)
76543210 00000010 timer (Min) FFh; timer (Max)
CCA_TIMER_TH
11111111
7-78
Application Note 9616
CONFIGURATION REGISTER ADDRESS (4Ch) RSSI THRESHOLD, ENERGY DETECT Bits This register contains value RSSI threshold measuring generating energy detect (ED). When RSSI exceeds threshold declared. indicates presence energy channel. threshold that activates programmable. Bits this register used Logic Bits (0:7)
76543210 00000000 (Min) (Max)
RSSI_STAT
00111111
CONFIGURATION REGISTER ADDRESS (50h) SPREAD SEQUENCE (HIGH) Bits This 8-bit register programmed with upper byte receive despreading code. This code used both signalling paths receiver. This register combined with lower byte RX_SPRED(LOW) generates receive despreading code programmable 16-bits. Right justified first. address example. CONFIGURATION REGISTER ADDRESS (54h) SPREAD SEQUENCE (LOW) Bits This 8-bit register programmed with lower byte receiver despreading code. This code used both signalling paths receiver. This register combined with upper byte RX_SPRED(HIGH) generates receive despreading code programmable 16-bits. CONFIGURATION REGISTER ADDRESS (58h) SIGNAL QUALITY (HIGH) THRESHOLD Bits This control register contains upper byte bits sync amplitude signal quality threshold used acquisition. This register combined with lower byte represents 15-bit threshold value sync amplitude signal quality measurements made during acquisition each antenna dwell. This threshold comparison added with threshold registers acquisition. lower value this threshold will increase probability detection probability false alarm. threshold according instructions text. CONFIGURATION REGISTER ADDRESS (5Ch) SIGNAL QUALITY THRESHOLD (LOW) Bits This control register contains lower byte bits sync amplitude signal quality threshold used acquisition. This register combined with upper byte represents 15-bit threshold value sync amplitude signal quality measurement made during acquisition each antenna dwell. CONFIGURATION REGISTER ADDRESS (60h) SIGNAL QUALITY READ (HIGH) Bits This status register contains upper byte bits measured signal quality threshold sync amplitude used acquisition. This register combined with lower byte represents 15-bit value, representing measured sync amplitude. This measurement made each antenna dwell result best antenna. CONFIGURATION REGISTER ADDRESS (64h) SIGNAL QUALITY READ (LOW) Bits This register contains lower byte bits measured signal quality threshold sync amplitude used acquisition. This register combined with higher byte represents 15-bit value, measured sync amplitude. This measurement made each antenna dwell result best antenna. CONFIGURATION REGISTER ADDRESS (68h) SIGNAL QUALITY DATA THRESHOLD (HIGH) Bits This control register contains upper byte bits (8-14) sync amplitude signal quality threshold used drop lock decisions. This register combined with lower byte represents 15-bit threshold value sync amplitude signal quality measurements, made every symbols. These thresholds drop lock probability. higher value will increase probability dropping lock. CONFIGURATION REGISTER ADDRESS (6Ch) SIGNAL QUALITY DATA THRESHOLD (LOW) Bits This control register contains lower byte bits sync amplitude signal quality threshold used drop lock decisions. This register combined with upper byte represents 15-bit threshold value sync amplitude signal quality measurements, made every symbols.
7-79
Application Note 9616
CONFIGURATION REGISTER ADDRESS (70h) SIGNAL QUALITY DATA (high) THRESHOLD READ (HIGH) Bits This status register contains upper byte bits (8-14) measured signal quality sync amplitude used drop lock decisions. This register combined with lower byte represents 15-bit value, representing measured signal quality sync amplitude. This measurement made every symbols. CONFIGURATION REGISTER ADDRESS (74h) SIGNAL QUALITY DATA THRESHOLD READ (LOW) Bits This register contains lower byte bits (0-7) measured signal quality sync amplitude used drop lock decisions. This register combined with lower byte represents 16-bit value, representing measured signal quality sync amplitude. This measurement made every symbols. CONFIGURATION REGISTER ADDRESS (78h) SIGNAL QUALITY THRESHOLD (HIGH) Bits This control register contains upper byte bits (8-15) carrier phase variance threshold used acquisition. This register combined with lower byte represents 16-bit threshold value carrier phase variance measurement made during acquisition each antenna dwell based choice best antenna. This threshold used with sync threshold registers declare acquisition. higher value this threshold will increase probability acquisition false alarm. CONFIGURATION REGISTER ADDRESS (7Ch) SIGNAL QUALITY THRESHOLD (LOW) Bits This control register contains lower byte bits (0-7) carrier phase variance threshold used acquisition. CONFIGURATION REGISTER ADDRESS (84h) SIGNAL QUALITY READ (LOW) Bits This status register contains lower byte bits (0-7) measured signal quality carrier phase variance used acquisition. This register combined with lower byte generates 16-bit value, representing measured signal quality carrier phase variance. This measurement made during acquisition each antenna dwell based selected best antenna CONFIGURATION REGISTER ADDRESS (88h) SIGNAL QUALITY DATA THRESHOLD (HIGH) Bits This control register contains upper byte bits (8-15) carrier phase variance threshold. This register combined with lower byte represents 16-bit threshold value carrier phase variance signal quality measurements made every symbols. CONFIGURATION REGISTER ADDRESS (8Ch) SIGNAL QUALITY DATA THRESHOLD (LOW) Bits This control register contains lower byte bits (0-7) carrier phase variance threshold. This register combined with upper byte) represents 16-bit threshold value carrier phase variance signal quality measurements made every symbols. CONFIGURATION REGISTER ADDRESS (90h) SIGNAL QUALITY DATA READ (HIGH) Bits This status register contains upper byte bits (8-15) measured signal quality carrier phase variance. This register combined with lower byte represents 16-bit value, measured carrier phase variance. This measurement made every symbols. CONFIGURATION REGISTER ADDRESS (94h) SIGNAL QUALITY DATA READ (LOW) Bits This register contains lower byte bits (0-7) measured signal quality carrier phase variance. This register combined with represents 16-bit value, measured carrier phase variance. This measurement made every symbols. CONFIGURATION REGISTER ADDRESS (98h) SIGNAL QUALITY 8-BIT READ Bits This 8-bit register contains sync amplitude signal quality measurement derived from 16-bit Sync signal quality value stored CR28-29 registers. This value result signal quality measurement best antenna dwell. signal quality measurement provides levels signal noise measurement. CONFIGURATION REGISTER ADDRESS RESERVED Reserved CONFIGURATION REGISTER ADDRESS RESERVED Reserved
7-80
Application Note 9616
CONFIGURATION REGISTER ADDRESS (A4h) SEARCH TIME Bits This register programmed with 8-bit value which represents length time demodulator search receive Header. Each increment represents symbol period. CONFIGURATION REGISTER ADDRESS (A8h) DSBPSK SIGNAL Bits This register contains 8-bit value indicating data packet modulation DBPSK. This value will full protocol operation data rate MBPS, used transmitted Signalling Field header. This value will also used detecting modulation type received Header. CONFIGURATION REGISTER ADDRESS (ACh) DQPSK SIGNAL Bits This register contains 8-bit value indicating data packet modulation DQPSK. This value will full protocol operation data rate MBPS used transmitted Signalling Field header. This value will also used detecting modulation type received header. CONFIGURATION REGISTER ADDRESS (B0h) SERVICE FIELD (RESERVED) Bits This register contains detected received 8-bit value Service Field Header. This field reserved full protocol mode future should always 00h. CONFIGURATION REGISTER ADDRESS (B4h) DATA LENGTH (HIGH) Bits This register contains detected higher byte (bits 8-15) received Length Field contained Header. This byte combined with lower byte indicates number transmitted bits data packet. CONFIGURATION REGISTER ADDRESS (B8h) DATA LENGTH (LOW) Bits This register contains detected lower byte received Length Field contained Header. This byte combined with upper byte indicates number transmitted bits data packet. CONFIGURATION REGISTER ADDRESS (BCh) CRC16 (HIGH) Bits This register contains upper byte bits -15) received CRC16 field Header. This register combined with lower byte represents 16-bit CRC16 value protecting transmitted header. fields protected selected configuring header control bits configuration register CONFIGURATION REGISTER ADDRESS (C0h) CRC16 (LOW) Bits This register contains lower byte bits (0-7) received CRC16 field Header. This register combined with upper byte represents 16-bit CRC16 value protecting transmitted header. fields protected selected configuring header control bits configuration register
RX_CRC16 RX_CRC16(HIGH) RX_CRC16(LOW)
76543210
NOTE: receive CRC16 Field protects following fields depending upon mode selection, defined configuration register Mode CRC16 used Mode CRC16 protects Mode CRC16 protects SFD, Length Field Mode CRC16 protects Signalling Field, Service Field, Length Field CONFIGURATION REGISTER ADDRESS (C4h) (HIGH) Bits This 8-bit register contains upper byte bits (8-15) used both Transmit Receive header. This register combined with lower byte represents 16-bit value field.
7-81
Application Note 9616
CONFIGURATION REGISTER ADDRESS (C8h) (LOW) Bits This 8-bit register contains upper byte bits (0-7) used both Transmit Receive header. This register combined with lower byte represents 16-bit value field. CONFIGURATION REGISTER ADDRESS (CCh) SERVICE FIELD Bits This 8-bit register programmed with 8-bit value Service Field transmitted Header. This field reserved future should always 00h. CONFIGURATION REGISTER ADDRESS (D0h) DATA LENGTH FIELD (HIGH) Bits This 8-bit register contains higher byte (bits 8-15) transmit Length Field described Header. This byte combined with lower byte indicates number bits transmitted data packet. 52/53 should 0000h. This value would cause modem reset after SFD. CONFIGURATION REGISTER ADDRESS (D4h) DATA LENGTH FIELD (LOW) Bits This 8-bit register contains lower byte bits (0-7) transmit Length Field described Header. This byte combined with higher byte indicates number bits transmitted data packet, including payload header. 52/53 should 0000h. This value would cause modem reset after SFD. CONFIGURATION REGISTER ADDRESS (D8h) CRC16 (HIGH) Bits This 8-bit register contains upper byte (bits 8-15) transmitted CRC16 Field Header. This register combined with lower byte represents 16-bit CRC16 value calculated HSP3824 protect transmitted header. fields protected selected configuring header mode control bits register address CONFIGURATION REGISTER ADDRESS (DCh) CRC16 (LOW) Bits This 8-bit register contains lower byte (bits 0-7) transmitted CRC16 Field Header. This register combined with higher byte represents 16-bit CRC16 value calculated HSP3824 protect transmitted header. fields protected selected configuring header mode control bits register address configuration register RX_CRC16 RX_CRC16(HIGH) RX_CRC16(LOW)
76543210
NOTE: receive CRC16 Field protects following fields depending upon mode selection. defined register address Mode CRC16 used Mode CRC16 protects Mode CRC16 protects SFD, Length Field Mode CRC16 protects Signalling Field, Service Field, Length Field CONFIGURATION REGISTER ADDRESS (E0h) PREAMBLE LENGTH Bits This register contains count Preamble length counter. This counter programmable 8-bits represents number preamble bits. This should antenna dual antennas.
7-82

Harris Wireless Products Programming HSP3824 Author: John Fa

Top Searches for this datasheet

Other recent searches