MEMORY CMOS SYNCHRONOUS DYNAMIC MB81F16822B-75/-102/-10
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DS05-11035-2E
MEMORY
CMOS
SYNCHRONOUS DYNAMIC
MB81F16822B-75/-102/-103
CMOS 2-Bank 1,048,576-Word Synchronous Dynamic Random Access Memory DESCRIPTION
Fujitsu MB81F16822B CMOS Synchronous Dynamic Random Access Memory (SDRAM) containing 16,777,216 memory cells accessible 8-bit format. MB81F16822B features fully synchronous operation referenced positive edge clock whereby operations synchronized clock input which enables high performance simple user interface coexistence. MB81F16822B SDRAM designed reduce complexity using standard dynamic (DRAM) which requires many control signal timing constraints, improve data bandwidth memory much times more than standard DRAM. MB81F16822B ideally suited laser printers, high resolution graphic adapters, accelerators other applications where extremely large memory bandwidth required where simple interface needed.
PRODUCT LINE FEATURES
Parameter
tRCD
MB81F16822B-75 min. max. min. max. max. 400µA max. 400µA max.
MB81F16822B-102 min. max. min. max. max. 400µA max. 400µA max.
MB81F16822B-103 min. max. min. max. max. 400µA max. 400µA max.
Clock Frequency Burst Mode Cycle Time Access Time From Clock Operating Current (Two Banks Active) Power Down Mode Current (ICC2P) Self Refresh Mode Current (ICC6)
Single +3.3 Supply ±0.3 tolerance LVTTL compatible interface refresh cycles every Dual banks operation Burst read/write operation burst read/single write operation capability
Programmable burst type, burst length, latency Auto-and Self-refresh (every 15.6 power down mode Output Enable Input Data Mask Asynchronous self-refresh feature power (ICC6A 400µA max.)
MB81F16822B-75/-102/-103
PACKAGE
44-pin plastic TSOP (II)
Marking side
(FPT-44P-M18) (Normal Bend)
Package Ordering Information
44-pin plastic (400 mil) TSOP-II with normal bend leads,order
MB81F16822B-75/-102/-103
ASSIGNMENTS DESCRIPTIONS
44-Pin TSOP (II) (TOP VIEW) <Normal Bend: FPT-44P-M18>
VSSQ VCCQ VSSQ VCCQ (BA) VSSQ VCCQ VSSQ VCCQ
(Marking side)
Number
Symbol VCC, VCCQ VSS, VSSQ* (BA)
Description Supply Voltage Data Ground Write Enable Column Address Strobe Address Strobe Chip Select Bank Select Address Input Column
Connection Clock Enable Clock Input Input Mask/Output Enable
These pins connected internally chip.
MB81F16822B-75/-102/-103
BLOCK DIAGRAM
Fig. MB81F16822B BLOCK DIAGRAM
CLOCK BUFFER
each block
BANK-1
BANK-0
CONTROL SIGNAL LATCH COMMAND DECODER
MODE REGISTER
DRAM CORE (2,048
A11,
ADDRESS BUFFER/ REGISTER
ADDR.
COLUMN ADDRESS COUNTER DATA BUFFER/ REGISTER
COL. ADDR.
VCCQ VSS/VSSQ
MB81F16822B-75/-102/-103
FUNCTIONAL TRUTH TABLE (Note
COMMAND TRUTH TABLE Notes 2,3,4
Function Device Deselect Operation Burst Stop Read Read with Auto-precharge Write Write with Auto-precharge Bank Active (RAS) Precharge Single Bank Precharge Banks Mode Register Notes: *8,9 Notes Symbol DESL READ WRIT ACTV PALL READA WRITA (BA) (AP)
Valid, Logic Low, Logic High, either commands assume CSUS command previous rising edge clock. commands assumed valid state transitions. inputs latched rising edge clock. DESL commands have same effect part. READ, READA, WRIT, WRITA commands should only issued after corresponding bank been activated (ACTV command). Refer STATE DIAGRAM. ACTV command should only asserted after corresponding bank been precharged (PRE PALL command). Required after power command should only issued after banks have been precharged (PRE PALL command). Refer STATE DIAGRAM.
MB81F16822B-75/-102/-103
TRUTH TABLE
Function Data Write/Output Enable Data Mask/Output Disable Command ENBL MASK
TRUTH TABLE
Current State Function Notes Symbol CSUS *2,*4 *2,*3 SELF SELFX (BA) (AP)
Bank Active Clock Suspend Mode Entry*1,*5
Except Idle
Clock Suspend Continue Clock Suspend Mode Exit Auto-refresh Command Self-refresh Entry Self-refresh Exit Power Down Entry
Clock Suspend Idle Idle Selfrefresh Idle
Power Down Power Down Exit
Notes: CSUS command requires that least bank active. Refer STATE DIAGRAM. SELF commands should only issued after banks have been precharged (PRE command). Refer STATE DIAGRAM. Self commands should only issued after last data have been appeared Once enters auto-refresh mode, Asynchronous Self-refresh Entry exceuted when brought together with DSEL command(ASE command) within tASE. DSEL commands should only issued after CSUS PRE(or PALL) commands asserted same time.
MB81F16822B-75/-102/-103
OPERATION COMMAND TABLE (Applicable single bank)
Current State Idle Bank Active Addr Command DESL Function Notes
READ/READA Illegal MODE WRIT/WRITA Illegal ACTV PRE/PALL REF/SELF DESL Bank Active after tRCD Auto-refresh Self-refresh Mode Register (Idle after tRSC)
*3,*7
READ/READA Begin Read; Determine MODE WRIT/WRITA Begin Write; Determine ACTV PRE/PALL REF/SELF Illegal Precharge; Determine Precharge Type Illegal Illegal
(Continued)
MB81F16822B-75/-102/-103
Current State Read
Addr
Command
Function (Continue Burst Bank Active) (Continue Burst Bank Active) Burst Stop Bank Active Terminate Burst, Read; Determine Terminate Burst, Start Write; Determine Illegal Terminate Burst, Precharge; Idle Determine Precharge Type Illegal Illegal (Continue Burst Bank Active) (Continue Burst Bank Active) Burst Stop Bank Active Terminate Burst, Start Read; Determine Terminate Burst, Write; Determine Illegal Terminate Burst, Precharge; Determine Precharge Type Illegal Illegal
Notes
DESL
READ/READA
Write
MODE
WRIT/WRITA ACTV PRE/PALL REF/SELF DESL
READ/READA
MODE
WRIT/WRITA ACTV PRE/PALL REF/SELF
(Continued)
MB81F16822B-75/-102/-103
Current State Read with Autoprecharge
Addr
Command
Function (Continue Burst Precharge Idle) (Continue Burst Precharge Idle) Illegal
Notes
DESL
Write with Autoprecharge
READ/READA Illegal MODE WRIT/WRITA Illegal ACTV PRE/PALL REF/SELF DESL Illegal Illegal Illegal Illegal (Continue Burst Precharge Idle) (Continue Burst Precharge Idle) Illegal
READ/READA Illegal MODE WRIT/WRITA Illegal ACTV PRE/PALL REF/SELF Illegal Illegal Illegal Illegal
(Continued)
MB81F16822B-75/-102/-103
Current State Precharge
Addr
Command DESL
Function (Idle after tRP) (Idle after tRP) Illegal
Notes
READ/READA Illegal MODE WRIT/WRITA Illegal ACTV PRE/PALL REF/SELF DESL Illegal (PALL effect other bank) Illegal Illegal (Bank Active after tRCD) (Bank Active after tRCD) (Bank Active after tRCD)
Bank Activating
READ/READA Illegal MODE WRIT/WRITA Illegal ACTV PRE/PALL REF/SELF Illegal Illegal Illegal Illegal
(Continued)
MB81F16822B-75/-102/-103
(Continued)
Current State Refreshing Addr Command DESL NOP/BST Function (Idle after tRC) (Idle after tRC) Notes
READ/READA/ Illegal WRIT/WRITA ACTV/PRE/ PALL REF/SELF/ DESL Illegal
Mode Register Setting
Illegal (Idle after tRSC) (Idle after tRSC) Illegal
READ/READA/ Illegal WRIT/WRITA ACTV/PRE/ PALL/REF/ SELF/MRS
Illegal
ABBREVIATIONS: Address Column Address
Bank Address Auto Precharge
MB81F16822B-75/-102/-103
COMMAND TRUTH TABLE
Current State Selfrefresh Addr Invalid Exit Self-refresh (Self-refresh Recovery Idle after tRC) Exit Self-refresh (Self-refresh Recovery Idle after tRC) Illegal Illegal Illegal (Maintain Self-refresh) Invalid Idle after Idle after Illegal Illegal Illegal Illegal Illegal Function Notes
Selfrefresh Recovery
(Continued)
MB81F16822B-75/-102/-103
Current State Power Down
Addr Invalid
Function
Notes
Exit Power Down Mode Idle Exit Power Down Mode Idle (Maintain Power Down Mode) Illegal Illegal Refer Operation Command Table. Refer Operation Command Table. Refer Operation Command Table.
Both Banks Idle
MODE
Auto-refresh Refer Operation Command Table. Power Down Power Down Illegal Illegal Illegal
MODE
Self-refresh Illegal Invalid
(Continued)
MB81F16822B-75/-102/-103
(Continued)
Current State Bank Active Bank Activating Read/Write Clock Suspend State Other Than Listed Above Addr Function Notes
Refer Operation Command Table Begin Clock Suspend Next Cycle Invalid Invalid Exit Clock Suspend Next Cycle Maintain Clock Suspend Refer Operation Command Table Illegal Invalid
Notes: entries assume High during proceeding clock cycle current clock cycle. Illegal means don't used command. used, power sequence asserted after power shut down. Illegal bank specified state; entry legal bank specified depending state that bank. Illegal bank idle. Must satisfy contention, turn around, and/or write recovery requirements. bank precharging idle state. precharge bank specified (and AP). SELF command should only issued after last read data have been appeared command should only issued condition that Hi-Z. Asynchronous Self-refresh Entry executed when brought together with DSEL command(ASE command) within tASE.
MB81F16822B-75/-102/-103
FUNCTIONAL DESCRIPTION
SDRAM BASIC FUNCTION
Three major differences between this SDRAM conventional DRAMs are: synchronized operation, burst mode, mode register. synchronized operation fundamental difference. SDRAM uses clock input synchronization, where DRAM basically asynchronous memory although been using clocks, CAS. Each operation DRAM determined their timing phase differences while each operation SDRAM determined commands operations referenced positive clock edge. Fig.2 shows basic timing diagram differences between SDRAMs DRAMs. burst mode very high speed access mode utilizing internal column address generator. Once column addresses first access set, following addresses automatically generated internal column address counter. mode register justify SDRAM operation function into desired system conditions. MODE REGISTER TABLE shows SDRAM configured system requirement mode register programming.
CLOCK (CLK) CLOCK ENABLE (CKE)
input output signals SDRAM register type buffers. used trigger register internal burst counter increment. inputs latched positive edge CLK. outputs validated CLK. high active clock enable signal. When latched clock input during active cycle, next clock will internally masked. During idle state (all banks have been precharged), Power Down mode(standby) entered with this will make extremely standby current.
CHIP SELECT (CS)
enables commands inputs, RAS, CAS, address input. When High command signals negated internal operation such burst cycle will suspended. such control isn't needed, tied ground level.
COMMAND INPUTS (RAS,
Unlike conventional DRAM, RAS, CAS, directly imply SDRAM operation, such address strobe RAS. Instead, each combination RAS, CAS, input conjunction with input rising edge determines SDRAM operation. Refer FUNCTIONAL TRUTH TABLE page
ADDRESS INPUTS A10)
Address input selects arbitrary location total 1,048,576 words each memory cell matrix. total twenty address input signals required decode such matrix. SDRAM adopts address multiplexer order reduce count address line. Bank Active command (ACTV), eleven addresses initially latched remainder nine Column addresses then latched Column address strobe command either Read command (READ READA) Write command (WRIT WRITA).
BANK SELECT (A11)
This SDRAM banks each bank organized words 8-bit. Bank selection occurs Bank Active command (ACTV) followed read (READ READA), write (WRIT WRITA), precharge command (PRE).
MB81F16822B-75/-102/-103
DATA INPUTS OUTPUTS (DQ0 DQ7)
Input data latched written into memory clock following write command input. Data output obtained following conditions followed read command input: tRAC from bank active command when (min) satisfied. (This parameter reference only.) tCAC from read command when greater than tRCD (min).(This parameter reference only.) from clock edge after tRAC tCAC. polarity output data identical that input. Data valid between access time (determined three conditions above) next positive clock edge (tOH).
DATA MASK (DQM)
active high enable inputs have output disable input mask function. During burst cycle when High latched clock, input masked same clock output will masked second clock later while internal burst counter will increment will next stage depending burst type.
BURST MODE OPERATION BURST TYPE
burst mode provides faster memory access. burst mode implemented keeping same address automatic strobing column address. Access time cycle time Burst mode specified tCK, respectively. internal column address counter operation determined mode register which defines burst type burst count length 1,2,4 bits boundary. order terminate move from current burst mode next stage while remaining burst count more than following combinations will required: Current Stage Burst Read Burst Read Burst Write Burst Write Burst Read Burst Write Next Stage Burst Read Burst Write Burst Write Burst Read Precharge Precharge Method (Assert following command) Read Command Step Step Mask Command (Normally clock cycles) Write Command after lOWD
Write Command Read Command Precharge Command Precharge Command
burst type selected either sequential interleave mode burst length sequential mode incremental decoding scheme within boundary address determined count length, assigns previous initial) address until reaching boundary address then wraps round least significant address(=0). interleave mode scrambled decoding scheme first access column address even (0), next address will (1), vice-versa.
(Continued)
MB81F16822B-75/-102/-103
(Continued)
When full burst operation executed single write mode, Auto-precharge command valid only write operation. burst type selected either sequential interleave mode. only sequential mode usable full column burst. sequential mode incremental decoding scheme within boundary address determined burst length, assigns previous initial) address until reaching boundary address then wraps round least significant address(=0). Burst Length Stating Column Address
Sequential Mode 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
Interleave 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
FULL COLUMN BURST BURST STOP COMMAND (BST)
full column burst option burst length available only sequential mode burst type. This full column burst mode repeatedly access same column. burst mode reaches column address, then wraps round first column address (=0) continues count until interrupted news Read (READ) /Write (WRIT) Precharge (PRE) Burst Stop (BST) command. selection Auto-precharge option illegal during full column burst operation except write command BURST READ SINGLE WRITE mode. command applicable terminated burst operation. command asserted burst mode, operation terminated immediately internal state moves Bank Active. When read mode interrupted command, output will High-Z. detail rule, please refer TIMING DIAGRAM-8. When write mode interrupted command, data applied same time with command will ignored.
BURST READ SINGLE WRITE
burst read single write mode provides single word write operation regardless burst length. this mode, burst read operation does affected this mode.
MB81F16822B-75/-102/-103
PRECHARGE PRECHARGE OPTION (PRE, PALL)
SDRAM memory core same conventional DRAMs', requiring precharge refresh operations. Precharge rewrites line reset internal address line executed Precharge command (PRE). With Precharge command, SDRAM will automatically standby state after precharge time (tRP). precharged bank selected combination when Precharge command asserted. High, both banks precharged regardless (PALL). Low, bank selected precharged (PRE). Auto-precharge enters precharge mode burst mode read write without Precharge command assertion. This Auto-precharge entered High when read write command asserted. Refer FUNCTION TRUTH TABLE.
AUTO-REFRESH (REF)
Auto-refresh uses internal refresh address counter. SDRAM Auto-refresh command (REF) generates Precharge command internally. banks SDRAM should precharged prior Auto-refresh command. Auto-refresh command should also asserted every 15.6 total 4096 refresh commands within period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh internal timer well Auto-refresh will continue refresh function until cancelled SELFX. Self-refresh entered applying Auto-refresh command conjunction with (SELF). Once SDRAM enters self-refresh mode, inputs except will "don't care" (either logic high level state) outputs will High-Z state. During Self-refresh mode, should maintained. SELF command should only issued after last read data been appeared
ASYNCHRONOUS SELF-REFRESH ENTRY(ASE)
SELF command requires high speed control well other command inputs. MB81F16822B supports Asynchronous Self-refresh entry executed when brought together with DSEL command(ASE command) within tASE(min). Once enters self-refresh mode, CKE=Low should maintained same manner regular Self-refresh mode. command should only effective access command issued after last command been issued.
SELF-REFRESH EXIT (SELFX)
Exit SElf-Refresh mode, apply minimum tCKSP before brought high, then command (NOP) Deselect command (DESL) should asserted within minimum tRC. Refer Timing Diagram detail.It recommended assert Auto-refresh command just after period avoid violation refresh period.
MODE REGISTER (MRS)
mode register SDRAM provides variety different operations. register consists four operation fields; Burst Length, Burst Type, latency, Operation Code. Refer MODE REGISTER TABLE page mode register programmed Mode Register command (MRS). Each field address line. Once mode register programmed, contents register will held until re-programmed another command part loses power). command should only issued condition that Hi-Z. condition mode register undefined after power-up stage. required each field after initialization SDRAM. Refer POWER-UP INITIALIZATION below.
MB81F16822B-75/-102/-103
POWER-UP INITIALIZATION
SDRAM internal condition after power-up will undefined. required follow following Power Sequence execute read write operation. Apply power start clock. Attempt maintain either DESL command input. Maintain stable power, stable clock, condition minimum Precharge banks Precharge (PRE) Precharge command (PALL). Assert minimum Auto-refresh command(REF). Program mode register Mode Register command(MRS).
addition, recommended track insure that output High-Z state. Mode Register command (MRS) before Auto-refresh command (REF).
MB81F16822B-75/-102/-103
Fig. BASIC TIMING CONVENTIONAL DRAM SYNCHRONOUS DYNAMIC
<SDRAM> Active Read/Write Precharge
Read Write Address (A11) Burst Length <Conventional DRAM> Address Select Column Address Select Precharge (A11) (A11) (A10)
Latency
MB81F16822B-75/-102/-103
MINIMUM CLOCK LATENCY DELAY TIME BANK OPERATION
READA WRITA READ ACTV PALL SELF tRSC
First command
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
tRCD
tRCD
tRCD
tRCD
tRAS
tRAS
READ
READA
tDPL tDPL
Second command (same bank)
WRIT
WRITA
tDAL
tDAL
tDAL
tDAL
PALL
SELFX
Notes: Assume conflict. tCK, minimum latency Assume Output High-Z state. Assume tRAS satisfied. Illegal Command
MB81F16822B-75/-102/-103
MINIMUM CLOCK LATENCY DELAY TIME BANK OPERATION
READA WRITA READ ACTV PALL SELF tRSC
First command
tRSC
tRSC
tRSC
tRSC
tRSC
ACTV
tRRD
tRAS
READ
READA
Second command (opposite bank)
WRIT
WRITA
tRAS
PALL
SELFX Notes:
Assume opposite bank idle state. Assume opposite bank active state. Assume conflict. tCK, minimum latency Assume PALL command dose affect operation opposite bank. Assume Output High-Z state. Assume tRAS opposite bank satisfied. Assume tRAS(ACTV PALL) satisfied. opposite bank should interrupted, tRAS bank satisfied. Illegal Command
MB81F16822B-75/-102/-103
Fig. STATE DIAGRAM (Simplified Single Bank Operation State Diagram)
MODE REGISTER IDLE
SELF SELFX SELF REFRESH
CKE\(PD)
CKE\ BANK ACTIVE SUSPEND BANK ACTIVE
ACTV
POWER DOWN
AUTO REFRESH
WRIT WRIT WRITA WRITE SUSPEND WRITE CKE\ WRITA READA READ WRIT READA PALL
READ READ
READ
CKE\
READ SUSPEND
WRITA
READA
WRITE SUSPEND
CKE\
WRITE WITH AUTO PRECHARGE PALL
READ WITH CKE\ AUTO PRECHARGE PALL
READ SUSPEND
POWER
PALL
PRECHARGE
POWER APPLIED DEFINITION ALLOWS Manual Input Automatic Sequence
MB81F16822B-75/-102/-103
ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Voltage Supply Relative Voltage Relative Short Circuit Output Current Power Dissipation Storage Temperature Symbol VIN, VOUT IOUT TSTG Value -0.5 +4.6 -0.5 +4.6 +125 Unit
WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
(Referenced VSS)
Parameter Supply Voltage Input High Voltage Input Voltage Ambient Temperature Notes Symbol VCC, VCCQ VSS, VSSQ Min. -0.5 Typ. Max. Unit
Notes: Overshoot limit: (max)= +1.5 with pulsewidth Undershoot limit: (min)= -1.5 with pulsewidth WARNING: Recommended operating conditions normal operating ranges semiconductor device. device's electrical characteristics warranted when operated within these ranges. Always semiconductor devices within recommended operating conditions. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representative beforehand.
CAPACITANCE
25°C, MHz) Parameter Input Capacitance, Except Input Capacitance Capacitance Symbol CIN1 CIN2 CI/O Min. Typ. Max. Unit
MB81F16822B-75/-102/-103
CHARACTERISTICS
recommended operating conditions unless otherwise noted.) Notes
Parameter Output High Voltage Output Voltage Input Leakage Current (Any Input) Output Leakage Current MB81F16822B-75 MB81F16822B-102 MB81F16822B-103 MB81F16822B-75 MB81F16822B-102 MB81F16822B-103 ICC1D ICC1S Symbol VOH(DC) VOL(DC) Conditions VCC; other pins under test VCC; Data disabled Burst: Length=4, BL=4, tCK=min. bank active, Outputs open, Addresses changed 3-times during tRC(min), Burst Length (each bank), BL=4(each bank), tCK=min. banks active, Output open, Addresses changed 3-times during tRC(min), VIL, banks idle, min, Power down mode, banks idle, Power down mode, VIH, banks idle, min, commands only, Input signals(except CMD) changed times during clock cycles, banks idle, Input signals stable, Value Min. Max. Unit
Operating Current (Average Power Supply Current)
ICC2P
ICC2PS Precharge Standby Current (Power Supply Current)
MB81F16822B-75 MB81F16822B-102 MB81F16822B-103 ICC2N
ICC2NS
MB81F16822B-75/-102/-103
(Continued)
Parameter Symbol Conditions VIL, bank active, min, VIL, bank active, VIH, bank active, min, commands only, Input signals(except CMD) changed times during clock cycles, VIH, bank active, min, Burst Length Outputs open, Multiple-banks active, Gapless data, Value Min. Max. Unit
ICC3P Active Standby Current (Power Supply Current) ICC3PS
MB81F16822B-75 Active Standby Current (Power Supply Current)
MB81F16822B-102
ICC3N
MB81F16822B-103
ICC3NS
MB81F16822B-75 Burst mode Current (Average Power Supply Current)
MB81F16822B-102
ICC4
MB81F16822B-103 MB81F16822B-75 Refresh Current (Average Power Supply Current) MB81F16822B-102 MB81F16822B-103 Refresh Current (Average Power Supply Current) ICC5
Auto-refresh; min, min, Self-refresh; min, Asynchronous Selfrefresh stop); VIL,
ICC6
Refresh Current (Average Power Supply Current)
ICC6A
MB81F16822B-75/-102/-103
CHARACTERISTICS
recommended operating conditions unless otherwise noted.) Notes
Parameter Notes Latency Latency
Symbol MB81F16822B MB81F16822B -102 MB81F16822B -103
Unit
Min. Clock Period Clock High Time Clock Time Input Setup Time Input Hold Time Access Time from Clock (tCK min) Output Low-Z Output High-Z Output Hold Time Latency Latency Latency Latency Latency *5,6 Latency tCK2 tCK3 tAC2 tAC3 tHZ2 tHZ3 tREFI tASE tCKSP 11.5
Max. 15.6
Min.
Max. 15.6
Min.
Max. 15.6
Time between Auto-refresh command Interval Low(or Low) Hold Time Asynchronous Self-refresh Entry Transition Time Setup time Power Down Exit
MB81F16822B-75/-102/-103
BASE VALUES CLOCK COUNT/LATENCY
Parameter Cycle Time Precharge Time Active Time Delay Time Write Recovery Time Data-in Precharge Lead Time Data-in Active/Refresh Latency Command Period Latency Mode Register Cycle Time Bank Active Delay Time Notes MB81F16822B Symbol Min. Max. tRAS tRCD tDPL tDAL2 tDAL3 tRSC tRRD 67.5 22.5 22.5
1cyc+tRP 2cyc+tRP
MB81F16822B -102 Min.
1cyc+tRP 2cyc+tRP
Max. 110000
MB81F16822B -103 Unit Min. Max.
1cyc+tRP 2cyc+tRP
110000
110000
CLOCK COUNT FORMULA Note10
Clock Base Value Clock Period (Round whole number)
MB81F16822B-75/-102/-103
LATENCY-FIXED VALUES
(The latency values these parameters fixed regardless clock period.)
Parameter Clock Disable Output High-Z Input Data Delay Last Output Write Command Delay Write Command Input Data Delay Precharge Output High-Z Delay Notes Symbol lCKE lDQZ lDQD lOWD lDWD lROH2 lROH3 lBSH2 lBSH3 lCCD lCBD MB81F16822B MB81F16822B -102 MB81F16822B -103 Unit cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
Burst Stop Command Output High-Z Delay Delay (min) Bank Delay (min)
Notes: depends output termination load conditions, clock cycle rate, signal clocking rate; specified values obtained with output open termination register. initial pause (DESL NOP) required after power-up followed minimum eight Auto-refresh cycles. characteristics assume capacitive load. reference level measuring timing input signals. Transition times measured between (min) (max). Assumes tRCD satisfied. also specifies access time burst mode. Specified where output buffer longer driven. Actual clock count (lRC) will clock count tRAS (lRAS) (lRP). Operation within tRCD (min) ensures that access time determined tRCD(min) tAC(max); tRCD greater than specified tRCD (min), access time determined tAC. *10. base values measured from clock edge command input clock edge next command input. clock counts calculated simple formula: clock count equals base value divided clock period (round whole number).
MB81F16822B-75/-102/-103
Fig. EXAMPLE TEST LOAD CIRCUIT
Output
LVTTL
Note: characteristics measured this condition. This load circuits applicable VOL.
MB81F16822B-75/-102/-103
Fig. TIMING DIAGRAM, SETUP, HOLD DELAY TIME
Input (Control, Addr. Data)
Output
Note: Reference level input signal LVTTL. Access time measured LVTTL.
Fig. TIMING DIAGRAM, DELAY TIME POWER DOWN EXIT
Don't Care tCKSP (min) clock (min)
Command
Don't Care
ACTV
MB81F16822B-75/-102/-103
Fig. TIMING DIAGRAM, PULSE WIDTH
tRC, tRP, tRAS, tRCD, tWR, tREFI, tDPL, tDAL, tRSC, tRRD, tCKSP Input (Control) Command Command
Note: These parameter limit value rising edge clock from command input next input. tCKSP latency value from rising edge CKE. Measurement reference voltage
Fig. TIMING DIAGRAM, ACCESS TIME
tRAC
tRCD
tCAC
(CAS Latency
(Output)
Q(Valid)
Note: tRAC, tCAC reference value. Data obtained after both tCAC=(CL-1)x satisfied.
MB81F16822B-75/-102/-103
MODE REGISTER TABLE
MODE REGISTER
Opcode ADDRESS MODE REGISTER
Latency Reserved Reserved Reserved Reserved Reserved Reserved
Burst Length Reserved Reserved Reserved Full Column Reserved Reserved Reserved Reserved Reserved
Op-code Burst Read Burst Write Burst Read Single Write
Burst Type Sequential (Wrap round, Binary-up) Interleave (Wrap round, Binary-up)
Notes: When burst length Write always regardless value. Full Column applicable interleave mode.
MB81F16822B-75/-102/-103
TIMING DIAGRAM CLOCK ENABLE READ WRITE SUSPEND
ICKE clock) (Internal) ICKE clock)
(Read)
Change)
Change)
(Write)
Written
Written
Notes: latency (lCKE) clock. During read mode, burst counter will incremented/decremented next clock CSUS command. Output remain same data. During write mode, data next clock CSUS command ignored.
TIMING DIAGRAM CLOCK ENABLE POWER DOWN ENTRY EXIT
tCKSP clock (min)
Command
PD(NOP)
Don't Care tREF (max)
ACTV
Notes: Precharge command (PRE PALL) should asserted bank active burst mode. Precharge command posted conjunction with when burst mode ended this clock. ACTV command latched after tCKSP (min) 1clock (min). should asserted command conjunction with CKE.
MB81F16822B-75/-102/-103
TIMING DIAGRAM COLUMN ADDRESS COLUMN ADDRESS INPUT DELAY
tRCD (min) ICCD clock) ICCD ICCD ICCD
Address
Address
Column Address
Column Address
Column Address
Column Address
Column Address
Note: address delay more clock period.
TIMING DIAGRAM DIFFERENT BANK ADDRESS INPUT DELAY
tRRD (min)
tRCD (min) tRCD (min) Address Address Address Column Address Column Address Column Address Column Address ICBD ICBD
A11(BA)
Bank
Bank
Bank
Bank
Bank
Bank
MB81F16822B-75/-102/-103
TIMING DIAGRAM DQM-INPUT MASK OUTPUT DISABLE
Read) IDQZ clocks) Read)
Hi-Z
burst
Write) IDQD (same clock) Write) Masked
burst
TIMING DIAGRAM PRECHARGE TIMING (APPLIED SAME BANK)
tRAS (min) Command ACTV Precharge
MB81F16822B-75/-102/-103
TIMING DIAGRAM READ INTERRUPTED PRECHARGE (Example
Command
Precharge IROH clocks)
Hi-Z
Command
Precharge IROH clocks)
Hi-Z
Command
Precharge IROH clocks)
Hi-Z
Command
Precharge effect (end burst)
Note: case lROH clock. case lROH clock.
MB81F16822B-75/-102/-103
TIMING DIAGRAM READ INTERRUPTED BURST STOP (Example Full Column)
Command (CL=2)
IBSH clocks)
Qn-2
Qn-1
Qn+1
Hi-Z
Command (CL=3)
IBSH clocks)
Qn-2
Qn-1
Qn+1
Qn+2
Hi-Z
Note: selection Auto-precharge option illegal during full column burst operation except Write command BURST READ SINGLE WRITE mode.
TIMING DIAGRAM WRITE INTERRUPT BURST STOP (Example
Command
Command
Last Data-In
Masked
MB81F16822B-75/-102/-103
TIMING DIAGRAM WRITE INTERUPTED PRECHARGE (Example
Command
Precharge tDPL(min) tRP(min)
Active
Data-In
Last Data-In
Masked
Note: precharge command (PRE) should only issued after tDPL final data input, satisfied.
TIMING DIAGRAM READ INTERRUPTED WRITE (Example
IOWD clocks) Command Read Write
Note
Note IDQZ clocks)
Note IDWD (same clock) Data Masked Data
Data
Notes:
First makes high-impedance state High-Z between last output first input data. Second makes internal output data mask avoid contention. Third illustrated above also makes internal output data mask. burst read ends (final data output) after second clock burst write, this third required avoid internal contention.
MB81F16822B-75/-102/-103
TIMING DIAGRAM WRITE READ TIMING (Example
(min) Command Write Read
(CL-1) Masked Read (max)
Note: Read command should issued after final data input satisfied read command applied same bank.
MB81F16822B-75/-102/-103
TIMING DIAGRAM READ WITH AUTO-PRECHARGE (Example Applied same bank)
tRAS (min) (min)
Command
ACTV
READA clocks (same Value
DESL
ACTV
tRP(min)
Notes: Precharge read with Auto-precharge command (READA) started from number clocks that same Burst Length (BL) after READA command asserted. Next ACTV command should issued after tRP(min) from READA command.
TIMING DIAGRAM WRITE WITH AUTO-PRECHARGE (Example Applied same bank)
tRAS (min)
tDPL (min)
tDAL (min) (min)
Command
ACTV
WRITA
DESL
ACTV
Notes:
Precharge write with Auto-precharge started after tDPL from burst. Even final data masked DQM, precharge does start clock final data input. Once auto precharge command asserted, command within same bank issued. Auto-precharge command doesn't affect full column burst operation except Burst Read Single Write mode. Next command should issued after (min) (min) from WRITEA command.
MB81F16822B-75/-102/-103
TIMING DIAGRAM AUTO-REFRESH TIMING
Command
(min)
(min)
Command
(BA)
Don't Care
Don't Care
Don't Care
Notes: banks should precharged prior first Auto-refresh command (REF). Bank select ignored command. refresh address bank select selected internal refresh counter. Either DESL command should asserted during period while Auto-refresh mode. activation command such ACTV command other than command should asserted after from last command.
TIMING DIAGRAM SELF-REFRESH ENTRY EXIT TIMING
tCKSP (min) tRC(min)
Command
NOP*1
SELF
Don't Care
SELFX
Command
Notes: Precharge command (PRE PALL) should asserted bank active prior Self-refresh Entry command (SELF). Self-refresh Exit command (SELFX) latched after tCKSP (min). recommended apply command conjunction with CKE. also recommended apply minimum clocks stabilize external clock prior SELFX command. Either DESL command used during period. should held High within tRC(min) period after tCKSP
MB81F16822B-75/-102/-103
TIMING DIAGRAM SELF-REFRESH TIMING (Asynchronous Self-refresh)
tASE tCKSP (min) (min)
Command
AREF
DESL
DESL
Command
Auto-refresh command cancels Entry entry Self-refresh.
Self-refresh Entry
Notes: Precharge command (PRE PALL) should asserted bank active prior Auto-refresh command (AREF). Either DESL command used during period. Applying command before brought cancenls entry Asynchronous Self-refresh. Either DESL command used during tASE period.
TIMING DIAGRAM SELF-REFRESH TIMING (Async. Self-refresh)
tASE CLK=Low fixed (min)
Command
AREF
DESL
DESL
Command
Auto-refresh Entry
Self-refresh Entry
Notes: Precharge command (PRE PALL) should issued bank active prior Auto-refresh command (AREF). Either DESL command must maintained. must stop kept order enter Asynchronous Self-refresh. Either DESL command used during period.
MB81F16822B-75/-102/-103
TIMING DIAGRAM SELF-REFRESH TIMING (Async. Self-refresh Cancellation)
tCKSP(min)*1
tASE
Command
AREF
DESL
Auto-refresh Entry
Notes:
Simply turn High before tASE (min). Next commnad issued form clock later when tCKSP satisfied. Either DESL command used. cancellation Asynchronous Self-refresh entry done brought High prior tASE (min).
TIMING DIAGRAM MODE REGISTER TIMING
tRSC
Command
DESL
ACTV
Address
Mode
Address
Note: Mode Register command (MRS) should only asserted after banks have been precharged.
MB81F16822B-75/-102/-103
PACKAGE DIMENSION
44-pin plastic TSOP (II) (FPT-44P-M18)
Resin protrusion. (Each side: .006 (0.15) Max)
Details part
0.15(.006)
0.25(.010) INDEX LEAD
0.10(.004) 0.40(.016)
18.41±0.10
(.725±.004) 0.30±0.10 (.012±.004) 0.13(.005)
1.15±0.05 (Mounting height) (.045±.002)
11.76±0.20 (.463±.008) 10.16±0.10 (.400±.004)
0.125±0.05 (.005±.002)
0.80(.031) TYP.
0.10(.004) 16.80(.661) REF.
0.50±0.10 (.020±.004) 0.05(.002)MIN (STAND OFF)
10.76±0.20 (.424±.008)
1995 FUJITSU LIMITED F44025S-1C-1
Dimensions inches)
MB81F16822B-75/-102/-103
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. FUJITSU semiconductor devices intended standard applications (computers, office automation other office equipment, industrial, communications, measurement equipment, personal household devices, etc.). CAUTION: Customers considering products special applications where failure abnormal operation directly affect human lives cause physical injury property damage, where extremely high levels reliability demanded (such aerospace systems, atomic energy controls, floor repeaters, vehicle operating controls, medical devices life support, etc.) requested consult with FUJITSU sales representatives before such use. company will responsible damages arising from such without prior approval. semiconductor devices have inherently certain rate failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Control Japan, prior authorization Japanese government should required export those products from Japan.
http://www.fujitsu.co.jp/
North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. Fri.: (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA #05-08, Lorong Chuan Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9712 FUJITSU LIMITED Printed Japan
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