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DESIGN IDEAS

EDITED
DESIGN IDEAS
BILL TRAVIS & ANNE WATSON SWAGER
Scheme implements multiple output ports
W KURDTHONGMEE, NAKORN SI THAMMARAT, THAILAND
FIGURE 1
OUTPUT PORT 1
OUTPUT PORT 2
OUTPUT PORT 3
OUTPUT PORT 4
One way to update output ports is to address every port (a) another method is to address them all simultaneously (b).
DESIGN IDEAS
LISTING 1-MCS-51 ROUTINE
TO UPDATE OUTPUT PORTS
LISTING 2-MCS-51 ROUTINE
FOR SIMULTANEOUS UPDATE
PIC plots pixels sans controller
DARYL CHRISTOPHER, JUNIATA COLLEGE,
TOM FISHER, INEXPENSIVE SYSTEMS, HUNTINGDON, PA
DESIGN IDEAS
FIGURE 2
LINE 0 FLM CP1 CP2 M D1 LINE 1
The 16C73A sends these signals to the DMF697. FLM is startof-scan, CP1 is start-of-line, CP2 is data latch, M is driver-voltage polarity, and D1 is data. FIGURE 3
-9V 5V
10k CONTRAST MPS 2907
RA0 50k CURSOR RA2
DMF697 VEE VCC VSS D1 FLM CP1 CP2 M 20 MHz
PIC16C73A OSC1
RC0 RC1 RC2 RC3
LISTING 1-CODE FRAGMENT
FOR A SINGLE PIXEL
This minimal circuit displays the graph and permits cursor movement it makes no provision for acquiring data.
LISTING 2-CODE FOR OBTAINING
STATIC INFORMATION
DESIGN IDEAS
Antenna extension provides open-door policy
RICHARD PANOSH, VISTA, BOLINGBROOK, IL
DESIGN IDEAS
Dual comparators stabilize proximity detector
ARTHUR HARRISON, US ARMY RESEARCH LABORATORY, ADELPHI, MD, AND JOSEPH STERN, MAXIM INTEGRATED PRODUCTS, SUNNYVALE, CA
FIGURE 2
Exclusive-ORing two inputs, one delayed by the R1-C1 network, and subsequent filtering by R2 and C2 implements a capacitance-to-voltage conversion.
FIGURE 1
5V 5V 0.1 µF 1 2 14 3 10k C8 0.1 µF TP1 + 4.7 µF
5V-DC INPUT
1 / 4 74HC86N
This proximity detector lights the LED when a person approaches the antenna plate within a threshold distance set by potentiometer R2.
of 17.3 nsec, yielding a time difference of only 0.8 nsec. To detect such small time differences-over temperature and with accuracy-the comparators must be stable in offset voltage and propagation delay. (Changes in offset voltage as well as propagation delay affect delay time.) One 10nsec comparator is generally stable to within 1 nsec. To resolve subnanosecond intervals, use the dual-comparator approach of Figure 1, which increases the useful resolution by a factor of four to five. Op amp IC2A offsets and amplifies the dc voltage at TP1, which corresponds to the distance between hand and antenna plate. A hand movement toward the antenna causes the voltages at TP1 and TP2 to rise. IC2B and Q1 serve as a com-
DESIGN IDEAS
Low-cost switcher converts 5 to 24V
PAUL C FLORIAN, PLANO, TX
FIGURE 1
5V L1 330 µH DCR2 ISAT200 mA 5V 0 TO 5V CONTROL VOLTAGE 3 0.1 µF 2 + C1 10 µF 35V ELECTROLYTIC - +
24V 0.1 µF
10k C1 100 µF 10V ELECTROLYTIC + 0.001 µF Q1
D1 1N4933 D2 24V ZENER 1N5252B
VOUT 24V 8 mA
R1 10k
8 LM358N 4 1 0 TO 20V TO VCO
0.047 µF Q3
C1 150 pF
A simple three-transistor switching regulator (a) supplies 24V and 8 mA. The circuit can help provide a 0 to 20V VCO tuning voltage from a 0 to 5V control voltage (b).
DESIGN IDEAS
60-Hz modulator records process variables
WARREN JOCHEM, RESEARCH TRIANGLE INSTITUTE, RESEARCH TRIANGLE PARK, NC
FIGURE 1
C3 0.1 µF J3 OUTPUT 14 0 TO 1V RMS 60 Hz
2 J1 INPUT 0 TO 10V DC R1 390k R2 100k
J2 COMM
- 1 IC1A 3 + TLC2274 4 C1 0.1 µF 5V
13 - IC1D 12 + R6 100k
CALIBRATE
C6 0.1 µF 11 - IC1C 10 + 9 R8 10k R9 1M -5V C12 10 µF + C10 0.1 µF VO IC4 79L05 GND VI + C9 470 µF D1 1N4001 5V C11 10 µF + C8 0.1 µF VO IC3 78L05 GND VI + C7 470 µF 12V AC
T1 120V AC
R10 1k
D2 1N4001
Chopper techniques convert a dc input signal from a process variable to a 60-Hz ac signal for measurement on a three-phase power monitor.
DESIGN IDEAS
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