communication with Touch Memory originated master using bit-synchronou

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

communication with Touch Memory originated master using bit-synchronou

Datasheet Thumbnail

Top Searches for this datasheet

APPENDIX MANAGING CONCURRENT INTERRUPTS TOUCH MEMORY SOFTWARE
communication with Touch Memory originated master using bit-synchronous, half-duplex, 1-wire serial link. Each Touch Memory contains self-timed serial communication controller which transmits receives each within specified period time after low-going edge originated master. However, time interval between bits determined master arbitrarily long, allowing competing interrupts from other devices serviced between bits. Communication with Touch Memory accomplished with falling edge activated time slots lasting with reset/presence signal having high period each lasting These time-dependent signals generated detected software procedures TouchReset TouchBit, which usually coded assembly language because they must produce short, accurate time intervals. Copies these routines variety microprocessors available from Dallas Semiconductor. might appear from timing requirements Touch Memory communication that Touch Memory would monopolize time microprocessor, leaving time service competing interrupts from timers other devices. fact, this case. When properly written, TouchReset TouchBit procedures inhibit interrupts only microseconds time, allowing ample opportunity service other interrupting devices. following text describes typical timing constraints imposed requirements interrupt service proposed method dealing with them while performing Touch Memory operations. first case considered which interrupts generated competing events occur intervals short interrupt service procedure requires less than execute. this case, depicted Figure interrupt system left enabled times except during first microseconds write-one read time slot. interrupt system must disabled while 1-Wire driven low, released, sampled, order insure that these operations take place time less. (The minimum allowable time between interrupts reduced using less than these operations, this fails take advantage available recovery time affect performance 1-Wire communication with long wire lengths large numbers Touch Memories bus.) Since interrupt services require less than every logic state response period lasts least TouchReset procedure sample 1-Wire sufficiently high rate that important characteristics response signal missed. (Note that more than half time spent servicing interrupts, TouchBit procedure need reference independent timer produce correctly timed write-zero signal, order insure that write-zero signal extended misinterpreted reset signal.) Figure depicts range interrupt intervals durations over which this software solution applied. second case, depicted Figure interrupts occur intervals short interrupt service procedures require more less than execute. This case handled disabling interrupts during entire time slot also during critical period TouchReset signal. critical period period immediately following release 1-Wire Bus, after been held least During critical period, procedure watches 1-Wire high again (presence pulse), high remain high presence pulse), remain (short circuit). remainder TouchReset procedure executed with interrupts enabled. Figure depicts range interrupt intervals durations over which this software solution applied. event that time interval between interrupts from same competing source unpredictable that limit cannot guaranteed, still possible communicate successfully with Touch Memory typical interval between interrupts long enough allow some communication packets sent received successfully. this method, interrupt system enabled times, allowing competing interrupts operate normally. Assuming competing interrupt randomly distributed time, approximately chance causing error either read write operation. therefore still possible, average competing interrupt rate excessive, CRC-checked packet transmitted confirmed without errors. Touch Memory communication protocols inherently error-tolerant provide reliable communication with uncertain electrical contact, this mechanism
061495 148/150
also used compensate errors introduced competing interrupts. efficiency this technique depends both average interrupt rate packet size. That interrupt environment becomes more contentious, effective data transfer rate goes down. interrupt timing unfavorable that none conditions described above satisfied, timing problems still eliminated completely hardware interface which capable performing critical timing buffering independently software. This case communication using serial port, where 8250 16C450 UART used generate critical timing detect response. this case, depicted Figure TouchReset TouchBit written high-level language interrupts left enabled times. This simplest system design since there possibility interfering with other interrupt-driven processes. 8250 16C450 UARTs have more capability than needed this task, much simpler bi-directional single- buffer with hardware-generated timing could suffice. Most UARTs capable operation 115200 above used handle timing when performing Touch Memory I/O. Recently introduced palmtop computers PDAs like Apple Newton, HP100, AST/Tandy/Casio Zoomer support 115200 rate. Figure depicts range interrupt intervals durations over which this software solution applied.
1-WIRE COMMUNICATION SHARED PROCESSOR ENVIRONMENT Figure (SHADED AREA REPRESENTS ASSURED COMMUNICATION)
061495 149/150
061495 150/150

communication with Touch Memory originated master using bit-synchronou

Top Searches for this datasheet

Other recent searches