following questions frequently asked customers using RoboClock, RoboCl

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Frequently Asked Questions about CY7B991/2 (RoboClock), CY7B9911 (RoboClock+) CY7B9910/20 (Robo Jr.)
following questions frequently asked customers using RoboClock, RoboClock+ Robo their applications. These answers will serve introduction each topic. Separate application notes cover most topics more complete detail. external divider feedback loop? Yes, possible external dividers feedback path. However, large dividers dividers that have inherently long delay, should used cautiously. There some constraints that should followed. large divider ratio cause phase detector update gaps become excessively large. This will cause drift excessively result output jitter. "rule thumb" maximum divider ratio feedback path should less than Larger values used with some consideration. achieve degree offset? external divider achieve degree offset independent frequency? simplest achieve degree phase shift programmable skew functionality RoboClock. exact offset degrees only available when HIGH state. When state, offset close degrees still attainable. period divided into different amounts time units (tU) each setting pin. VCOperiod (FS=LOW) VCOperiod (FS=MID) VCOperiod (FS=HIGH)
degree offset VCOperiod Therefore, degree offset would require offset degree offset degree offset HIGH degree offset
offset with HIGH achievable simply programming output have skew However, possible exact offset (FS=LOW) ±6.5 (FS=MID). With position, offset possible. This creates phase offset degrees degrees tU). 90-degree phase shift equal offset. skewed outputs shifted ±4.62 ±5.38 (off ±0.38 ns). With position, offset degrees (±10 degrees (±12 possible. MHz, exact 90-degree phase shift equal ±8.33 offset. skewed outputs shifted ±7.58 ±9.09 (off ±0.76 ns). Offsets between outputs achieved selecting appropriate skew taps shown Table specific outputs connected This establishes zero phase reference, phase relationship between outputs maintained even another output (and skew) used Table 1.Skew Combinations degree offset FS=HIGH FS=MID FS=HIGH
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Frequently Asked Questions about CY7B991/CY7B992 (RoboClock)
also possible external dividers, Figure shows, achieve degree offset independent frequency. This example utilizes negative-edge triggered flip-flop external divider. possible achieve positive negative degree phase shift independent frequency range. polarity phase determined choosing either output from flip-flop. delay flip-flop also compensated adjusting programmable skew output RoboClock. should noted that propagation delay flip-flop typically controlled specified. Also, delays symmetrical. compensating skew control RoboClock account propagation delays hold over temperature, because most flip-flops exhibit significant variation while RoboClock does not.
Phase=0
(+90°)
(-90°) Delay Flip-Flop Figure Circuit Achieve Degree Offset What happens outputs when there input? There scenarios that cause output react differently: connected during power behavior output will probabilistic. state dependent upon internal circuitry that controlled input. output inactive output clock) oscillate lowest possible frequency determined setting pin. input disconnected during steady state operation, will "think" that running fast will compensate lowering frequency. frequency will determined setting pin. final frequency will lower than values stated data sheet. When input reconnected, will phase frequency alignment. will compensate increasing frequency will overshoot final frequency. will continue damped oscillation state until "locks" onto signal. This time called LOCK data sheet.
Frequently Asked Questions about CY7B991/CY7B992 (RoboClock)
RoboClock 3.3V-compatible? RoboClock requires supply. However, possible make output swing 3.3V compatible levels RoboClock (CY7B991). CMOS level RoboClock (CY7B992) cannot made 3.3V-compatible design which produces rail-to-rail output swings. termination networks shown Figure either which make RoboClock compatible with 3.3V systems. more in-depth explanation, application note, "Using CY7B991 (RoboClock), CY7B9911 (RoboClock+) CY7B9910 Robo Jr.) 3.3V Environment" available from Cypress Semiconductor Corporation website (http://www.cypress.com).
+3.3V
Figure Typical Termination 3.3V 3.3V-Compatible RoboClock Outputs What jitter characteristics RoboClock? connect many RoboClocks cascaded configuration? RoboClock neither tolerant intolerant jitter. more accurate describe jitter characteristics RoboClock. jitter transfer characteristic that second order low-pass filter with point approximately MHz. plot seen Figure This plot shows typical behavior with frequency MHz. There some amplification narrow band just before roll-off (gain greater than evidenced plot. This means that jitter components that fall within this range will amplified they pass through RoboClock. This reason that recommended connect more than RoboClocks series. input jitter peaking frequency will amplified passes through cascaded devices. Although this problem evident, recommended limit series connected RoboClocks extremely conservative. band jitter amplification changes with temperature process variation eventually will result lower cascaded multiplication than peak gain would predict. Thus, real applications, jitter amplification seldom reaches point that output jitter causes system function correctly. Also, this type jitter necessarily problem except between systems served multiple RoboClocks.
Figure Jitter Transfer Characteristics RoboClock
Frequently Asked Questions about CY7B991/CY7B992 (RoboClock)
What required voltage levels three level input? model three-level input? voltage levels VIHH, VIMM, VILL data sheet. VIHH between VCC. VIMM between Vcc/2 Vcc/2+500 between input left floating will held within VIMM range. These values guarantee that correct value will detected. actual thresholds (high threshold VTHH, threshold VTHL) will in-between specified ranges, shown Figure
VIHH VTHH VIMM VTHL
VCC/2
VILL
Figure Voltage Levels 3-Level Inputs three-level inputs modeled pull-up pull-down resistor. internal resistor values three-level inputs approximately 25-K pull-up 25-K pull-down. This shown Figure corresponding curve trace three-level input (with VCC=5.0V applied part) seen Figure Figure same curve trace with vertical scale zoomed out. large change input current approximately 5.7V -0.6V diodes becoming forward biased.
VTHH Three Level Input VTHL Figure Internal Pull-Up Pull-Down Resistors Three-Level RoboClock Input with Threshold Detection
What phase relationship between output? They negative (falling) edge aligned. Figure falling edge divide four output (3Q1), aligned with falling edge divide output (4Q1). having falling edges clocks aligned, rising edges spaced farther time. assumed that most logic rising edge triggered, this makes design more robust jitter, skew problems, loading effects. This trade-off important because divided outputs skewable
Frequently Asked Questions about CY7B991/CY7B992 (RoboClock)
Figure Curve Three-Level RoboClock Input (Zoomed
Figure Curve Three-Level RoboClock Input
Frequently Asked Questions about CY7B991/CY7B992 (RoboClock)
Figure Frequency Divider Example What models available RoboClock? There HSPICE IBIS models available Cypress BBS. number U.S. (408) 943-2954, Japan number 49-810-62-2675, Europe number 49-810-62-2675. They also available Cypress Semiconductor website (http://www.cypress.com). Logic Modeling division Synopsys also offers wide variety standard logic models that various simulation platforms. These models (cy7b991-XX cy7b992-XX) accurately depict functionality RoboClock. They reached (800) 346-6335 their site: slow TEST mode? There lower limit frequency TEST mode. This because TEST mode internal bypassed input levels supplied directly control outputs. input signal applied will seen outputs with approximately delay. This delay roughly changed using TEST level inputs. outputs will still function according function select pins. more depth explanation the, "CY7B991/2 (RoboClock), CY7B9911 (RoboClock+) CY7B9910/20 (Robo Jr.) Test Mode" application note. available Cypress Applications Handbook Cypress Semiconductor website (http://www.cypress.com). What effect does slow rise fall times input have RoboClock operation? slow rise time affects apparent tPD, which propagation delay (REF rise rise). measured arbitrary standard 1.5V (CY7B991) VCC/2 (CY7B992). actual threshold voltage (VTH) will vary around 1.5V (0.8v<VTH<2.0V CY7B991 1.35V<VTH<VCC 1.35V CY7B992) depending upon VCC, temperature process variation. This change will affect example, input ramp rate approximately V/ns then 100mV variation will change apparent input gate approximately This normally problem, since both threshold matched driven similar edge rates. ramp rate much longer than then this "apparent" variation will show increased decreased) through RoboClock. Actually (disregarding minimal effect edge rate VTH) does change. Only measurement changes. propagation delay from time begins rise, until time when output begins rise, will look like increasing with slower rise rate with increasing VTH. Another possible effect slow rise fall times could introduced jitter. This increased amount time that input near threshold voltage. threshold, input buffer much more sensitive variations noise. there power-up conditions that cause part misbehave? Yes, there This mentioned NOTE CY7B991/992 datasheet. states, "When selected HIGH, input must transition upon power-up until reached 4.3V". power supply ramps-up, "wakes-up" before output buffers. Since output buffers functional, there transitions
Frequently Asked Questions about CY7B991/CY7B992 (RoboClock)
"thinks" that running fast enough, speeds eventually reaching maximum allowable rate dictated pin. Finally, reaches level where output buffers become functional. When HIGH, possible internal faster than outputs follow (only undivided outputs exhibit this behavior). Although outputs functional, they still provide proper transitions thus, still "thinks" that running slow. result that locks maximum rate stays there with outputs able provide proper transitions. This condition issue RoboClock operating with position, divided output implemented feedback. these conditions then there methods ensure that this situation does occur. 1.Assure that stable transitions) until reaches 4.3v (point where output buffers come on). 2.Have part power TEST mode (PLL bypassed with mode position). 3.Hold that will ramp point that outputs follow) until above 4.3v. manage connect power-on reset. This will ensure that until RoboClock power. power-on reset line CMOS, then connected directly pin. then able drive HIGH state (see question necessary resistor network proper voltage levels pin. implementation look like Figure
Input Power-on Reset Figure Management Using Power-on Reset Another manage using time constant make ramp slower than VCC, holding state until reaches 4.3v using pull-up pull-down values determined following: takes seconds ramp, then find value with following equation: VIMM e^(-t/RC)) VIMM maximum voltage pin. From datasheet, this VCC/2+500 Choose your values product equals calculated value. example, VCC=5.0V, takes second ramp (t=1 ms). should always chosen that less than Then should approximately micro Farads. What output buffer current output buffer power output pair? These specs (minimum maximum values) listed data sheet. They ICCN respectively. total output current output pair (RoboClock pairs total) approximated following expression that includes device current plus load current (expressed mA): CY7B991: CY7B992: total power dissipation output pair approximated following expression that includes device power dissipation plus power dissipation load circuit (expressed mW): CY7B991:
Frequently Asked Questions about CY7B991/CY7B992 (RoboClock)
CY7B992 where F=frequency C=capacitive load Z=line impedance Ohms N=number loaded outputs: FC=F*C example, when using CY7B991 with F=40 MHz, C=30 Z=50, (one output loaded, other floating), ICCN calculated follows: ICCN= ICCN= 27.87 this specific output pair PD=99.264 this specific output pair What different skew values data sheet mean? Skew difference time between transitions pair outputs with fixed time relationship.The skew values apply skew between different outputs RoboClock identically loaded specified datasheet. skew depends upon function output many cases function rest outputs. outputs RoboClock have been carefully designed control delay edge rate, attempt minimize skew. Outputs built pairs (XQ0 XQ1) sharing same drive power supply. outputs also categorized their function. classes nominal, divided, inverted. Ideally edges would occur However, minor variation internal delay, output rise fall delay, adjacent output transition direction, edge placement (coupling) affect position output transition. skew specifications shown datasheet attempt quantify these variations. further information these values calculate desired skew see, "Everything Need Know About CY7B991/2 (RoboClock), CY7B9911 (RoboClock+) CY7B9910/20 (Robo Jr.)" Cypress Applications Handbook Cypress Semiconductor home page (http://www.cypress.com). tSKEWPR: Zero Output Matched-Pair Skew This parameter specifies maximum amount skew between outputs same pair (e.g., 1Q0) when eight outputs selected 0tU. tSKEW0:Zero Output Skew (All Outputs) This parameter specifies time between first output edge last output edge outputs that selected (even there other outputs selected divide-by invert functionality shifted outputs). tSKEW1:Output Skew (Rise-Rise,Fall-Fall, Same Class) This parameter specifies maximum amount skew between outputs same output class selected same output adjustment without restrictions placement function other outputs. signals compared must same class must rising edge rising edge, falling edge falling edge aligned. three different output classes Nominal, Divided Inverted. Nominal includes phase variants including 0tU. Divided includes divide four divide functionality. Inverted class includes invert function allowed 4QX. tSKEW2:Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided) This parameter specifies amount output skew between rising falling edge Nominal output opposite edge Inverted output. also applies opposite edge transitions between Divided outputs. tSKEW3:Output Skew (Rise-Rise, Fall-Fall, Different Class) This output skew parameter specifies maximum same edge transition difference between different class outputs.
Frequently Asked Questions about CY7B991/CY7B992 (RoboClock)
tSKEW4:Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted) This parameter specifies maximum opposite edge transition difference between different class outputs. tDEV tSKEW5: Device-to-Device Output Skew system design, tDEV amount skew between outputs devices operating same environment (frequency, temperature, voltage, flow, etc.). encompasses worst case output possibilities, therefore very conservative number. tSKEW5 outdated parameter that does incorporate worst case scenario, required addition applicable output-output skew value calculate actual device-device skew. correct value when calculating skew between outputs between devices tDEV. tPD:Propagation Delay (REF Rise Rise) This measure misalignment between rise rise. either positive negative. typical value What difference between ODCV (Output Duty Cycle Variation) tPWH/tPWL? tODCV deviation output from duty cycle measured 1.5V CY7B991 VCC/2 CY7B992. tPWH/tPWL deviation measured corresponding high thresholds (tPWH measured 2.0V CY7B991 CY7B992, tPWL measured 0.8V CY7B991 0.2V CY7B992). differences account rise fall time "pulse-narrowing" from point measurement. need estimate reliability design. many components does contain? complete documentation reliability RoboClock see, "Product Reliability Handbook-1996". most commonly desired reliability information follows. Technology: Number components: Number transistors: Number gates: size: Commercial Theta Commercial Theta Junction Temp.: BiCMOS 3250 2130 mils mils degrees Watt degrees Watt degrees
Cypress Semiconductor Corporation, 1997. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

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