3502 ICD2062B Dual Programmable ECL/TTL Clock Generator
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3502
ICD2062B
Dual Programmable ECL/TTL Clock Generator
Features
Second generation dual oscillator graphics clock generator PECL Video Outputs: Outputs: Individually programmable PLLs using highly reliable, Manchester-encoded, 21-bit serial data word 2-pin serial programming interface allows direct connection most graphics chip sets with external hardware required Programmable video clock dividers allow easy interface most RAMDACs VRAMs Three-state oscillator control disables outputs test purposes Phase-locked loop oscillator input derived from single 14.318 crystal Sophisticated internal loop-filter requires external components operation Low-power, high-speed CMOS technology Available 20-pin SOIC package configuration sired frequency value range (VCLKOUT) (MCLKOUT). ICD2062B ideally suited design where multiple varying frequencies required, replacing more expensive metal oscillators, particularly where application requires expensive complementary oscillators. Video Clock output programmatically divided-by 8-in order generate Load Signal, which further divided clocking video timing logic. second Load Signal synchronously gated order enable starting stopping clocking video RAMs. ICD2062B also configure pipeline delay certain RAMDACs (such Bt457/458) fixed pipeline delay. Some examples uses this device include: graphics board clocks allow dynamic synchronization with different brands monitors display formats; on-board test strategies where ability skew system's desired frequency (for example: ±10%) allows worst case evaluations.
ICD2062A ICD2062B
ICD2062B revision ICD2062A complete mask redesign which includes feature enhancements well minor fixes. following points detail differences between versions. ICD2062B offers following features: VCO-The primary difference between versions design internal VCO. ICD2062B video been redesigned support frequencies (see above); Higher Upper Frequency Limit (VCLKOUT)-165 MHz; Register Initialization ROM-A allows ICD2062B initialized higher default frequencies; More Load Clock divisors-The ICD2062B Load Clock divisors
Functional Description
ICD2062B clock generator high-resolution video displays. uses low-frequency, low-cost reference crystal produce following: compatible complementary output signal high-speed video RAMDACs, high-speed output signal video RAMs system logic operation, requisite load, control, clock signals control loading data between controller, VRAM, RAMDACs. ICD2062B Dual Programmable Clock Generator offers fully user-programmable phase-locked loops single package. outputs changed fly"
Configuration
SOIC View S0/CLK S1/DATA AVDD XTALIN XTALOUT MCLKOUT VCLKOUT VCLKOUT ENABLE LDA/4 LDA/2 INIT1 INIT0 ERROUT
ICD2062B-1
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134 408-943-2600 March 1995 Revised July 1997
ICD2062B
Logic Block Diagram
f(REF) XTALIN XTALOUT Reference Frequency (Typically 14.31818 Xtal)
AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA MCLK VCLK AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
Buffer
MCLKOUT
ECL/TTL Buffer
VCLKOUT VCLKOUT
S0/CLK Decode Logic S1/DATA Serial Program Register Selects
AAAAAAAAAAAAAAAAAAAAAAAAA CNTL DIVREG (Reserved) MREG REG2 REG1 REG0 AAAAAAAAAAAAAAAAAAAAAAAA
Divide Register Register File
Synch LDA/4
LDA/2
4-21 Serial ERROUT
Addr ENABLE
INIT1 INIT0 Initialization AVDD
Power-On Reset
Power-On Reset State Machine
Note: ENABLE then synch. copy LDA, else
ICD2062B
Summary
Name S0/CLK S1/DATA AVDD XTALIN[2] XTALOUT[2] MCLKOUT VCLKOUT Number Description (LSB) frequency select logic, used select output frequencies. Clock Input serial programming mode. (Internal pull-down allows no-connect.) (MSB) frequency select logic, used select output frequencies. Data Input serial programming mode. (Internal pull-down allows no-connect.) Analog Core Output Enable three-states output when signal (pin internal pull-up.) Ground Reference Oscillator input phase-locked loops (nominally from parallel-resonant 14.31818 crystal). Optionally System Clock. Oscillator Output reference crystal. (Pin no-connect external reference oscillator System clock signal used.) Memory Clock output Differential clock outputs. Connect directly RAMDAC CLOCK inputs. drive RAMDACs. Output levels equivalent circuit operating from single supply. VCLKOUT skew-free. Differential clock outputs. Connect directly RAMDAC CLOCK inputs. drive RAMDACs. Output levels equivalent circuit operating from single supply. VCLKOUT skew-free. Error Output: signals error during serial programming. Ground Select power-up initial conditions (LSB) (Internal pull-down allows no-connect.) Ring Load output (TTL compatible). When ENABLE HIGH, same timing output. drive capacitive loads without buffering. Select power-up initial conditions (MSB) (Internal pull-down allows no-connect.) Skew-free Load Outputs (TTL compatible). Generated dividing VCLKOUT Register Each output drive capacitive loads without buffering. Generated dividing two. Generated dividing four. Synchronous load enable input. Internally synched LDA, used start/stop output synchronously. ENABLE LOW, held LOW; when HIGH, free-running.
VCLKOUT
ERROUT INIT0 INIT1 LDA/2 LDA/4 ENABLE
Note: best accuracy, parallel-resonant crystal, assume CLOAD=17
Register Definitions
Register File Register File consists following registers their selection addresses:
Table Register Addressing Address Register REG0 REG1 REG2 MREG (Reserved) DIVREG CNTL Load Divisor Register Control Register Usage Video Clock Register Video Clock Register Video Clock Register Memory Timing Clock
ICD2062B
Register Selection Video Clock output controlled only bits, also signal shown Table
Word, appropriate output signal will multiplexed reference signal f(REF) extra timeout interval (See Switching Characteristics further details). Control Register Definition
Table VCLKOUT Selection VCLKOUT High-Z REG0 REG1 REG2
Control Register (CNTL Reg) allows user adjust various internal options. Most these options special cases, should have applicability standard graphics usage. register word defined Figure MUXREF-This control determines which clock multiplexed VCLKOUT output during frequency changes. While VCLK changes different frequency, known clock multiplexed output. default multiplex f(REF) reference frequency, some graphics controllers cannot slow f(REF). This bit, when set, allows MCLK used alternative frequency. Timeout Interval-The timeout interval normally defined Switching Characteristics. derived from MCLK VCO, this programmed certain extremes, then timeout short. this control set, then timeout interval doubled. RAMDAC Reset-This control bit, when set, will cause ICD2062B issue RAMDAC reset sequence, which required some specific RAMDACs (such Bt457/458). more specifics this operation, refer section Internal RESET Sequence. NOTE: This operation will only take place first time this set. Duty Cycle Adjust-This control causes decrease output waveform high time. default adjustment. situations which capacitive load beyond device specifications, where threshold voltage changed from CMOS levels, this adjustment sometimes bring output closer duty cycle. VCLKOUT Pad-This control determines whether VCLKOUT levels. default levels. When mode, VCLKOUT nonfunctional, remains three-stated.
Memory Clock output controlled signal indicated Table Table MCLKOUT Selection VCLKOUT High-Z MREG
Clock Select pins have dual purpose. When these pins performing serial download, VCLKOUT signal remains unchanged (unless currently selected register being programmed). When pins functioning register selects, timeout interval required determine whether user desires register select serial programming. timeout interval, register selection occurs. this point, VCLKOUT signal will multiplexed reference signal f(REF) additional timeout interval allow settle value. (The timeout interval both cases approximately msec-see timeout interval spec Switching Characteristics.) When frequency being MCLK, active VCLK register being programmed, then glitch-free multiplexing Reference Frequency performed. Once STOP sent after MCLK active VCLK Programming Reserved (Must MUXREF Multiplex f(REF) VCLKOUT- Default Multiplex MCLKOUTto VCLKOUT Timeout Interval Normal Timeout Interval -Default Twice Normal Timeout Interval RAMDAC Reset Reset Command- Default Reset RAMDAC Duty Cycle Adjust high-timedecrease adjust- Default VCLKOUT Output Levels Output Levels- Default
Counter Prescale (Reg0) Prescale=2 -Default Prescale=4 Counter Prescale (Reg1) Prescale=2 -Default Prescale=4 Counter Prescale (Reg2) Prescale=2 -Default Prescale=4
Figure Control Register Definition
ICD2062B
Counter Prescale (REG0, REG1, REG2)-These control bits determine whether prescale Counter value, which allows fine tuning output frequency respective register. Prescaling explained more detail later this datasheet. Divide Register Definition output signals LDA, LDA/2, LDA/4, function VCLK value divided division factor stored Divide Register (DIVREG). maximum output MHz. Table DIVREG Division Factors Division Clock Clock HIGH Device Factor (cycles) (cycles) Version B[3] Block (see Figure contains several components: Serial Unlock Decoder (containing unlocking mechanism Manchester decoder), watchdog timer, Serial Data register Demultiplexer Register File. Unlocking Mechanism Unlocking Mechanism watches initial break sequence, detailed Figure initial unlock sequence consists least five LOW-to-HIGH transitions with DATA HIGH, followed immediately single LOW-to-HIGH transition with DATA LOW. Following this unlock sequence, encoded serial data clocked into Serial Data register (Serial Reg). Watchdog Timer Following transition DATA, watchdog timer reset begins counting. Throughout entire programming process, watchdog timer ensures that successive edges DATA violate timeout specification msec-see Switching Characteristics.) timeout does occur, lock mechanism rearmed current data Serial Data register ignored. Since VCLK registers selected bits, since change their state affect resultant output frequency, data input Selection Bits only permitted pass through Decode Logic after Watchdog Timer timed out. This delay data permits serial program cycle take place without affecting current register selection. process serial programming effect performance graphics subsystem. Note that there latency amounting duration Watchdog Timer before VCLK register selections take effect.
Note: Default power-up.
Serial Programming Architecture
ICD2062B programming scheme simple, impenetrable accidental access. Because only common denominator between most 8514 controllers clock select pins, these have perform dual functions clock selection serial programming. Serial Program
ERROUT Serial Unlock Decode Logic Serial Data Register DEMUX Man. Decoder (Address Data) Dcdr. Load/Arm Select Load Request Register File Reference Frequency Watchdog Timer f(REF)
ICD2062B-1
Figure Serial Programming Block Diagram-Detail
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAA
AAAAAAAAAAAAAAAA S1/DATA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA S0/CLOCK AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
ICD2062B-2
Figure Unlock Sequence
ICD2062B
Register Initialization ICD2062B Clock Synthesizer registers known state upon power-up. This implemented Power-On initialization circuitry. Three pixel clock registers Memory Clock register initialized based state INIT1 INIT0 pins power-up. power-on, when supply voltage rises above certain threshold voltage (typically vary with temperature), part recognizes first rising edges reference clock, using them clocking signal internal state machines initialization. Hence proper initialization programmability, power-on reference clock pulses seen ICD2062B, should have good signal integrity rail-to-rail characteristics clock pulses seen under stable working conditions. This issue when using crystal reference. Power-On Reset function operates transparently video subsystem. performs initialization function cleared before system Power-On Reset permits system begin boot process. INIT pins must ramp with either these pins desired. They internally pulled down, will default left unconnected. various registers initialized shown Table (all frequencies MHz). Table Register Initialization INIT1 INIT0 MREG 32.500 40.000 50.350 56.644 REG0 25.175 25.175 110.000 110.000 REG1 28.322 28.322 135.000 135.000 REG2 28.322 28.322 165.000 185.000 Set-Up Hold Time requirements must both edges. unlock sequence, start, stop bits Manchester-encoded. specifics timing, "Serial Programming Timing" section switching waveforms. bits shifted this order: start bit, data bits, address bits (which designate desired register), stop (which also functions load strobe transfer data from Serial into desired register). registers (REG0, REG1, REG2, MREG), data made fields: D[20:17] Index; D[16:10]=P'; D[9:7]=Mux; D[6:0]=Q'. (See Programming ICD2062B section more details data word.) other registers with fewer than bits (DIVREG, CNTL Reg), upper bits used (starting with MSB). total bits must always loaded into Serial Data register error issued). Undefined bits should always zero maintain software compatibility with future enhancements. Following entry last data bit, stop Load command issued bringing DATA HIGH toggling HIGH-to-LOW LOW-to-HIGH. unlocking mechanism then automatically rearms itself following load. Only when watchdog timer timed selection pins permitted return their normal register select function. Note that Serial Data register that receives address data bits exactly correct length accept data being sent. stop used load command that passes Serial Data contents register file location indicated address bits. stop received after Serial Data register been filled, rather more valid encoded data received, then received serial data ignored, unlocking mechanism rearmed, error issued. device counts serial data clock edges know exactly when serial buffer full, thus know which stop bit. Following stop bit, unlocking mechanism rearms itself. corrupt data detected (i.e., incorrectly Manchester-encoded data), then unlocking mechanism rearmed, serial counter reset, received data ignored, ERROUT asserted. ERROUT Operation ERROUT signal used announce when program error been detected internally ICD2062B. signal remains until next unlock sequence.
Address Bits Stop Prog. CNTL DIVREG
Serial Data Register Serial data clocked into Serial Data register order shown Figure serial data sent using modified Manchester-encoded data format. This defined individual data sampled rising edge CLK. complement data must sampled previous falling edge CLK.
Data Bits Start AAAA AAAA AAAA AAAA AAAA
Prog. Word CNTL
DIVREG
ICD2062B-3
Figure Serial Data Timing
ICD2062B
DATA DFF1 DFF2 valid data
ICD2062B-4
Table Post-VCO Divisor Divisor
DFF3 ERROUT
Figure Modified Manchester Decoder Circuit
Figure shows basic mechanism used detect erroneous serial data. Note that circuit must have different values rising falling edge when sampling falling edge first. Valid data read rising edge CLK.
ERROUT signal invoked following error conditions: incorrect start bit, incorrect Manchester encoding; incorrect length data word; incorrect stop bit. Note that there input available target controller chip monitor ERROUT, software routine which counts VSYNC pulses order measure output frequency used determination programming success.
Index Field used preset appropriate range. value this field should chosen from Table (This table referenced frequency, f(VCO), rather than desired output frequency.) Note that VCLK shut off, that MCLK must left running. When Index Field 1111, VCLK turned both channels from same MCLK VCO. reduce jitter, VCOs should integral multiples each other; therefore, allow output clocks (n=0, multiples each other, turn VCLK multiplex MCLK over VCLKOUT, dividing down desired frequency. This will significantly reduce heterodyne jitter. desired frequency lies boundary table-in other words, exactly upper limit entry lower limit next-then either index value used (since both limits tested) higher value should used. assist with these calculations, Cypress/IC Designs provides BitCalc (Part #ICD/BCALC), Windowsprogram that automatically generates appropriate programming words from user's reference input desired output frequencies, well assembling program words such things control power-down registers. Table Index Field VCLK fVCO (MHz) 65.0 70.7 70.7 77.8 77.8 85.6 85.6 88.0 88.0 94.2 94.2 96.8 96.8 106.5 106.5 111.7 111.7 117.2 117.2 122.8 122.8 135.1 135.1 148.6 148.6 160.0 160.0 165.0 Turn VCLK MCLK VCLK MCLK fVCO (MHz) Reserved 52.0 55.0 55.0 60.0 60.0 68.0 68.0 70.0 70.0 75.0 75.0 80.0 80.0 84.5 84.5 90.0 90.0 95.0 95.0 100.0 100.0 104.0 104.0 110.0 110.0 120.0 110.0 120.0 110.0 120.0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Programming ICD2062B
desired output frequency defined serial interface, with 21-bit number shifted ICD2062B programmable oscillators, requiring 21-bit programming word loaded into each channel's respective registers independently. This word contains fields, shown Table Table Programming Word Fields Field Index Counter value (P') Counter value (Q') bits Notes (Most Significant Bits)
(Least Significant Bits)
frequency Programmable Oscillator f(VCO) determined these fields follows: P'=P-3 Q'=Q-2 f(VCO)=(2 f(REF) P/Q) where f(REF)=Reference frequency (typically 14.31818 MHz) Note that reference frequency other than 14.31818 used, then initially loaded frequencies will correct. value f(VCO) must remain between minimum maximum frequency. These limits vary depending clock (MCLK VCLK). Table actual boundary frequencies each case. output frequencies below minimum, f(VCO) must brought into range. accomplish this, post-VCO divisor selected setting values field (M). Table
ICD2062B
Programming Constraints There five primary programming constraints which user must aware: Table Programming Constraints Parameter f(REF) f(REF)/Q f(VCO) Minimum VCLK: MCLK: Maximum VCLK: MCLK: Table Prescale Values Actual Frequency Prescale (MHz) 99.84028 99.99998 Error (PPM) 1600 Programming Example-Prescaling=4 Assume desired VCLKOUT frequency MHz. Table compares results using default prescaling value optional prescaling value
constraints have with trade-offs between optimum speed with lowest noise, stability, factors affecting loop equation. factors listed here completeness' sake; however, using BitCalc program, these constraints become transparent. Programming Example-Prescaling=2 (default) following example calculations BitCalc performs: Derive proper programming word 39.5 VCLK output frequency, using 14.31818 reference frequency: Since 39.5 MHz<50 MHz, double 79.0 MHz. 001. 0010. result: f(VCO)=79.0=(2 14.31818 P/Q) 2.7587 Table Value Pairs f(VCO) (MHz) 79.0363 78.9969 78.9669 Error (PPM)
this precision price, namely that user reset Prescale Bits PS0-2 (corresponding REG0-2), which involves loading Control Word (taking care preserve current values other Control Bits), before Program Word loaded. Once appropriate Prescale Bits set, then frequency programming proceed before, unless until desired program frequency without prescaling, which point Control Word must first loaded with proper bits set, observing precautions noted above. summarize, sequence Prescale bits (load Control Word) Program (load Program Word) Note that care must taken change Prescale currently active register: results will unpredictable best, could cause lock.
RAMDAC/VRAM Interface
Interfacing RAMDAC
Figure shows interface ICD2062B RAMDAC. part should located close RAMDAC possible. Termination resistors needed VCLKOUT outputs, should located close possible RAMDAC. specific information, please refer Cypress/IC Designs application note Outputs.
ICD2062B drive CLOCK inputs four RAMDACs, they located physically adjacent each other. this case, only sets termination resistors should used, these should located closest farthest RAMDAC from ICD2062B. Typical ICD2062B Usage DIVREG register holds divisor, which which pixel clock divided generate load signals: LDA, LDA/2, LDA/4. ENABLE input synchronized internally LDA; used start stop output synchronously. When ENABLE LOW, held LOW. When ENABLE HIGH, then will free-running phase with LDA. This allows video DRAM shift registers non-clocked during retrace intervals. Note that fanouts greater than needs buffered.
Choose Q)=(80,29) best accuracy PPM). Therefore: P'=P-3=80-3=77=1001101 (4dH) Q'=Q-2=29-2=27=0011011 (1bH) full programming word, obtained concatenating: I=0010, P'=1001101, M=001, Q'=0011011 =001010011010010011011 (05349bH) programming word then sent serial stream, first. Appropriate start stop bits must also included defined Serial Programming Architecture section.
ICD2062B
VCLKOUT ICD2062B VCLKOUT 14.31818 XTALIN CLOCK CLOCK RAMDAC
XTALOUT
ICD2062B-5
Figure ICD2062B RAMDAC Interface Example
VSYNC Control Signals Controller HSYNC BLANK
VRAM
Delay BLANKRAMDAC
ICD2062B Register Selects Serial Interface
MCLKOUT LDA/2 VCLKOUT
RAMDAC 4-bit/8-bit
ENABLE
CLOCK CLOCK
ICD2062B-6
VCLKOUT
Figure ICD2062B Typical Interface Circuit
ICD2062B
BLANK Video Data (Load Clock) (Shift Clock) VCLKOUT (Pixel Clock) frequency times (ICD2062A) frequency times (ICD2062B) ENABLE
BLANKRAMDAC
ICD2062B-7
Figure Timing Diagram Interface Circuit Internal RESET Sequence internal RESET signal allows ICD2062B RAMDAC pipeline delay specific cycle count, depending RAMDAC. Reset takes place first time Control Register's Reset set. Following rising edge LDA/4 after Reset set, VCLKOUT VCLKOUT outputs stopped HIGH LOW, respectively; next rising edge LDA/4, these outputs again allowed free-running. Figure shows operation internal RESET signal.
CLOCK (free-running)
LDA/4
INTERNAL RESET
VCLKOUT
VCLKOUT
ICD2062B-8
Figure Internal RESET Timing
ICD2062B
Power Management Issues
Estimating Total Current Drain Actual current drain function frequency circuit loading. operating current given output given equation: where I=current, C=load capacitance (max. pF), V=output voltage (usually pads, 1.5V pads), f=output frequency MHz). calculate total operating current, following: MCLKOUT VCLKOUT VCLKOUT LDA/2 LDA/4 f(MCLKOUT) f(VCLKOUT); (ECL pad, V=1.5V) f(VCLKOUT); (ECL pad, V=1.5V) f(LDA) f(LDA/2) f(LDA/4) Internal f(LDC)
This gives approximation actual operating current. unconnected output pins, assume loading, depending package type. Table Typical Values Frequency HIGH HIGH Capacitive Load HIGH Current (mA)
Output Enable
When asserted (active HIGH), output pins except XTALOUT ERROUT enter high-impedance mode, support automated board testing.
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Supply Voltage Ground Potential .-0.5V +7.0V Input Voltage .-0.5V +0.5V Storage Temperature -65°C +150°C soldering temperature sec) 260°C Junction temperature. 125°C
Operating Range
Ambient Temperature TAMBIENT 70°C AVDD
Electrical Characteristics Over Operating Range[4]
Parameter VOH(ECL) VOL(ECL) VOH(TTL) VOL(TTL) IDD-TYP COUT(ECL) Description Output HIGH Voltage[5] Voltage[6] -4.0mA Except Crystal Pins Except Crystal Pins VDD-0.5V 0.5V Three-state outputs A/B, Inputs Typical= -250 150/200 Test Conditions Min. VDD-1.0 VDD-2.0 Max. VDD-0.8 VDD-1.6 Unit
Output Voltage Output HIGH
Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Output Leakage Current Power Supply Current Power Supply Current Output Capacitance
Notes: Input capacitance typically except crystal pins. outputs: VCLKOUT, VCLKOUT. outputs: MCLKOUT, LDA, LDA/2, LDA/4, LDC, ERROUT.
ICD2062B
Switching Characteristics Over Operating Range
Parameter f(REF) Name Description Min. Typ. 14.318 Max. Unit Reference Frequency Reference Oscillator nominal value (Note: references other than 14.318 MHz, pre-loaded frequencies will accurate.) Reference Clock Period Input Duty Cycle Output Clock Periods Output Clock Periods Output Duty Cycle Rise Times Fall Times f(REF) Duty cycle inputs defined Output values Output values Duty cycle outputs[7] Rise time outputs into 25-pF load Fall time outputs into 25-pF load Skew between VCLKOUT complementary outputs freq1 Output freq2 Output f(REF) Time Timeout Interval tfreq2 Time Three-state Valid Load Clock Period frequency output frequency output Time clock output remains HIGH while output muxes reference frequency Internal interval serial programming changes settle[8] Time clock output remains HIGH while output muxes frequency value Time outputs into three-state mode after signal assertion Time outputs recover from three-state mode after signal goes HIGH Maximum period VCLKOUT output skew LDA/2 output skew LDA/4 output skew output skew ENABLE set-up time ENABLE hold time Clock period serial clock Minimum HIGH time serial clock Minimum time serial clock Set-Up time Hold time Load command t(REF)/2 tfreq2/2 t(REF) t(REF) t(REF) t1+30 3(t(REF)/2) 3/(tfreq2/2) msec msec
t(REF) tskew-ECL tfreq1 tfreq2 ttimeout tSKEW-LDA tSKEW-LDA/2 tSKEW-LDA/4 tSKEW-LDC tEN-SU tEN-HD tserclk tldcmd
1000 1970 1970
Notes: non-ECL outputs, duty cycle measured CMOS threshold levels. VTH=2.5V. interval short, Timeout Interval section Control register definition.
ICD2062B
Switching Waveforms
Duty Cycle Timing
ICD2062B-9
Rise Fall Times
t(REF) XTALIN f(REF)
VCLKOUT MCLKOUT
tskew-ECL
VCLKOUT
ICD2062B-10
Three-State Timing
VCLKOUT MCLKOUT
THREE-STATE OUTPUT
ICD2062B-11
Selection Timing
Selection Recognition Time ttimeout (Internal Timeout)
Settle Time
ttimeout
VCLKOUT tfreq1
Frequency
t(REF)
tfreq2
ICD2062B-12
ICD2062B
Switching Waveforms (continued)
MCLK Active VCLK Register Programming Timing
StopBit
Settle Time
ttimeout
(Internal Timeout)
VCLKOUT MCLKOUT tfreq
Frequency
t(REF) (ort MCLK CNTL Reg)
tfreq
ICD2062B-13
RAMDAC/VRAM Interface Timing
VCLKOUT tSKEW-
LDA/2 tSKEW-LDA/4 LDA/4 tSKEW- tEN- ENABLE
ICD2062B-14
Serial Programming Timing
Unlock Sequence DATA
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tserclk
Start
ValidDataSequence(24bits) DATA
Stop
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tldcmd
ICD2062B-15
ICD2062B
Test Circuit
DEVICE UNDER TEST
CLOAD
AVDD Tantalum
Ordering Information[9]
Ordering Code ICD2062B Package Name Package Type 20-Pin SOIC Operating Range Commercial[10]
Notes: Please call your local Cypress representative. +70°C
Example: order ICD2062BSC-2 ICD2062B, 20-pin plastic SOIC, commercial temperature range device with Video Clock frequency range MHz. Document 38-00404-A
Package Diagram
20-Lead (300-Mil) Molded SOIC
Cypress Semiconductor Corporation, 1997. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
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