3501 ICD2061A Dual Programmable Graphics Clock Generator

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

3501 ICD2061A Dual Programmable Graphics Clock Generator

Datasheet Thumbnail

Top Searches for this datasheet

CD20
3501
ICD2061A
Dual Programmable Graphics Clock Generator
Features
Second generation dual oscillator graphics clock generator independent clock outputs from Individually programmable oscillators using highly reliable, Manchester-encoded, 21-bit serial data word 2-pin serial programming interface allows direct connection most graphics chip sets with external hardware required advanced power-down capabilities Three-state oscillator control disables outputs test purposes Phase-locked loop oscillator input derived from single 14.318 crystal Sophisticated internal loop-filter requires external components manufacturing "tweaks" commonly required with external filters operation Low-power, high-speed CMOS technology Available 16-pin SOIC package configuration clock chips, while also offering versatility serially programmable frequency synthesizers. features advanced power-down capabilities, making ideally suited portable computer market. ICD2061A extended frequency range improved voltage/temperature stability when compared first-generation frequency synthesizers. ICD2061A Dual Programmable Graphics Clock Generator offers fully user-programmable phase-locked loops single package. outputs changed fly" desired frequency value between MHz. ICD2061A ideally suited design where multiple varying frequencies required, replacing more expensive metal oscillators. Being able change output frequency dynamically adds whole degree freedom electrical engineer which previously unavailable with existing crystal oscillator devices. Some examples uses this device include: laptop computers, which slowing speed operation mean less power consumption speeding mean faster operation; graphics board clocks allow dynamic synchronization with different brands monitors display formats; on-board test strategies where ability skew system's desired frequency (for example: ±10%) allows worst case evaluations. While primarily designed graphics subsystem market, programming versatility ICD2061A makes ideal wherever variable, highly accurate clock sources required.
Functional Description
ICD2061A Dual Programmable Graphics Clock Generator features fully programmable clock oscillators which handle frequency requirements most graphics systems. ICD2061A offers selection ease ROM-based
Configuration
S0/CLK S1/DATA AVDD XTALIN XTALOUT MCLKOUT
SOIC View
PWRDWN INTCLK INIT1 INIT0 FEATCLK ERROUT VCLKOUT ICD2061A-1
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134 408-943-2600 June 1994 Revised July 1997
ICD2061A
Logic Block Diagram
Powerdown Divisor
MCLKOUT f(REF) XTALIN XTALOUT Reference Frequency VCLK VCLKOUT MCLK
(Typically 14.31818 Xtal) FEATCLK
PWRDWN INTCLK S0/CLK S1/DATA Decode Logic Serial Program Register Selects Addr INIT1 INIT0 Initialization AVDD Register File CNTL
(Reserved) PWRDWN MREG REG2 REG1 REG0 4-21 Serial ERROUT
Power-On Reset
Power-On Reset State Machine
ICD2061A
Summary
Name S0/CLK S1/DATA AVDD XTALIN[1] XTALOUT[1] MCLKOUT VCLKOUT ERROUT FEATCLK INIT0 INIT1 INTCLK PWRDWN Number Description (LSB) frequency select logic, used select oscillator frequencies. Clock Input serial programming mode. (Internal pull-down allows no-connect.) (MSB) frequency select logic, used select oscillator frequencies. Data Input serial programming mode. (Internal pull-down allows no-connect.) Analog Core Output Enable. Three-states output when pulled LOW. (Internal pull-up allows connect.) Ground Reference Oscillator input phase-locked loops (nominally from parallel-resonant 14.31818 crystal). Optionally System Clock. Oscillator Output reference crystal. (Pin no-connect external reference oscillator System clock signal used.) Memory Clock output Video Clock output Error Output: signals error during serial programming. External clock input (Feature Clock) (Internal pull-up allows no-connect.) Select power-up initial conditions (LSB) (Internal pull-down allows no-connect.) Ring Select power-up initial conditions (MSB) (Internal pull-down allows no-connect.) Selects Feature Clock external clock input VCLKOUT output (Internal pull-up allows no-connect.) Power-down (active LOW) (Internal pull-up allows no-connect power-down operation required. Power Management Issues specific details concerning this pin.)
Note: best accuracy, parallel-resonant crystal, assume CLOAD=17
Register Definitions
Register File consists following registers their selection addresses: Register File Table Register Addressing[2] Address Register REG0 REG1 REG2 MREG PWRDWN (Reserved) CNTL Control Register Usage Video Clock Register Video Clock Register Video Clock Register Memory Timing Clock Divisor Power-Down mode
power-on, when supply voltage rises above certain threshold voltage (typically vary with temperature), part recognizes first rising edges reference clock, using them clocking signal internal state machines initialization. Hence proper initialization programmability, power-on reference clock pulses seen ICD2061A, should have good signal integrity rail-to-rail characteristics clock pulses seen under stable working conditions. This issue when using crystal reference. Power-On Reset function operates transparently video subsystem. performs initialization function cleared before system Power-On Reset permits system begin boot process. INIT pins must ramp with either these pins desired. They internally pulled down, will default left unconnected. various registers initialized follows Table (all frequencies MHz). Table Register Initialization-ROM Option INIT1 INIT0 MREG 32.500 40.000 50.350 56.644 REG0 25.175 25.175 40.000 40.000 REG1 28.322 28.322 28.322 50.350 REG2 28.322 28.322 28.322 50.350
Note: register values preserved power-down mode.
Power-On Reset Register Initialization ICD2061A Clock Synthesizer registers known state upon power-up. This implemented Power-On initialization circuitry. Three registers Memory Clock register initialized based state INIT1 INIT0 pins power-up.
ICD2061A
Power-Down Mode Power-Down Mode1 Default (MCLKOUT= PWRDWNDivisor) Power-Down Mode (Xtal shutdown) MUXREF Multiplex f(REF) VCLKOUT Default Multiplex MCLKOUTto VCLKOUT Timeout Interval Normal Timeout IntervalDefault Twice Normal Timeout Interval Reserved (Must DutyCycleAdjust high-time decrease adjustDefault Reserved (Must Figure Control Register Definition Register Selection Video Clock output controlled only bits, also PWRDWN signals. Additionally, clock synthesizer multiplexed with external frequency input (FEATCLK) which corresponds Feature Clock standard. Table shows VCLKOUT selection criteria. Table VCLKOUT Selection PWRDWN INTCLK VCLKOUT High-Z Forced High REG0 REG1 FEATCLK REG2 REG2 Control Register Definition Control Register (CNTL Reg) allows user adjust various internal options. Most these options special cases, should have applicability standard graphics usage. register word defined Figure Duty Cycle Adjust-This control causes decrease output waveform high time. default adjustment. situations which capacitive load beyond device specifications, where threshold voltage changed from CMOS levels, this adjustment sometimes bring output closer duty cycle. Clock Select pins have dual purpose. When these pins performing serial download, VCLKOUT signal remains unchanged (unless currently selected register being programmed). When pins functioning register selects, time-out interval required determine whether user desires register select serial programming. timeout interval, register selection occurs. this point, VCLKOUT signal will multiplexed reference signal f(REF) additional timeout interval give time settle value. [The timeout interval both cases approximately msec-see timeout interval spec Switching Characteristics.] When frequency being MCLK, active VCLK register programmed, glitch-free multiplexing Reference Frequency performed. Once STOP sent after MCLK active VCLK Programming Word, appropriate output signal will multiplexed reference signal f(REF) extra timeout interval (See Switching Characteristics further details). Counter Prescale (Reg0) Prescale=2 Default Prescale=4 Counter Prescale (Reg1) Prescale=2 Default Prescale=4 Counter Prescale (Reg2) Prescale=2 Default Prescale=4
Memory Clock output controlled PWRDWN signals indicated Table Table MCLKOUT Selection PWRDWN MCLKOUT High-Z MREG PWRDWN[3]
Notes: Power-Down Mode determined setting CNTL Reg. Figure Control Register Definition.
ICD2061A
ERROUT Decode Logic Serial Unlock Decoder Load/Arm Man. Dcdr. Serial Data Register (Address Data) DEMUX Select Load Request Reference Frequency f(REF)
Register File
Watchdog Timer
Figure Serial Programming Block DiagramDetail Timeout Interval-The timeout interval normally defined Switching Characteristics. derived from MCLK VCO, this programmed certain extremes, then timeout short. this control set, then timeout interval doubled. MUXREF-This control determines which clock multiplexed VCLKOUT output during frequency changes. While VCLK changes different frequency, known clock multiplexed output. default multiplex f(REF) reference frequency, some graphic controllers cannot slow f(REF). This bit, when set, allows MCLK used alternative frequency. Power-Down Mode-This control determines which Power-Down Mode PWRDWN will implement. default (Power-Down Mode forces MCLKOUT signal function PWRDWN register. Power-Down Mode turns crystal oscillator disables outputs. There more detailed description section entitled Power Management Issues. Counter Prescale (REG0, REG1, REG2)-These control bits determine whether prescale Counter value, which allows fine tuning output frequency respective register. Prescaling explained more detail various sections this datasheet. mechanism Manchester decoder), watchdog timer, Serial Data register (Serial Reg) Demultiplexer Register File (see Figure Unlocking Mechanism Unlocking Mechanism watches initial break sequence, detailed Figure initial unlock sequence consists least five LOW-to-HIGH transitions with DATA HIGH, followed immediately single LOW-to-HIGH transition with DATA LOW. Following this unlock sequence, encoded serial data clocked into Serial Data register (Serial Reg). Note that ICD2061A serially programmed when Power-Down Mode. Watchdog Timer Following transition DATA, watchdog timer reset begins counting. Throughout entire programming process, watchdog timer ensures that successive edges DATA violate timeout specification msec-see Switching Characteristics.) timeout does occur, lock mechanism rearmed current data Serial Data register (Serial Reg) ignored. Since VCLK registers selected bits, since change their state affect resultant output frequency, data input Selection Bits only permitted pass through Decode Logic after Watchdog Timer timed out. This delay data permits serial program cycle take place without affecting current register selection. process serial programming effect performance graphics subsystem. Note that there latency amounting duration Watchdog Timer before VCLK register selections take effect.
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
Serial Programming Architecture
ICD2061A programming scheme simple, impenetrable accidental access. Because only common denominator between most 8514 controllers clock select pins, these have perform dual functions clock selection serial programming. Serial Program Block (See ICD2061A Logic Block Diagram) contains several components: Serial Unlock Decoder (containing unlocking
AAAAAAAAAAAAAAAA SEL1/DATA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
SEL0/CLOCK
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
Figure Unlock Sequence
ICD2061A
Data Bits Start AAAA AAAA AAAA AAAA AAAA Address Bits Stop Prog. CNTL PWRDWN
Prog. Word CNTL
PWRDWN
ICD2061A-2
Figure Serial Data Timing Serial Data Register serial data clocked into Serial Data register (Serial Reg) following order shown Figure serial data sent using modified Manchester-encoded data format. This defined individual data sampled rising edge CLK. complement data must sampled previous falling edge CLK. Set-Up Hold Time requirements must both edges. unlock sequence, start, stop bits Manchester-encoded. specifics timing, "Serial Programming Timing" section switching waveforms. bits shifted this order: start bit, data bits, address bits (which designate desired register), stop (which also functions load strobe transfer data from Serial into desired register). registers (REG0, REG1, REG2, MREG), data made fields: D[20:17] Index; D[16:10]=P'; D[9:7]=Mux; D[6:0]=Q'. (See Programming ICD2061A section more details data word.) other registers with fewer than bits (PWRDWN, CNTL Reg), upper bits used (starting with MSB). total bits must always loaded into Serial Data Register error issued). Undefined bits should always zero maintain software compatibility with future enhancements. Following entry last data bit, stop Load command issued bringing data HIGH toggling HIGH-to-LOW LOW-to-HIGH. unlocking mechanism then automatically rearms itself following load. Only when watchdog timer timed selection pins permitted return their normal register select function. Note that Serial Data register (Serial Reg) that receives address data bits exactly correct length accept data being sent. stop used load command that passes Serial contents register file location indicated address bits. stop received
after Serial Data register been filled, rather more valid encoded data received, then received serial data ignored, unlocking mechanism rearmed, error issued. device counts serial data clock edges know exactly when serial buffer full, thus know which stop bit. Following stop bit, unlocking mechanism rearms itself. corrupt data detected (i.e., incorrectly Manchester-encoded data), then unlocking mechanism rearmed, serial counter reset, received data ignored, ERROUT asserted. ERROUT Operation ERROUT signal used report when program error been detected internally ICD2061A. signal stays active until next unlock sequence.
Figure shows basic mechanism used detect valid erroneous serial data. Note that circuit must have different values rising falling edge when sampling falling edge first. Valid data read rising edge CLK.
ERROUT signal invoked following error conditions: incorrect Manchester encoding; incorrect length data word; incorrect stop bit; timeout. Note that there input available target controller chip monitor ERROUT, software routine which counts VSYNC pulses order measure output frequency used determination programming accuracy.
DATA
DFF1 DFF2 valid data DFF3 ERROUT
Figure Serial Data Timing
ICD2061A
Programming ICD2061A
desired output frequency defined serial interface, with 24-bit number shifted ICD2061A programmable oscillators, requiring 24-bit programming word loaded into each channel's respective registers independently. This word contains fields: Table Programming Word Fields Field Address Index Counter value Counter Value
Notes: (Most Significant Bits) (Least Significant Bits)
dividing down desired frequency. This will significantly reduce heterodyne jitter. Table Index Field 0000 0001 Bits 4[4] 7[5] 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 VCLK fVCO (MHz) 50.0 51.0 51.0 53.2 53.2 58.5 58.5 60.7 60.7 64.4 64.4 66.8 66.8 73.5 73.5 75.6 75.6 80.9 80.9 83.2 83.2 91.5 91.5 100.0 100.0 120.0 100.0 120.0 Turn VCLK MCLK VCLK MCLK fVCO (MHz) 50.0 51.0 51.0 53.2 53.2 58.5 58.5 60.7 60.7 64.4 64.4 66.8 66.8 73.5 73.5 75.6 75.6 80.9 80.9 83.2 83.2 91.5 91.5 100.0 100.0 120.0 100.0 120./0 100.0 120.0 100.0 120.0
frequency Programmable Oscillator f(VCO) determined these fields follows: P'=P-3 Q'=Q-2 f(VCO)=(2 f(REF) P/Q) where f(REF)=Reference frequency (between MHz-25 MHz; typically 14.31818 MHz) Note that reference frequency other than 14.31818 used, then initially loaded frequencies will correct. value f(VCO) must remain between inclusive. Therefore, output frequencies below f(VCO) must brought into range. accomplish this, post-VCO divisor selected setting values field (D). Table Table Post-VCO Divisor Divisor
desired frequency lies boundary table-in other words, exactly upper limit entry lower limit next-then either index value used (since both limits tested). assist with these calculations, Cypress/IC Designs provides BitCalc (Part #ICD/BCALC), Windowsprogram that automatically generates appropriate programming words from user's reference input desired output frequencies, well assembling program words such things control power-down registers. Programming Constraints There five primary programming constraints which user must aware: Table Programming Constraints Parameter f(REF) f(REF)/Q f(VCO) Minimum VCLK: MCLK: Maximum VCLK: MCLK:
Index Field used preset appropriate range. value this field should chosen from following table. (This table referenced frequency, f(VCO), rather than desired output frequency.) Note that VCLK shut off, that MCLK must left running. When Index Field 1111, VCLK turned both channels from same MCLK VCO. reduce jitter, doesn't want VCOs integral multiples each other; therefore, does want clocks (n=0, multiples each other, this done turning VCLK multiplexing MCLK over VCLKOUT,
constraints have with trade-offs between optimum speed with lowest noise, stability, factors affecting loop equation. factors listed here completeness' sake; however, using BitCalc program, these constraints become transparent.
ICD2061A
Programming Example-Prescaling=2 (default) following example calculations BitCalc performs: Derive proper programming word 39.5 output frequency, using 14.31818 reference frequency: Since 39.5 MHz<50 MHz, double 79.0 MHz. 001. 1000. result:
(VCO)=79.0=(2
14.31818 P/Q)
2.7587 Table Value Pairs f(VCO) (MHz) 79.0363 78.9969 78.9669 Error (PPM)
this precision price, namely that user reset Prescale Bits PS0-2 (corresponding REG0-2), which involves loading Control Word (taking care preserve current values other Control Bits), before Program Word loaded. Once appropriate Prescale Bits set, then frequency programming proceed before, unless until desired program frequency without prescaling, which point Control Word must first loaded with proper bits set, observing precautions noted above. summarize, sequence Prescale bits (load Control Word) Program (load Program Word) Note that care must taken change Prescale currently active register: results will unpredictable best, could cause lock.
Choose Q)=(80,29) best accuracy PPM). Therefore: P'=P-3=80-3=77=1001101 (4dH) Q'=Q-2=29-2=27=0011011 (1bH) full programming word, W=I, Q'=1000, 1001101, 001, 0011011 =100010011010010011011 (11349bH) programming word then sent serial stream, first. Appropriate start stop bits must also included defined Serial Programming Scheme section. Programming Example-Prescaling=4 Assume desired VCLKOUT frequency MHz. Table compares results using default prescaling value optional prescaling value Table Prescale Values Prescale Actual Frequency (MHz) 99.84028 99.99998 Error (PPM) 1600
Power Management Issues
Power-Down Mode ICD2061A contains mechanism reduce quiescent power when stand-by operation desired. Power-Down Mode (invoked pulling, PWRDWN signal having proper CNTL zero), both VCOs shut down, VCLKOUT output forced high, MCLKOUT output user-defined low-frequency value refresh dynamic RAM. power-down MCLKOUT value determined following equation: Divisor Value) Power-Down register divisor determined according following 4-bit word programmed into PWRDWN register. (See Table 11.)
ICD2061A
Table PWRDWN Register Programming PWRDWN bits PWRDWN Register Value Power-Down Divisor (default) MCLKOUT Power-Down (f(REF)=14.31818 MHz) 447.4 477.3 511.4 550.7 596.6 650.8 715.9 795.5 894.9 1.023 1.193 1.432 1.790 2.386 3.580 VCLKOUT f(VCLK) MCLKOUT-> f(MCLK) Internal ->12 This gives approximation actual operating current. unconnected output pins, assume loading, depending package type. Table Typical Values Frequency HIGH HIGH Capacitive Load HIGH Current (mA)
power-up, value PWRDWN Register loaded with default value (1000 binary), which yields MCLKOUT frequency (14.31818/18). default mode Power-Down Mode Note that ICD2061A serially programmed when Power-Down Mode. Power-Down Mode there need output during power-down operation, then alternate Power-Down Mode available, which will completely shut down outputs reference oscillator, still preserve register contents. This results absolute least power consumption. Power-Down Mode invoked first programming power-down CNTL Reg, then pulling PWRDWN LOW. PWRDWN This standard internal pull-up during normal operation. When user pulls down invoke Power-Down Mode normal pull-up resistor dynamically switched weak pull-up, which significantly reduces power consumption. after pulling this LOW, allowed float, weak pull-up will gradually cause signal rise, enabling normal pull-up, will eventually turn device back Estimating Total Current Drain Actual current drain function frequency circuit loading. operating current given output given equation: where: I=current C=Load capacitance (max., 25pF) V=output voltage (usually f=output frequency MHz) calculate total operating current, following terms:
When Power-Down Mode using 14.31818 reference crystal, power consumption should exceed Power-Down Mode power consumption should exceed
Output Enable
When asserted (active LOW), output pins except XTALOUT ERROUT enter high-impedance mode, support automated board testing.
External Clock Input (Feature Connector Compatibility)
maintain backward compatibility feature connector standard, video clock output VCLKOUT multiplex between clock synthesizer output external clock input FEATCLK. This multiplexing controlled INTCLK input signal appropriate decode selection signals (SEL0, SEL1). section Register Definitions more information.
ICD2061A
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Supply Voltage Ground Potential .-0.5V +7.0V Input Voltage -0.5V +0.5V Storage Temperature -65°C +150°C soldering temperature sec) 260°C Junction temperature. 125°C
Operating Range
Ambient Temperature TAMBIENT 70°C AVDD
Electrical Characteristics Over Operating Range[6]
Parameter IADD IPD1 IPD2 Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Output Leakage Current Supply Current Analog Power Supply Current Power-Down Current (Mode Power-Down Current (Mode Test Conditions -4.0mA Except Crystal Pins Except Crystal Pins +0.5V (Three-state) Inputs 105.0 -250.0 85.0 Min. Max. Unit
Note: Input capacitance typically 10pF, except crystal pins.
ICD2061A
Switching Characteristics Over Operating Range
Parameter f(REF) t(REF) tfreq1 tfreq2 ttimeout tserclk tldcmd Name Reference Frequency Reference Clock Period Input Duty Cycle Output Clock Periods Output Duty Cycle Rise Times Fall Times freq1 Output freq2 Output f(REF) Time Timeout Interval tfreq2 Time Three-state Valid Power-Down Power-Up MCLKOUT HIGH MCLKOUT delay t(REF) 1/f(REF) Duty cycle inputs defined Output values Duty cycle outputs defined t2[7] Rise time outputs into 25-pF load Fall time outputs into 25-pF load frequency output frequency output Time clock output remains HIGH while output muxes reference frequency Internal interval serial programming changes settle[8] Time clock output remains HIGH while output muxes frequency value Time outputs into three-state mode after signal assertion Time outputs recover from three-state mode after signal goes HIGH Time Power-Down Mode operation take effect Time recovery from Power-Down Mode operation Time MCLKOUT HIGH after PWRDWN asserted HIGH Delay MCLKOUT prior fMCLK signal output Clock period serial clock Minimum HIGH time Minimum time Set-Up time Hold time Load command tMCLK/2 t(REF) t(REF) t(REF) t(REF)+30 t(REF)/2 tfreq2/2 3(t(REF)/2) 3/(tfreq2/2) tPWR-DWN 3/(tMCLK/2) msec msec Description Reference Oscillator nominal value Min. Max. 1000 2564 Unit
Notes: Duty cycle measured CMOS threshold levels. VTH=2.5V. interval short, Timeout Interval paragraph.
ICD2061A
Switching Waveforms
Duty Cycle Timing
ICD2061A-3
Rise Fall Times
t(REF) XTALIN f(REF)
VCLKOUT MCLKOUT
ICD2061A-4
State Timing
VCLKOUT MCLKOUT
THREE-STATE OUTPUT
ICD2061A-5
Selection Timing
Selection Recognition Time SEL0 SEL1 ttimeout (Internal Timeout) ttimeout Settle Time Frequency
VCLKOUT tfreq1 t(REF) tfreq2
ICD2061A-6
ICD2061A
Switching Waveforms (continued)
MCLK Active VCLK Register Programming Timing
Stop Settle Time Frequency
ttimeout (Internal Timeout)
VCLKOUT MCLKOUT tfreq t(REF) tfreq
ICD2061A-7
Soft Power-Down Timing(Mode
PWRDWN This when VCLKOUT directly muxes VCLKPLL (may glitch)
VCLKOUT fVCLK
(forced HIGH) fVCLK
MCLKOUT fMCLK fPWRDWN (value from PWRDWN Register) fMCLK
ICD2061A-8
Serial ProgrammingTiming
Unlock Sequence DATA
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tserclk
Start
Valid Data Sequence bits) DATA
Stop
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tldcmd
ICD2061A-9
Note: takes msec after Soft Power-Down guarantee lock VCLKOUT MCLKOUT PLLs.
ICD2061A
Test Circuit
DEVICE UNDER TEST
CLOAD
AVDD
Ordering Information[10]
Ordering Code ICD2061A Package Name Package Type 16-Pin SOIC Operating Range Commercial[11]
Notes: Please call your local Cypress representative. +70°C
Example: order ICD2061ASC-1 ICD2061A, 16-pin plastic SOIC, commercial temperature range device with initial frequencies shown Table
Document 38-00403-A
ICD2061A
Package Diagrams
16-Lead Molded SOIC
Cypress Semiconductor Corporation, 1997. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

3501 ICD2061A Dual Programmable Graphics Clock Generator

Top Searches for this datasheet

Other recent searches