3512 ICD2051 Dual Programmable Clock Generator Features

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3512 ICD2051 Dual Programmable Clock Generator Features

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CD20
3512
ICD2051
Dual Programmable Clock Generator
Features
independent clock outputs ranging from Individually programmable PLLs 22-bit serial word Low-skew ÷1,÷2, CLKA outputs Phase-locked loop oscillator input derived from external low-frequency reference clock MHz) external crystal MHz) Sophisticated internal loop-filter requires external components manufacturing tweaks commonly required with external filters Three-state control disables outputs test purposes (optional) operation Low-power, high-speed CMOS technology Available 16-pin SOIC package
Functional Description
ICD2051 Programmable Clock Generator offers fully user-programmable phase-locked loops single package. outputs changed fly" desired frequency value between MHz. ICD2051 ideally suited design where more multiple varying frequencies required, thus replacing more expensive metal oscillators. capability dynamically change output frequency adds whole degree freedom electrical engineer. Some examples uses this device include: laptop computers, which slowing speed operation mean less power consumption speeding mean faster operation; graphics board clocks allow dynamic synchronization with different brands monitors display formats; on-board test strategies where ability skew system's desired frequency (for example ±10%) allows worst case evaluations.
Logic Block Diagram
f(REF) XTALIN Phase Detector Charge Pump
XTALOUT
Internal Loop Filter post-VCO divider select
µCode Decode
range select Phase-Locked Loop Oscillator Section
MUXREFA
CLKA
CLKA/2 CLKA/4 XBUF
SectionB SCLKA DATA SCLKB MUXREFB Serial Rcvr
CLKB
Serial Rcvr
ICD2051-1
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134 408-943-2600 January 1995 Revised April 1995
ICD2051:1/95
Revision: April 1995
ICD2051
Configuration
SOIC View
SCLKB MUXREFB f(REF)/XTALIN XTALOUT XBUF CLKB ICD2051-2 DATA MUXREFA SCLKA CLKA/4 CLKA/2 CLKA
Summary
Name SCLKB MUXREFB Number Description Serial clock input line CLKB MUXREFB CLKB equals input reference frequency MUXREFB CLKB equals programmed frequency This used glitch-free frequency changes required. Three-states CLKB outputs when pulled LOW. (Internal pull-up allows no-connect three-state operation needed.) Ground Reference Oscillator input internal phase-locked loops Oscillator output reference crystal. Buffered Crystal Oscillator Output CLKB Programmable Output CLKA Programmable Output CLKA divided (low skew) CLKA divided Serial clock input line CLKA. Three-states CLKA outputs when pulled LOW. (Internal pull-up allows no-connect three-state operation needed.) MUXREFA CLKA equals input reference frequency MUXREFA CLKA equals programmed frequency This used glitch-free frequency changes required. Serial data input line both programmable PLLs
fREF/ XTALIN[1] XTALOUT[1] XBUF CLKB CLKA CLKA/2 CLKA/4 SCLKA MUXREFA
DATA
Note: best accuracy, parallel-resonant crystal, assume CLOAD
ICD2051:1/95
Revision: April 1995
ICD2051
General Considerations
Table Index Field Programming ICD2051 desired output frequency defined serial interface, with 22-bin number shifted ICD2051 programmable PLLs (CLKA CLKB), requiring 22-bit programming word loaded into each channel independently. This word contains fields: Table Programming Word Fields Field Index Counter value (P') Reserved Counter value (Q') bits (Least Significant Bits) normally logic Notes (Most Significant Bits) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 f(VCO) (MHz) 40.0 42.5 42.5 47l.5 47.5 53.5 53.5 58.5 58.5 62.5 62.5 68.5 68.5 69.0 69.0 82.0 82.0 87.0 87.0 92.0 92.0 92.1 92.1 105.0 105.0 115.0 115.0 120.0 115.0 120.0 115.0 120.0
frequency programmable oscillator f(VCO) determined these fields follows: P'=P-3 Q'=Q-2 f(VCO)=2 f(REF) where f(REF)=Reference frequency (between MHz) value f(VCO) must remain between MHz. Therefore, output frequencies below MHz, f(VCO) must multiplied into required range. accomplish this, post-VCO Divisor selected setting values field follows: Table Field Divisor
desired frequency lies boundary table exactly upper limit entry lower limit next) then either index value used (since both limits tested), recommend using higher one. assist with these calculations, Cypress/IC Designs provides BitCalc (Part #ICD/BCALC), Windowsprogram which automatically generates appropriate programming words from user's reference input desired output frequencies. software also assembles program words control power-down registers. Contact your local Cypress representative more information. Programming Constraints There five primary programming constraints user must aware Table Programming Constraints Parameter f(REF) f(REF)/Q f(VCO) Minimum Maximum
Index field used preset appropriate range. value this field should should chosen from Table (Note that this table referenced frequency f(VCO), rather than desired output frequency.)
constraints have with trade-offs between optimum speed lowest noise, stability factors affecting loop equation. factors listed completeness sake; however, using BitCalc program these constraints become transparent. ICD2051 Programming Example following example calculations BitCalc performs:
ICD2051:1/95
Revision: April 1995
ICD2051
Derive proper programming word 39.5 output frequency, using 14.31818 reference frequency: Since 39.5 MHz<40 MHz, double 79.0 MHz. 001. 0111. result: f(VCO)=79.0=(2 14.31818 P/Q) P/Q=2.7857 Several choices available: Table Value Candidates f(VCO) (MHz) 79.0363 78.9969 78.9669 Error (PPM) glitch-free. (See Serial Programming Timing Switching Waveforms section this datasheet.) Skew-Controlled CLKA CLKA output available concurrently values desired output. outputs also closely matched order minimize phase differences between outputs. Typical phase coherence less than skew between outputs, with less available order option. Output Frequency Accuracy accuracy ICD2051 output frequencies depends target output frequency. stated previously, output frequencies ICD2051 integrally related input reference frequency: f(OUT)=2 f(REF) Only certain output frequencies possible particular reference frequency. However, ICD2051 normally produces output frequency within 0.1% desired output frequency. Specifics regarding accuracy (ppm) given desired output frequency part BitCalc program output. Three-State Output Operation signal, when pulled LOW, will three-state clock output line (CLKA CLKB respectively). This supports wired-OR connections between external clock lines, allows procedures such automated testing where clock must disabled. signals contain internal pull-ups; they left unconnected three-state operation required. Estimating Total Current Drain Actual current drain function frequency circuit loading. operating current given output given equation: where I=current, C=load capacitance (max. pF), V=output voltage (usually 5V), f=output frequency MHz). calculate total operating current, following: XBUF CLKA CLKA/2 CLKA/4 CLKB Internal
Choose Q)=(80,29) best accuracy ppm). Therefore: P'=P-3=80-3=77=1001101 (4dH) Q'=Q-2=29-2=27=0011011 (1bH) programming word, generated concatenating I=0111, P'=1001101, R=1, M=001, Q'=0011011 obtain W=0111100110110010011011 (1e6c9bH) LOW-to-HIGH transition SCLKA/SCLKB (depending appropriate channel) used shift programming word into DATA serial stream, first. (See set-up hold timing specifications later this datasheet.) more than shifts performed, only last data bits received will retained. Glitch-Free Frequency-Modification Procedure When changing frequency, there period time when output signal will transition glitch changes post divider. applications where critical that output clock glitch always maintain some known value, MUXREFA MUXREFB inputs must used. Under normal operation, MUXREF(X) HIGH output clocks programmed value. When MUXREF(X) brought LOW, reference clock multiplexed associated output clock. output remains this fixed frequency while programmed frequency seeks value. When programming ICD2051, MUXREF inputs following manner: MUXREF(X) state. This will output reference frequency. transition guaranteed glitch-free. (See timing specifications.) Shift desired output frequency value 22-bit word defined above) using appropriate SCLK DATA lines. After last shifted will settle state (within .01% actual output frequency) within msec. MUXREF(X) HIGH state. This will output programmed frequency. This transition guaranteed
This gives approximation actual operating current. unconnected output pins, assume 5-10 loading, depending package type. Typical values: Table Typical Load Current Values Frequency high high Load none none high Current (mA)
ICD2051:1/95
Revision: April 1995
ICD2051
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Supply Voltage Ground Potential .-0.5V +7.0V Input Voltage -0.5V +0.5V Storage Temperature -65°C +150°C soldering temperature sec) 260°C Junction temperature 125°C Package power dissipation.525 mWatts
Operating Range
Ambient Temperature TAMBIENT 70°C AVDD
Operating Conditions
Parameter Supply Voltage Ambient Operating Temperature Load Capacitance Description Min. 4.75 Max. 5.25 Unit
Electrical Characteristics Over Operating Range
Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Output Leakage Current Power Supply Current -4.0mA Except XTALIN pins Except XTALIN pins 5.25V Three-state outputs max., MHz, -250 Test Conditions Min. Max. Unit
ICD2051:1/95
Revision: April 1995
ICD2051
Switching Characteristics Over Operating Range[2]
Parameter f(REF) t(REF) Name Output Frequency Reference Frequency Reference Clock Period Duty Cycle Output Rise Time Output Fall Time CLKA/2/4 skew MUXREF Set-Up Time SCLK Cycle Time SCLK HIGH Time SCLK Time Output Clock Stable Time Data Set-Up Time Data Hold Time Transition Time Transition Time Transition Time Transition Time Output Disable Time Output Enable Time Reference Oscillator nominal value t(REF) 1/f(REF) Duty cycle output oscillators defined Rise time outputs into 25-pF load Fall time outputs into 25-pF load Skew delay between CLKA output CLKA/2 CLKA/4 outputs Delay required after MUXREF goes prior starting SCLK clock line Minimum cycle time SCLK clock Minimum HIGH time SCLK clock Minimum time SCLK clock Time required CLKA CLKB output become valid after last SCLK clock Time required data valid prior rising edge SCLK Time required data remain valid after rising edge SCLK Time CLKA CLKB HIGH after assertion MUXREF Delay CLKA CLKB prior valid t(REF) signal output Time CLKA CLKB HIGH after release MUXREF Delay CLKA CLKB prior valid frequency output Time outputs into three-state mode after signal assertion Time outputs recover from three-state mode after signal goes HIGH t(REF)/2 tfreq2/2 tfreq1 3(t(REF)/2) t(REF) 3(tfreq2/2) tfreq1 2*t(REF) t(REF) t(REF) Description Min. 0.320 Max. 1000 msec Unit
Note: Input capacitance typically except crystal pads.
Switching Waveforms
Duty Cycle Timing
1.5V 1.5V 1.5V
ICD2051-3
ICD2051:1/95
Revision: April 1995
ICD2051
Switching Waveforms (continued)
Rise Fall Times
f(REF) INPUT OUTPUT CLOCKS
CLKA/2 CLKA/4
ICD2051-4
Serial Programming Timing
MUXREFA MUXREFB CLOCKS REQUIRED DATA SCLKA SCLKB
DATA CLKA CLKB
DATA VALID
tfreq1
ORIGINAL FREQUENCY
t(REF)
REFERENCE FREQUENCY
tfreq2
FREQUENCY
ICD2051-5
Three-State Timing
CLKA CLKB THREE-STATE OUTPUT
ICD2051-6
ICD2051:1/95
Revision: April 1995
ICD2051
Test Circuit
DEVICE UNDER TEST CLOAD
Ordering Information
Ordering Code ICD2051
Note: +70°C
Package Name
Package Type 16-Pin SOIC
Operating Range Commercial[3]
Document 38-00402
Package Diagram
16-Lead Molded SOIC
Cypress Semiconductor Corporation, 1996. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

3512 ICD2051 Dual Programmable Clock Generator Features

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