Table 2.Twisted Pair Cable Types Shielded Twisted Pair Mbaud Mbaud Mba

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Table 2.Twisted Pair Cable Types Shielded Twisted Pair Mbaud Mbaud Mba

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Frequently Asked Questions about HOTLinkfollowing questions frequently asked customers evaluating HOTLinkproducts. These cursory answers will serve introduction each topic. Separate application notes cover these topics more complete detail. HOTLink communicate over various media? HOTLink intrinsic distance limit. issues that determine distances over which data sent using HOTLink are: choice interconnect media (fiber-optic cable, coaxial cable, twisted-pair cable, etc.); jitter that accumulates injected while data transit over selected media. HOTLink drive standard fiber-optic interface modules that support standard PECL interface signals. These electro-optical modules suitable communicating over distances from meters several kilometers. Fiber-optic interconnect offers longest distances lowest interference potential transmission media. lower-cost applications, HOTLink directly drive wire transmission lines. main distance determining factors when using wire links related characteristics cable. Wire transmission lines have significant frequency-dependent attenuation that causes jitter direct function data rate media length. Uncompensated transmission line lengths limited much more jitter (and jitter tolerance receiver) than actual signal attenuation. detrimental effect jitter lessened with addition suitable attenuation compensation filter that matches attenuation characteristics cable. This filter trades receiver differential voltage amplitude jitter reduction increases possible transmission distance. When using wire transmission lines, other issues beyond transmission distance often determine transmission line suitability. These issues include both radiated emissions susceptibility external disturbance that must examined prior selection link media type. Some typical wire types uncompensated transmission distances over which HOTLink communicate shown Table simple compensation filter, built from passive components, increase reliable transmission distance more than twice these distances. more information application note "HOTLink Copper Interconnect-Maximum Length Frequency." Table 1.Coaxial Cable Types Coaxial Cable Mbaud Mbaud Mbaud RG-58 RG-58 RG-58 RG-6 RG-6 RG-6 RG-59 RG-59 RG-59 RG-62 RG-62 RG-62
Table 2.Twisted Pair Cable Types Shielded Twisted Pair Mbaud Mbaud Mbaud IBM®-Type IBM-Type IBM-Type Unshielded Twisted Pair Mbaud Mbaud Mbaud UTP3 UTP5
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134
408-943-2600 June 1995
Frequently Asked Questions About HOTLink
PECL inputs outputs HOTLink products connected (-5.2V) products? +5.0V PECL inputs outputs directly compatible with true (10K, 10KH, 100K, etc.) running power supplies. Connections between HOTLink PECL running -5.2V easily accomplished capacitor-coupling serial data lines. Details this coupling technique included Cypress application note "HOTLink Design Considerations.
What happens when inputs HOTLink Receiver left open? inputs HOTLink Receiver have internal pull-down resistors assure that ECL-emitter follower outputs will positive input current (approximately into pin) normal voltages. Thus, single-ended inputs (i.e., A/B, INB) will float logical level. (These pull-downs will sink enough current normal output termination. They only intended prevent emitter-follower oscillations caused negative input-impedance that possible some less robust designs.) Open inputs will interpreted follows: will cause Receiver accept data from serial inputs; will cause output assume output state; will interpreted input with data (assuming also LOW). data interpreted error (RVS=HIGH C0.7 Encoded mode, Qa-j outputs Bypass mode) will cause internal clock-synchronizer phase-locked loop (PLL) track REFCLK input frequency. internal resistor network used pull differential serial data inputs (i.e., INA± INB±) will cause unconnected inputs rest approximately 2.0V. This resting voltage byproduct internal resistive attenuator used enhance input-common mode range. both inputs differential pair left unconnected, inputs will undefined state HOTLink receiver behavior will unpredictable. Stray, non-differential noise that appears these unconnected inputs will amplified interpreted serial data. This will cause random parallel-data output changes, cause wander drift away from REFCLK frequency. input intentionally unused differential-pair should terminated through resistor assure that data transitions accidentally created.
What special power-supply bypassing required HOTLink products? HOTLink requires special considerations power-supply bypassing beyond that normally associated with high speed logic. This typically includes ground plane, split plane, multiple chip bypassing using quality capacitors. Each ground pins HOTLink should connect directly ground plane using short (<.25") traces vias. pins should connect under HOTLink then connect board through single via. Connect 22-nF capacitor each directly from GND. more information "Using Decoupling Capacitors" application note.
HOTLink Receiver switched from INB, long will take re-lock? Assuming that data both within ±0.1% frequency offset described HOTLink datasheet, phase-locked loop (PLL) will acquire lock data stream within byte times. exact time required involves statistical probabilities related phase, frequency, jitter, cannot exactly predicted. Empirical testing using normal data patterns shows that time required achieve absolute minimum phase error with data stream will vary from zero about bytes. operational serial link will produce valid parallel data much earlier than amount time required achieve minimum phase error, since instantaneous phase error accommodated jitter. wide jitter tolerance offered HOTLink Receiver will minimize time that data incorrectly interpreted during phase acquisition. larger problem facing system protocol that allows switching serial data streams, byte synchronization (byte-framing). After data-stream been switched, must reframed. This requires that K28.5 K28.5s within five bytes multibyte framing enabled) must received. time that elapses before this happens depends system protocol timing data input switch. Correct data might come HOTLink Receiver hundreds byte times reframing regardless speed phase acquisition. more information, refer Receiver Data-Phase Acquisition Time section "HOTLink Jitter Characteristics" application note.
connection between HOTLink Transmitter Receiver briefly interrupted, long will take re-lock? exact behavior HOTLink Receiver depends length cause interruption. interruption synchronous with data (i.e., data bits disappear without significant disturbance placement final data transitions), lasts less than dozen bytes, probable that will relock very first bit. interruption asynchronous (i.e., timing final transitions disturbed) synchronous interruption lasts longer than dozen bytes, will relock within first bytes after resumption data stream. long
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interruption occurs that synchronous byte boundaries, receiver lose byte synchronization when relocks. this case, data will need reframed. interruption asynchronous, link interface allows noise injected into serial inputs HOTLink Receiver, time relock becomes much harder predict. noise that being injected causes track within frequency offset limits (approximately ±0.25% REFCLK frequency) will reacquire bytes (typically less than ten) after good data stream reappears. frequency been moved offset limits input noise, take more than 60-70 bytes before locks good data. When hits frequency offset limit, will recenter itself REFCLK frequency then attempt lock data. While lock (after experiencing data stream interruption) frequency will wander beyond offset limits. more information, refer Receiver Data-Phase Acquisition Time section "HOTLink Jitter Characteristics" application note. connection between HOTLink Transmitter Receiver broken, what will come receiver? exact behavior HOTLink Receiver difficult predict when serial data link broken, since there many ways that link itself behave. following behaviors most common; Bypass Mode-Reframe-OFF LOW) Clean link break with extraneous noise input into serial inputs:
runs REFCLK frequency. always HIGH. Qa-j HIGH depending exact offsets built into transmission line termination. terminations exactly matched, then Qa-j indeterminate.
Bypass Mode-Reframe-OFF Noise injection into serial inputs:
runs REFCLK frequency ±<1.0% (typically <±0.25%) wander between range limits center frequency, randomly controlled injected noise. rest HIGH pulse randomly false K28.5s decoded from noise. Qa-j will indeterminate switch randomly.
Encoded Mode-Reframe-OFF Clean break with extraneous noise input into serial inputs:
runs REFCLK frequency. pulses once byte. Q0-7 indicate C0.7, SC/D always HIGH, always HIGH there offsets built into transmission line termination. terminations exactly matched, then Q0-7, SC/D indeterminate.
Encoded Mode-Reframe-OFF Noise injection into serial inputs:
runs REFCLK frequency ±<1.0% (typically <±0.25%) wander between range limits center frequency randomly controlled injected noise. pulse randomly once byte. Q0-7, SC/D indeterminate switch randomly.
Either Mode-Reframe-ON Noise injection into serial inputs:
runs REFCLK frequency ±<1.0% (typically <±0.25%) wander between range limits center frequency randomly controlled injected noise. been HIGH less than 2048 bytes, will stretch randomly false K28.5s decoded from noise. been HIGH more than 2048 byte-times, will only stretch when multiple K28.5 string decoded from noise. pulse randomly once byte. Q0-7, SC/D indeterminate switch randomly.
Frequently Asked Questions About HOTLink
What correct operation input receiver? What minimum number K28.5 characters required insure proper framing? tell receiver framed properly? Recovery information from serial data stream requires recovery clock (accomplished receiver PLL) byte synchronization (accomplished receiver framer). HOTLink framer enabled disabled input. well behaved, standardized point-to-point protocols that seldom switched, control byte framer managed service protocol controller. This service monitors when some error criteria have been exceeded, goes framing subroutine. This framer service sets RF=HIGH while framing during normal message transactions. less well behaved systems, systems that switch data sources often, necessary leave RF=HIGH long periods permanently). Leaving HIGH opens system problem data corruption serial link caused data patterns that happen match SYNC character. Since this Alias SYNC unlikely aligned normal byte boundaries, will cause framer align parallel data wrong byte boundary resulting long running data corruption. When HIGH, receiver searches received data stream pattern matching K28.5 (001111 1010 110000 0101). When found, internal counter that controls byte translation reset byte boundaries aligned SYNC character. HOTLink minimizes alias SYNC problem incorporating multi-byte framer into receiver. been HIGH less than 2048 bytes, would typical protocol driven framing control, single K28.5 will align byte boundaries. been HIGH more than 2048 bytes, would typical packet switched systems, multi-byte framer enabled single K28.5 longer sufficient align byte boundaries. minimize risk alias SYNC, reframing only allowed when K28.5s detected. These K28.5s adjacent, separated exactly one, two, three transmission characters. other spacing (i.e., non-integral character separation, between K28.5) assumed caused transmission errors will ignored framing purposes. addition upper level protocol error detection mechanisms common communication links, HOTLink Receiver offers several indications that link misframed. example, Bypass mode output pulses once K28.5 detected. LOW, only K28.5 that detected that properly framed, others will just pass through part received data. protocol maximum packet size minimum number K28.5s, simple retriggerable-one-shot used detect when framing been lost. this example, one-shot retriggered properly spaced K28.5s, then data properly framed. one-shot times-out, indicating that much time elapsed between SYNC characters, data would automatically reframed raising till next K28.5 indication. Another example HOTLink's indication misframed link occurs during Encoded mode. Encoded mode, output serves similar quite obvious function. Normal data being sent over typical data links will have very error rate (e.g., bit-error-rates 1x10-12 quite common. BER=1x10-12 error hour MHz). Therefore, asserted often assumed that cause misframing. Another retriggerable-one-shot could used detect this condition, could detected simple synchronous state machine constructed PLD. more information, refer "HOTLink CY7B933 Description" application note.
What happens receiver's clock parallel outputs when reframes? When byte boundary realignment occurs, external timing HOTLink Receiver changes match byte alignment. Logic internal receiver guarantees that clock outputs (CKR RDY) never glitch. They will stretch byte alignment adding HIGH time output pulse. exact width high times these clock outputs will depend exact timing realignment, neither will ever less than that nominal, normally running output (i.e., five times, each, minimum). data outputs (Q0-7, SC/D, RVS) change time determined internal bit-rate counters, timed assure maximum set-up hold times down-stream logic. Since realignment will reset cycle internal counter, possible that outputs will change, then change again between clock edges when byte realignment happens. Since clock-cycle stretches, this glitch data output remains outside specified data-access hold times. more information, refer "HOTLink CY7B933 Description" application note.
What does BIST BIST system without redoing calculations critical interface timing? What functionality does BIST test guarantee? HOTLink built-in self-test allows clear unambiguous check HOTLink Transmitter Receiver, serial link connecting them. part offline diagnostic, this feature allows user insure that interconnect link fully operational that other diagnostic failure indications caused system blocks above physical layer. BIST
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allows HOTLink adapter card manufacturer quick link quality test node quality test with loop-back functionality HOTLink) without necessity bringing fully functional system link testing. BIST controlled unused HOTLink data-enable inputs. Only connections minimal external logic necessary BIST otherwise complete system. (See Cypress application note "HOTLink Built-In Self-Test.") BIST status indications appear RVS(Qj) outputs which easily monitored logic internal external data flow controller. BIST mode, HOTLink Transmitter generates 29-1 (511 byte) pseudo-random pattern using Input register configured Linear Feedback Shift register. HOTLink Receiver compares serial BIST data stream with identical BIST patterns generated Output register. logic transmitter (except input pins) logic receiver (including output pins their attached loads) checked BIST. serial link interconnect components exercised with normal data patterns, which checked byte-by-byte real time. What fiber-optic components compatible with HOTLink products? standard fiber-optic interface components compatible with HOTLink products. following table representative comprehensive list optical interface manufacturers. more complete list vendors products included "HOTLink Design Considerations" application note. AMP/Lytel Division Chubb P.O. 1300 Somerville, 08876 (908) 685-2000 Corp 1201 Cumberland West Lafayette, 47906-1388 (317) 463-2565 Hewlett-Packard Components Division West Trimble Road Jose, 95131 (800) 535-7449 (408) 435-6342 Siemens Fiber Optic Components Commerce Totowa, 07512 (201) 890-1606 Sumitomo Electric Fiber Optics Corporation Sawmill River Road Tarrytown, 10591-6725 (914) 347-3770
What significance HOTLink claim external components"? HOTLink Transmitter Receiver have completely integrated clock multiplier data separator functions. These functions implemented with high-performance phase-locked loops (PLLs) that have been tuned maximum performance minimum system noise sensitivity. competitive products that purport offer similar functions, these PLLs often implemented with external filter frequency setting components with goal achieving maximum performance. these very same external components largest cause end-user complaints random system failures because they expose most critical analog signals circuit external noises that abound normal systems. External components require critical, costly time consuming printed circuit board layout well high-speed analog digital design techniques that unfamiliar many system integrators. HOTLink products designed built using fully differential analog digital circuits give lowest possible output jitter highest possible jitter tolerance. There external components compromise system performance unexpected unpredictable ways. more information, refer HOTLink Transmitter Jitter section "HOTLink Jitter Characteristics" application note. What intrinsic bit-error-rate HOTLink Transmitter Receiver? HOTLink BER=Zero. HOTLink Transmitter Receiver have intrinsic failure modes. their power maintained interface link connecting them reasonable design margin, total error rate will exactly that interconnect media. Link error rates <<1x10-15 common easily achieved. Even with worst-case design derating end-of-life derating, <<1x10-12 presents significant challenge. real question being asked "What will link when using HOTLink?" answer this question involves design serial transmission link margins designed into HOTLink will significantly degrade link. more information, refer "Understanding Bit-Error-Rate with HOTLink" application note. much jitter created transmitter? much jitter created receiver? What significance HOTLink Transmitter requirement crystal-stable clock source? phase-locked loops (PLLs) HOTLink Transmitter Receiver like low-pass filters jitter that embedded data clock signal source. transmitter, signal source input. jitter that appears will passed unattenuated frequency components below natural frequency filter (approximately kHz). Frequency components above natural frequency will attenuated about dB/octave. Frequency components
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that fall very near natural frequency filter will slightly amplified (approximately dB). These normal characteristics Type-2, second-order filter. When transmitter jitter clock source, typical output jitter will less than peak-to-peak. possible measure significantly more jitter than that which actually present complete system well understood. hundred millivolts noise, while insignificant logic normal system board, will imaginary jitter measured output. This imaginary jitter appears because single ended oscilloscope sees waveform were measured against fixed threshold, while differential serial interface sees noise common mode signal ignored (e.g., noise could create 100-200 imaginary jitter). Likewise, normal method measuring peak-to-peak jitter, infinite persistence scope trace, will show larger jitter than that contributed HOTLink Transmitter. frequency jitter (wander) oscillator, scope trigger, temperature, voltage related delay variations will contribute width stored scope trace. Delay variations include threshold variations that cause apparent delay variation (e.g., threshold change cause 100-200 apparent jitter). signal source receiver serial data stream and, like transmitter, passes frequency components received jitter that fall below natural frequency filter (approximately 1000 depending actual data transition density being received). Frequency components above natural frequency will attenuated there minor jitter peaking about natural frequency PLL. Since characteristics input jitter will determine jitter content receiver output (the only place directly measure Rx-PLL jitter) somewhat difficult predict output jitter. Maximum output jitter less than (peak-to-peak) when receiver tracking normal data (BIST data typical) that exhibits maximum tolerable peak-to-peak jitter. Jitter from normal data wide-bandwidth, significantly high-frequency content, have peak-to-peak amplitude about time. serial data contains significant frequency jitter component (typical crystal oscillators some pulse generators) output jitter measured could much higher. Jitter measurements receiver output more misleading than those associated with transmitter serial outputs, since measurements made outputs. jitter characteristics mentioned above affect system performance following ways. low-frequency jitter (below bandwidth either transmitter receiver PLL) will treated wander. purposes PLLs, wander (usually caused frequency power supply variations temperature fluctuations within timing ICs) will reduce system timing margins will contribute bit-error-rate. Wander affect system timing interfaces where transmitter clock source used clock information received from receiver tracking data from another clock source. variation clock frequencies violate set-up hold times, exact problems usually solved FIFO memories typical communication systems. High-frequency jitter above natural frequency filters) contribute BER. High-frequency jitter caused clock source, media transfer characteristics, external noise. recovered internal bit-rate clock will track high-frequency jitter above natural frequency. High-frequency jitter, therefore, cause edge move into receiver sampling window causing erroneously sampled error). suitable clock source should selected with above effects mind. only clock source guaranteed offer required stability high-frequency specifications crystal oscillator. High-frequency jitter minimal, low-frequency wander usually small very frequency. Frequency accuracy easily guaranteed mechanical means, high accuracy devices relatively cost. Free-running resistor-capacitor (RC) oscillators, logic gate ring oscillators inductor-capacitor (LC) oscillators include much high-frequency jitter, experience wide frequency variation function process environmental conditions thus unsuitable this application. "HOTLink Jitter Characteristics" application note more information. HOTLink anything other than Fibre Channel/ESCONinterconnect? HOTLink been designed implement required performance specifications Fibre Channel ESCON, additional user features that encourage beyond these specifications. specific timing parallel clock signals allow efficient interconnect with typical generic controllers FIFO memories. built-in self-test included 8B/10B encoder functions allow users implement custom protocols that suitable data-movement application. HOTLink compatible with common link interconnect media interfaces. low-cost, low-power, high-performance tool that enables otherwise impractical system innovation. there data move, HOTLink carry HOTLink compatible with ATM? HOTLink compatible with 194.40 Mbaud (155.52 MBit/second), 8B/10B interface defined AForum. offers data, special characters framing behaviors described AForum User-Network Interface (UNI) Specification. particular HOTLink serves physical layer interface physical layer Mbps Interface (and copper variant). When operating this capacity, HOTLink runs 194.40 Mbaud uses built-in 8B/10B encoder. required data special codes responses included HOTLink.
Frequently Asked Questions About HOTLink
HOTLink compatible with SONET? HOTLink directly compatible with SONET least following reasons:
There standard SONET frequencies within operating range 160-330 Mbaud. HOTLink 10-bit unencoded interface, SONET systems 8-bit interface. SONET requires much slower rate-of-change frequency during loss signal than HOTLink achieve.
HOTLink Receiver tolerate long strings zeros contained SONET serial streams, future designs will directly accommodate SONET specifications. What latency through HOTLink Transmitter Receiver? input data stored Transmitter Input register rising edge CKW, this becomes time-zero. Approximately bit-times (i.e., times period CKWB10) minus output buffer (approximately later, first that data will emerge from OUTA±, pins. After transit time serial link, which significant, that will appear receiver. Transit times typical serial links include propagation delay optical modules (typically 5-10 pair), any, propagation rate link media (i.e., approximately ns/ft copper, ns/ft multi-mode optical cable). Approximately bit-times plus output buffer (approximately after first data received input receiver, appears Q0-7 outputs. Eight bit-times later rises data transfer complete. total latency HOTLink Tx/Rx pair approximately link delay plus bit-times. there VERILOG VHDL model HOTLink? Logic Modeling offers full function logic models both HOTLink Transmitter (CY7B923) HOTLink Receiver (CY7B933). These models perform normal chip functions including BIST, Encoded, Bypass modes operation. models accurately model "real" parts have been validated having them actual-chip design-simulation vectors outgoing-test vectors. Logic Modeling offers wide variety standard product logic models that various simulations platforms. They reached Logic Modeling 19500 N.W. Gibbs Drive Beaverton, 97006 Telephone (503) 690-6900 (503) 690-6906 need estimate reliability HOTLink design. many components does contain? Table HOTLink Reliability Data CY7B923 Number components Number transistors Number gates Percent digital gate count Percent analog area size 4285 3813 2072 mils CY7B933 7988 6855 2960 mils
Built Cypress Standard 0.8-micron BiCMOS. Designed reliable operation temperatures -55°C 155°C. pins characterized withstand >4400V (HBM). Wafer Capability Jose, Round Rock,
HOTLink trademark Cypress Semiconductor. registered trademark International Business Machines Corporations. ESCON trademark International Business Machines Corporations.
Cypress Semiconductor Corporation, 1995. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

Table 2.Twisted Pair Cable Types Shielded Twisted Pair Mbaud Mbaud Mba

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