1074 CY7C1020 Static Features 5.0V operation 10%)

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1074 CY7C1020 Static Features 5.0V operation 10%)

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Y7C10
1074
CY7C1020
Static
Features
5.0V operation 10%) High speed active power (max., version) Very standby power (max., version) Automatic power-down when deselected Independent Control Upper Lower bytes Available 44-pin TSOP 400-mil (BLE) LOW, then data from pins (I/O1 through I/O8), written into location specified address pins through A14). byte high enable (BHE) LOW, then data from pins (I/O9 through I/O16) written into location specified address pins through A14). Reading from device accomplished taking chip enable (CE) output enable (OE) while forcing write enable (WE) HIGH. byte enable (BLE) LOW, then data from memory location specified address pins will appear I/O1 I/O8. byte high enable (BHE) LOW, then data from memory will appear I/O16. truth table back this datasheet complete description read write modes. input/output pins (I/O1 through I/O16) placed high-impedance state when device deselected HIGH), outputs disabled HIGH), disabled (BHE, HIGH), during write operation LOW, LOW). CY7C1020 available standard 44-pin TSOP type 400-mil-wide packages.
Functional Description
CY7C1020 high-performance CMOS static organized 32,768 words bits. This device automatic power-down feature that significantly reduces power consumption when deselected. Writing device accomplished taking chip enable (CE) write enable (WE) inputs LOW. byte enable
Logic Block Diagram
DATA DRIVERS
Configuration
TSOP View I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
Array
I/O1 I/O8 I/O9 I/O16
COLUMN DECODER
1020-1
I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9
DECODER
SENSE AMPS
1020-2
Selection Guide
7C1020-10 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA)
Shaded area contains advance information.
7C1020-12
7C1020-15
7C1020-20
Cypress Semiconductor Corporation
3901 North First Street
Jose 95134 408-943-2600 October 1996 Revised September 1997
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage Relative GND[1] -0.5V +7.0V Voltage Applied Outputs High State[1] .-0.5V +0.5V Input Voltage .-0.5V +0.5V
CY7C1020
Current into Outputs (LOW). Static Discharge Voltage >2001V (per MIL-STD-883, Method 3015) Latch-Up Current. >200
Operating Range
Range Commercial Ambient Temperature[2] +70°C 4.5V-5.5V
Electrical Characteristics Over Operating Range
7C1020-10 Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Load Current Output Leakage Current Operating Supply Current Automatic Power-Down Current Inputs Automatic Power-Down Current CMOS Inputs
7C1020-12 Min. Max. -0.5
7C1020-15 Min. -0.5 Max. Unit
Test Conditions Min., -4.0 Min.,
Min.
Max.
-0.5 VCC, Output Disabled Max., IOUT fMAX 1/tRC Max. VCC, VIL, fMAX Max. VCC, 0.3V, 0.3V, 0.3V,
ISB1
ISB2
Shaded area contains advance information. Notes: (min.) -2.0V pulse durations less than "instant case temperature.
Electrical Characteristics Over Operating Range (continued)
CY7C1020
7C1020-20 Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Load Current Output Leakage Current Operating Supply Current Automatic Power-Down Current Inputs Automatic Power-Down Current CMOS Inputs
Test Conditions Min., -4.0 Min.,
Min.
Max.
Unit
-0.5 VCC, Output Disabled Max., IOUT fMAX 1/tRC Max. VCC, VIL, fMAX Max. VCC, 0.3V, 0.3V, 0.3V,
ISB1
ISB2
Shaded area contains advance information.
Capacitance[3]
Parameter COUT Description Input Capacitance Output Capacitance Test Conditions 25°C, MHz, 5.0V Max. Unit
Note: Tested initially after design process changes that affect these parameters.
Test Loads Waveforms
OUTPUT INCLUDING SCOPE OUTPUT Equivalent EQUIVALENT OUTPUT INCLUDING SCOPE <3ns
1020-3 1020-4
INPUT PULSES 3.0V <3ns
1.73V
Switching Characteristics[4] Over Operating Range
7C1020-10 Parameter READ CYCLE tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE tSCE tPWE tLZWE tHZWE Read Cycle Time Address Data Valid Data Hold from Address Change Data Valid Data Valid HIGH High HIGH High
CY7C1020
7C1020-12 Min. Max.
7C1020-15 Min. Max.
7C1020-20 Min. Max. Unit
Description
Min.
Max.
Z[6]
Power-Up HIGH Power-Down Byte enable Data Valid Byte enable Byte disable High
WRITE CYCLE
Write Cycle Time Write Address Set-Up Write Address Hold from Write Address Set-Up Write Start Pulse Width Data Set-Up Write Data Hold from Write HIGH Z[6] High
Byte enable write
Notes: Test conditions assume signal transition time less, timing reference levels 1.5V, input pulse levels 3.0V, output loading specified IOL/IOH 30-pF load capacitance. tHZOE, tHZBE, tHZCE, tHZWE specified with load capacitance part Test Loads. Transition measured ±500 from steady-state voltage. given temperature voltage condition, tHZCE less than tLZCE, tHZOE less than tLZOE, tHZWE less than tLZWE given device. internal write time memory defined overlap LOW, LOW. must initiate write, transition these signals terminate write. input data set-up hold timing should referenced leading edge signal that terminates write.
Switching Waveforms
Read Cycle No.1
CY7C1020
ADDRESS tOHA DATA PREVIOUS DATA VALID DATA VALID
1020-5
Read Cycle No.2 Controlled)
ADDRESS
tACE BHE, tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE SUPPLY CURRENT tHZCE tHZBE DATA VALID IISB
1020-6
tHZOE
HIGH IMPEDANCE
DATA
IICC
Notes: Device continuously selected. and/or HIGH read cycle. Address valid prior coincident with transition LOW.
Switching Waveforms (continued)
Write Cycle Controlled)
[11,
CY7C1020
ADDRESS
tSCE
tPWE BHE, DATAI/O
1020-7
Write Cycle (BLE Controlled)
ADDRESS
BHE,
tPWE tSCE DATAI/O
1020-8
Notes: Data high impedance and/or BLE= VIH. goes HIGH simultaneously with going HIGH, output remains high-impedance state.
Switching Waveforms (continued)
Write Cycle No.3 Controlled, LOW)
CY7C1020
ADDRESS
tSCE
tPWE
BHE, tHZWE DATA tLZWE
1020-10
Truth Table
I/O1-I/O8 High Data Data High Data Data High High High I/O9-I/O16 High Data High Data Data High Data High High Power-Down Read bits Read Lower bits only Read Upper bits only Write bits Write Lower bits only Write Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) Ordering Code CY7C1020-10VC CY7C1020L-10VC CY7C1020-10ZC CY7C1020L-10ZC CY7C1020-12VC CY7C1020L-12VC CY7C1020-12ZC CY7C1020L-12ZC CY7C1020-15VC CY7C1020L-15VC CY7C1020-15ZC CY7C1020L-15ZC CY7C1020-20VC CY7C1020L-20VC CY7C1020-20ZC CY7C1020L-20ZC
Shaded areas contain advance information.
CY7C1020
Package Name
Package Type
Operating Range
44-Lead (400-Mil) Molded Commercial 44-Lead (400-Mil) Molded Commercial 44-Lead TSOP Type 44-Lead TSOP Type Commercial Commercial
44-Lead (400-Mil) Molded Commercial 44-Lead (400-Mil) Molded Commercial 44-Lead TSOP Type 44-Lead TSOP Type Commercial Commercial
44-Lead (400-Mil) Molded Commercial 44-Lead (400-Mil) Molded Commercial 44-Lead TSOP Type 44-Lead TSOP Type Commercial Commercial
44-Lead (400-Mil) Molded Commercial 44-Lead (400-Mil) Molded Commercial 44-Lead TSOP Type 44-Lead TSOP Type Commercial Commercial
Document 38-00542-A
Package Diagrams
44-Lead (400-Mil) Molded
Package Diagrams (continued)
CY7C1020
44-Pin TSOP
Cypress Semiconductor Corporation, 1997. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

1074 CY7C1020 Static Features 5.0V operation 10%)

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