double-sided construction ceramic Ball Grid Array (BGA) package allows

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double-sided construction ceramic Ball Grid Array (BGA) package allows

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Application Note AN1001 ClearONERC Configuration Options
double-sided construction ceramic Ball Grid Array (BGA) package allows board designer closely locate passive resistor capacitor elements near active signal sources loads. package solution, eases routing design, saving many hours printed circuit layout time space.
ClearONE Resistor/Capacitor BGA) terminator networks provide high performance passive termination. Designed ceramic substrate, devices virtually eliminate channel capacitance while providing identical performance characteristics each signal line. choosing BGA, designer provided with opportunity closely match signal line circuit performance. Each channel will closely matched resistor capacitor values with minimal channel capacitance cross talk. Minimizing cross talk while closely matching channel performance critical differential signal line applications. Server back plane jitter filters memory terminators have optimally placed bypass capacitors fewer component placements.
Differential Lines
Backplane 0.01uF
Figure Back Plane Jitter Filter
Encapsulation Resistor System
High Power Dissipation
Resistor Overglaze
Conductive Vias
Fully Filled
Ceramic Substrate
0.020" Thick Alumina
Ceramic Chip Capacitors Conductive Pads Signal Lines
Signal Plane Ground Plane Printed Circuit Board Power Plane Signal Plane Solder Spheres
0.025" 0.030" Dia. High Temperature 10/90 Sn/Pb Alloy
Solder Interface
63/37 Sn/Pb Eutectic
Traces
Figure Physical Construction
Electronic Components Page www.ctscorp.com ClearONERC Configuration Options
7/14/2005 AN1001
Component Specifications Design Options
Resistors: Value Range Tolerance Power Rating1 Single Element Total Package Capacitors: Values2 Dielectric: Values2 Dielectric: Values2 Dielectric: Package: Pitch Styles (Figure Channel Capacitance Ball Grid Array Size
Notes:
Ohms ±1.0% ±200ppm/°C .050mW min. 70°C Watt 70°C .01µF .022 1.0mm 1.27mm .25pF
Individual element total device power requirements must both considered each application Working Voltage must considered when making capacitor value dielectric selections
Table Resistor, Capacitor, Package Options
Style
Style
Style
Figure Styles
Environmental Performance
Operating Temperature Range: -55°C +85°C
Standard Process Range with Epoxy Encapsulation
-55°C +125°C (X7R Dielectric) Range applies special order non-encapsulated version with
exposed capacitors.
Electronic Components Page www.ctscorp.com ClearONERC Configuration Options
7/14/2005 AN1001
Encapsulated Figure Packages
Non-Encapsulated
Conclusion
terminators provide options, features performance required today's state board designs. interested working closely with board designers provide custom solutions meet their needs.
Referenced Documents
Application Notes:
Printed Circuit Assembly Guidelines Rework AN-C1-PCAG-A AN-RC1-RW-A
LINK Application Notes: Link Data Sheet:
Written Date:
Damon Niswonger 7/14/2005
Electronic Components Page www.ctscorp.com ClearONERC Configuration Options
7/14/2005 AN1001

double-sided construction ceramic Ball Grid Array (BGA) package allows

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