Miniature Surface Mount Digital Color Sensor ADJD-S311-CR999 cost

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Miniature Surface Mount Digital Color Sensor ADJD-S311-CR999 cost

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ADJD-S311-CR999
Miniature Surface Mount Digital Color Sensor
ADJD-S311-CR999 cost effective, channels package with mere size 0.76mm. CMOS with integrated filters cater wide dynamic range illumination level ideal applications like portable mobile devices, which demand higher integration, smaller size power consumption. Sensitivity control performed
Features
10bitresolutionperchanneloutput Lowsupplyvoltage(VDD)2.5V illumination Lowpowermode(sleepmode) 0°Cto70°Coperatingtemperature Industry'ssmallestformfactor -CSP2.2x2.2x0.76mm Leadfreepackage
Applications
players,etc. Consumerappliances Portablemedicalequipments Portablecolordetector/reader
General Specifications
Feature Interface Supply Value 00kHz serial interface digital (nominal), analog (nominal)
Powering Device
voltage must applied IO's during power-up power-down ramp time
VDDD
VDD_RAMP
Protection Diode Turn-On During Power-Up Power-Down
particular power-up power-down sequence must used prevent diode from turning general, AVDD DVDD should power-up powerdown together prevent diodes from turning inadvertently. During this period, voltage should
Ground Connection
star-connected central power source shown AGND DGND cause diodes turn inadvertently.
Electrical Specifications Absolute Maximum Ratings (Notes
Parameter Storage temperature Digital supply voltage, DVDD DVSS Analog supply voltage, AVDD AVSS Input voltage Solder Reflow Peak temperature Human Body Model rating Symbol TSTG_ABS VDDD_ABS VDDA_ABS VIN_ABS TL_ABS ESDHBM_ABS Minimum Maximum Units pins, human body model JESD-A4-B pins Notes
Recommended Operating Conditions
Parameter Free operating temperature Digital supply voltage, DVDD DVSS Analog supply voltage, AVDD AVSS Output current load high Output current load Input voltage high level (Note Input voltage level (Note Symbol VDDD VDDA 0.7VDDD Minimum Typical Maximum VDDD 0.3VDDD Units
Electrical Specifications
Parameter Output voltage high level (Note Output voltage level (Note Supply current (Note Sleep-mode supply current (Note Input leakage current Symbol IDD_STATIC IDD_SLP ILEAK Conditions (Note (Note Minimum VDDD-0.8 Typical (Note VDDD-0.4 Maximum Units
Electrical Specifications
Parameter Internal clock frequency External clock frequency -wire interface frequency Symbol f_CLK_int f_CLK_ext f_wire Conditions Minimum Typical (Note Maximum Units
Optical Specification
Parameter Dark offset Symbol Conditions Minimum Typical (Note Maximum Units
Minimum sensitivity (note
Parameter Irradiance Responsivity Symbol Conditions Refer Note Refer Note Refer Note Clear Refer Note Minimum Typical (Note Maximum Units LSB/ (mWcm-)
Maximum sensitivity (note
Parameter Irradiance Responsivity Symbol Conditions Refer Note Refer Note Refer Note Clear Refer Note Minimum Typical (Note 3796 6590 Maximum Units LSB/ (mWcm-)
Saturation Irradiance minimum sensitivity (note
Parameter Saturation Irradiance Symbol Conditions Refer Note Refer Note Refer Note Clear Refer Note Minimum Typical (Note 6.73 5.74 4.03 3.87 Maximum Units mW/cm
Saturation irradiance maximum sensitivity (note
Parameter Saturation Irradiance Symbol Conditions Refer Note Refer Note Refer Note Clear Refer Note Minimum Typical (Note Maximum Units mW/cm
Notes The"Absolute Maximum Ratings" those values beyond which damage device occur. device should operated these limits. parametric values defined the"Electrical Specifications" table guaranteed absolute maximum ratings. AppliestoallDIpins.
Notes:(continued)
Relative sensitivity
Spectral Response
Wavelength (nm)
Figure Typical spectral response when gains color channels equal.
Serial Interface Timing Information
Parameter clock frequency (Repeated) START condition hold time Data hold time clock period clock high period Repeated START condition setup time Data setup time STOP condition setup time free time between START STOP conditions Symbol fscl tHD:STA tHD:DAT tLOW tHIGH tSU:STA tSU:DAT tSU:STO tBUF Minimum Maximum 3.45 Units
tHD:STA
tHIGH
tSU:DAT
tSU:STA
tBUF
tLOW tHD:DAT tHD:STA tSU:STO
Figure Serial Interface Timing Waveforms
Serial Interface Reference
START/STOP Condition
master initiates terminates serial data transfers.To begin serial data transfer, master must send SCLisHIGH.
START condition
STOP condition
Figure START/STOP Condition
Data Transfer
LOW.
Data valid Data change
Figure Data Transfer
requirements.
STARTorrepeated STARTcondition
STOPorrepeated STARTcondition
Figure Data Byte Transfer
SDAdatasampledonthe positiveedgeofSCL
SDAdatadrivenonthe negativeedgeofSCL
Figure Data Synchronization
format).
Acknowledge/Not acknowledge
SDApulledLOW byreceiver (SLAVE-RECEIVER) Acknowledge
(MASTER-TRANSMITTER)
SDAleftHIGH bytransmitter Acknowledge clockpulse
(MASTER)
Figure Slave-Receiver Acknowledge
newdatatransfer.
(SLAVE-TRANSMITTER)
SDAleftHIGH bytransmitter SDAleftHIGH byreceiver acknowledge Acknowledge clockpulse
(MASTER-RECEIVER) (MASTER)
STOPorrepeated STARTcondition
Figure Master-Receiver Acknowledge
Addressing
Slaveaddress
Figure Slave Addressing
Data format
functioninsidethechip. write register, master first generates START condition.Then sends slave address device master writes register address wants access waits slave acknowledge.The master then writesthenewregisterdata.Once theslaveacknowledges, themaster generates aSTOPcondition toendthe data transfer.
Startcondition
Masterwillwritedata
Stopcondition
Mastersends slaveaddress
Masterwrites registeraddress Slaveacknowledge
Masterwrites registerdata Slaveacknowledge
Slaveacknowledge
Figure Register Byte Write Protocol
master writes register address wants access waits slave acknowledge.The master then
Startcondition
Masterwillwritedata
Repeatedstart condition
Masterwillreaddata
Stopcondition
Mastersends slaveaddress
Masterwrites registeraddress Slaveacknowledge Slaveacknowledge
Mastersends slaveaddress
Masterreads registerdata Slaveacknowledge Masternot acknowledge
Figure Register Byte Read Protocol
Application Diagram
HOST SYSTEM SLEEP CLK_IO
DVDD
RESET SDASLV SCKSLV
HOST SYSTEM
RESET SDASLV SCKSLV AVDD AGND DGND DVDD
Voltage Regulator
Voltage Regulator
Figure typical Application Diagram
Star connectedground
High Level gain selection needs optimum performance depending light levels.The flowcharts below
Sensor operation flowchart
Sensor Operation
Sensor gain optimization flowchart
Sensor Gain Optimization Hardware reset
Select sensor gain setting Hardware reset Acquire trim offset Select sensor gain setting
Acquire sensor reading
Acquire sensor output Stop
Sensor output optimum? Stop
Detail hardware reset asserting XRST) should
Setup Value Number Integration Time Slot
time registers adjust gain sensor.The from FFFH. More integration time slot will give highersensitivity.
Sensor Gain Settings
capacitors integration time slot sensor Address (Hex) Register CAP_RED CAP_GREEN CAP_BLUE CAP_CLEAR INT_RED INT_GREEN INT_BLUE INT_CLEAR Description Number channel capacitors Number green channel capacitors Number blue channel capacitors Number clear channel capacitors Number channel integration time slots Number green channel integration time slots Number blue channel integration time slots Number clear channel integration time slots
Setup Value Number Capacitor
following value written each capacitor registers adjust gain sensor.The registers control number capacitors selected each channel. maximum selectable capacitor with registers starting from (i.e. 15). Less Value (Hex) Number Capacitor
Sensor Output Registers
obtain sensor value,`01' must written Address (Hex) Register CTRL DATA_RED_LO DATA_RED_HI DATA_GREEN_LO DATA_GREEN_HI DATA_BLUE_LO DATA_BLUE_HI DATA_CLEAR_LO DATA_CLEAR_HI Description Control register channel data byte channel data high byte Green channel data byte Green channel data high byte Blue channel data byte Blue channel data high byte Clear channel data byte Clear channel data high byte
Mechanical Drawing
Note: Dimensionsareinmilimeters(mm) a.Lineartolerance=+/-0.1mm b.Angulartolerance=+/-1°
Configuration
DVDD CLKIO DGND SCKSLV SDASLV RESET AVDD SLEEP AGND
Dimensions
Description Package Body Dimension Package Body Dimension Package Height Ball Diameter Total Count Nominal (um)
Information
Name DVDD SCKSLV AVDD CLKIO SDASLV SLEEP DGND RESET AGND Type Power Input Power Input Input/Output Input Ground Input Power Description Digital power Serial interface clock Analog power External clock input Bidirectional data pin. pull-up resistor should tied SDASLV because goes tri-state output logic When SLEEP device goes into sleep mode. sleep mode, analog circuits powered down clock signal gated away from core logic resulting very current consumption. digital ground Global, asynchronous, active-low system reset. When asserted low, XRST resets registers. Minimum reset pulse must provided external circuitry. analog ground
Recommended Underfill Type Characteristic
HenkelFP4548 Lowmoistureabsorption LowCTE Underfillupto70-85%ofheight
Recommended stencil design
Stencilthickness 5mils Stenciltype NiElectroforming StencilApertureType Square StencilAperture AdditionalFeature 310um Roundedsquareedge 310um
Height 70~85%
Underfill
Recommended land design
NiAuflashovercopperpad PadDiameter(C)=0.20mm NSMDDiameter(D)=0.25~0.30mm
NSMD
560um
After soldering mounting precaution
surface. Precaution:
LoadingForce
Recommended Reflow Profile
T-peak T-reflow
217~220 Delta-Flux max. °C/sec. Delta-Cooling max. °C/sec.
TEMPERATURE
T-max. T-min.
180°C 160°C
Delta-Ramp max. °C/sec.
sec.
t-comp t-pre
sec.
t-reflow
TIME
Recommendations Handling Storage ADJD-S311-CR999
sensitive product important ensure reliability product. refer Avago Application Note AN5305
Storage before
should also sealed with moisture absorbent material (Silica Gel) indicator card (cobalt chloride) indicatethemoisturewithinthebag
Control after opening
components must kept <30°C/60%RH time high temperature related process including
Control unfinished reel
Control assembled boards
lifeof168hrs
Baking required
Package Tape Reel Dimensions
Reel Dimensions
R10.65 +1.5* 12.4
R5.2
55.0 178.0
176.0 EMBOSSED RIBS RAISED: 0.25 WIDTH: 1.25
BACK VIEW
18.0 MAX.*
Notes: 1.*Measureathubarea. 2.Allflangeedgestoberounded.
Carrier Tape Dimensions
(E1)1.75±0.10 (F)5.50±0.05
(P0)4.00±0.10 1.50
0.10 0.00
(P2)2.00±0.10
(T)0.30±0.05
(W)12.00±0.10
1.50
R0.50
(P1)8.00±0.10
(B0)2.60±0.10
(K0)0.90±0.10
(A0)2.60±0.10
Notes:
SENSOR
SAMPLE DATA
OFFSET DATA
WIDTH INT_RED[7:0] INT_RED[11:8] INT_GREEN[7:0] INT_GREEN[11:8] INT_BLUE[7:0] INT_BLUE[11:8] INT_CLEAR[7:0] INT_CLEAR[11:8] DATA_RED[7:0] DATA_GREEN[7:0] DATA_BLUE[7:0] DATA_CLEAR[7:0] SIGN_RED SIGN_GREEN SIGN_BLUE SIGN_CLEAR OFFSET_RED[6:0] OFFSET_GREEN[6:0] OFFSET_BLUE[6:0] OFFSET_CLEAR[6:0] sign DATA_CLEAR[9:8] DATA_BLUE[9:8] DATA_GREEN[9:8] 11/10-bit data DATA_RED[9:8] CAP_CLEAR[3:0] CAP_BLUE[3:0] CAP_GREEN[3:0] CAP_RED[3:0] NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER NUMBER BITS EXTCLK SLEEP TOFS BITS GOFS GSSR RESET (DEC) TYPE ACCESS NOTES
Appendix Sensor Register List
(DEC)
(HEX)
MNEMONIC
CTRL
CONFIG
CAP_RED
CAP_GREEN
CAP_BLUE
CAP_CLEAR
INT_RED_LO
INT_RED_HI
INT_GREEN_LO
INT_GREEN_HI
INT_BLUE_LO
INT_BLUE_HI
INT_CLEAR_LO
INT_CLEAR_HI
DATA_RED_LO
DATA_RED_HI
DATA_GREEN_LO
DATA_GREEN_HI
DATA_BLUE_LO
DATA_BLUE_HI
DATA_CLEAR_LO
DATA_CLEAR_HI
OFFSET_RED
OFFSET_GREEN
OFFSET_BLUE
OFFSET_CLEAR
Appendix Sensor Register List
1)CTRL:ControlRegister
GOFS
GSSR
GSSR GOFS
Notavailable.
2)CONFIG:ConfigurationRegister
EXTCLK
SLEEP
TOFS
EXTCLK SLEEP TOFS
Notavailable. Externalclockmode.Activehigh. Trimoffsetmode.Activehigh.
CAP_RED Notavailable. Numberofredchannelcapacitors. CAP_RED[3:0]
CAP_GREEN Notavailable. Numberofgreenchannelcapacitors.
CAP_GREEN[3:0]
CAP_BLUE Notavailable. Numberofbluechannelcapacitors.
CAP_BLUE[3:0]
CAP_CLEAR Notavailable. Numberofclearchannelcapacitors.
CAP_CLEAR[3:0]
INT_RED[7:0] INT_RED Number channel integration time slots. INT_RED[11:8]
INT_GREEN[7:0] INT_GREEN Number green channel integration time slots.
INT_GREEN[11:8]
INT_BLUE[7:0] INT_BLUE Number blue channel integration time slots.
INT_BLUE[11:8]
INT_CLEAR[7:0] INT_CLEAR Number clear channel integration time slots.
INT_CLEAR[11:8]
DATA_RED[7:0] DATA_RED RedchannelADCdata.
DATA_RED available. channel data.
DATA_RED[9:8]
DATA_GREEN[7:0] DATA_GREEN GreenchannelADCdata.
DATA_GREEN available. Green channel data.
DATA_GREEN[9:8]
DATA_BLUE[7:0] DATA_BLUE BluechannelADCdata.
DATA_BLUE available. Blue channel data.
DATA_BLUE[9:8]
DATA_CLEAR[7:0] DATA_CLEAR ClearchannelADCdata.
DATA_CLEAR available. Clear channel data.
DATA_CLEAR[9:8]
SIGN_RED SIGN_RED OFFSET_RED Signbit.0=POSITIVE,1=NEGATIVE. RedchannelADCoffsetdata. OFFSET_RED[6:0]
SIGN_GREEN SIGN_GREEN Signbit.0=POSITIVE,1=NEGATIVE. OFFSET_GREEN[6:0]
OFFSET_GREEN GreenchannelADCoffsetdata.
SIGN_BLUE SIGN_BLUE Signbit.0=POSITIVE,1=NEGATIVE. OFFSET_BLUE[6:0]
OFFSET_BLUE BluechannelADCoffsetdata.
SIGN_CLEAR SIGN_CLEAR Signbit.0=POSITIVE,1=NEGATIVE. OFFSET_CLEAR[6:0]
OFFSET_CLEAR ClearchannelADCoffsetdata.
product information complete list distributors, please site:
www.avagotech.com
Avago, Avago Technologies, logo trademarks Avago Technologies, Limited United States other countries. Data subject change. Copyright Avago Technologies Limited. rights reserved. AV0-09EN July

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