Miniature Surface-Mount Digital Color Sensor ADJD-S312-CR999 cost
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ADJD-S312-CR999
Miniature Surface-Mount Digital Color Sensor
ADJD-S312-CR999 cost effective, CMOS digital output color sensor miniature surface-mount package with mere size 3x3x0.77mm. comes with integrated filters, analog-to-digital converter digital core communication sensitivity control. output allows direct interface micro-controller other logic control further signal processing without need additional components. This device designed cater wide dynamic range illumination level ideal applications like portable mobile devices which demand higher integration, smaller size power consumption. Sensitivity control performed serial interface optimized individually different color channel. sensor also used conjunction with white reflective color management.
Features
Fully integrated digital color sensor Digital 2-wire serial interface Industry's smallest form factor 3x3x0.77mm Adjustable sensitivity different levels illumination Uniformly distributed photodiode array resolution channel output Built internal oscillator Sleep function when external components supply voltage (VDD) 2.6V 70°C operating temperature Lead free package
Applications
General color detection measurement Mobile appliances such mobile phones, PDAs, players,etc Consumer appliances Portable medical equipments Portable color detector/reader
WARNING: Standard CMOS handling precautions should observed avoid static discharge.
AVAGO TECHNOLOGIES' PRODUCTS SOFTWARE SPECIFICALLY DESIGNED, MANUFACTURED AUTHORIZED SALE PARTS, COMPONENTS ASSEMBLIES PLANNING, CONSTRUCTION, MAINTENANCE DIRECT OPERATION NUCLEAR FACILITY MEDICAL DEVICES APPLICATIONS. CUSTOMER SOLELY RESPONSIBLE, WAIVES RIGHTS MAKE CLAIMS AGAINST AVAGO TECHNOLOGIES SUPPLIERS, LOSS, DAMAGE, EXPENSE LIABILITY CONNECTION WITH SUCH USE.
General Specifications
Feature
Interface Supply
Value
100kHz serial interface 2.6V digital (nominal), 2.6V analog (nominal)
Powering Device
voltage must applied IO's during power-up power-down ramp time
VDDD VDDA
tVDD_RAMP
Protection Diode Turn-On During Power-Up Power-Down
particular power-up power-down sequence must used prevent diode from turning inadvertently. figure above describes sequence. general, AVDD DVDD should power-up powerdown together prevent diodes from turning inadvertently. During this period, voltage should applied IO's same reason.
Ground Connection
AGND DGND must both preferably star-connected central power source shown application diagram. potential difference between AGND DGND cause diodes turn inadvertently.
Block Diagram
SDASLV SCLSLV XRST SLEEP Control Core Gain Selection PHOTOSENSOR ARRAY
PHOTOCURRENT VOLTAGE CONVERSION
PHOTOCURRENT VOLTAGE CONVERSION GREEN
PHOTOCURRENT VOLTAGE CONVERSION BLUE
ANALOG DIGITAL CONVERSION
Electrical Specifications Absolute Maximum Ratings (Notes
Parameter
Storage temperature Digital supply voltage, DVDD DVSS Analog supply voltage, AVDD AVSS Input voltage Solder Reflow Peak temperature Human Body Model rating
Symbol Minimum Maximum Units Notes
TSTG_ABS VDDD_ABS VDDA_ABS VIN_ABS TL_ABS ESDHBM_ABS -0.5 -0.5 -0.5 VDDD+0.5 pins, human body model JESD22-A114-B pins
Recommended Operating Conditions
Parameter
Free operating temperature Digital supply voltage, DVDD DVSS Analog supply voltage, AVDD AVSS Output current load high Output current load Input voltage high level (Note Input voltage level (Note
Symbol
VDDD VDDA
Minimum
Maximum
Units
Notes
VDDD
VDDD VDDD
Electrical Specifications
Over Recommended Operating Conditions (unless otherwise specified)
Parameter
Output voltage high level (Note Output voltage level (Note Dynamic supply current (Note 7,8) Static supply current (Note Sleep-mode supply current (Note Input leakage current
Symbol Conditions Minimum
IDD_DYN IDD_STATIC IDD_SLP ILEAK (Note (Note (Note VDDD-0.8
Typical (Note
VDDD-0.4
Maximum
Units
Electrical Specifications
Parameter
Internal clock frequency
Symbol Conditions Minimum
fCLK
Typical (Note
Maximum
Units
Optical Specification
Parameter
Dark offset*
*code from dark code (dark code 128LSB)
Symbol Conditions Minimum
Typical (Note
Maximum
Units
Minimum sensitivity (note
Parameter
Irradiance Responsivity
Symbol
Conditions
Refer Note Refer Note Refer Note
Minimum
Typical (Note Maximum
Units
LSB/ (mWcm-2)
Maximum sensitivity (note
Parameter
Irradiance Responsivity
Symbol
Conditions
Refer Note Refer Note Refer Note
Minimum
Typical (Note Maximum
1150 1640 2310
Units
LSB/ (mWcm-2)
Minimum sensitivity (note
Parameter
Saturation Irradiance
Symbol
Conditions
Refer Note Refer Note Refer Note
Minimum
Typical (Note Maximum
4.17 2.88 1.90
Units
mWcm-2
Maximum sensitivity (note
Parameter
Saturation Irradiance
Symbol
Conditions
Refer Note Refer Note Refer Note
Minimum
Typical (Note Maximum
0.13 0.09 0.06
Units
mWcm-2
Notes: "Absolute Maximum Ratings" those values beyond which damage device occur. device should operated these limits. parametric values defined "Electrical Specifications" table guaranteed absolute maximum ratings. "Recommended Operating Conditions" table will define conditions actual device operation. Unless otherwise specified, voltages referenced ground. Specified room temperature (25°C) VDDD VDDA 2.6V. Applies pins. Applies pins. SDASLV tri-state when output logic high. Minimum depends pull-up resistor value. Applies pins. Dynamic testing performed with operating mode representative typical operation. Refers total device current consumption. Output bidirectional pins loaded. Test condition blue light peak wavelength spectral half width Test condition green light peak wavelength spectral half width Test condition light peak wavelength spectral half width Saturation irradiance (MSB)/(Irradiance responsivity)
Spectral response
Relative sensitivity
Wavelength (nm)
Typical spectral response when gains color channels equal.
Serial Interface Timing Information
Parameter clock frequency (Repeated) START condition hold time Data hold time clock period clock high period Repeated START condition setup time Data setup time STOP condition setup time free time between START STOP conditions Symbol fscl tHD:STA tHD:DAT tLOW tHIGH tSU:STA tSU:DAT tSU:STO tBUF Minimum Maximum 3.45 Units
tHD:STA
tHIGH
tSU:DAT
tSU:STA
tBUF
tLOW tHD:DAT tHD:STA tSU:STO
Figure Serial Interface Timing Waveforms
High Level sensor needs configured before used. gain selection needs optimum performance depending light levels. flowcharts below describe different procedures required.
SENSOR GAIN OPTIMIZATION Step Hardware Reset Step Device Initialization Step Select sensor gain settings Step Acquire readings
SENSOR OPERATION Step Hardware Reset Step Device Initialization Step Select sensor gain settings Step Acquire dark offset store current offset values
readings optimum?
Step Acquire readings Step Compute sensor values
STOP
STOP
Sensor gain optimization flowchart Sensor operation flowchart
Please refer application note more detailed information.
Detail hardware reset asserting XRST) should performed before starting operation. user controls configures device programming internal registers through serial interface. start application, following setup data must written setup registers:
Address (Hex)
Setup Value Integration Time following value written each integration time registers adjust gain sensor. default value after reset these registers 07H.
Value (Hex)
Integration Time Slot
Register
SETUP0 SETUP1 SETUP2 SETUP3 SETUP4
Setup Data (Hex)
Sensor Gain Settings sensor gain adjusted varying photodiode size integration time sensor manually through following registers. Sensor Sensitivity Photodiode Size Integration Time Slot
Address (Hex)
Register
PDASR PDASG PDASB TINTR TINTG TINTB
Channel Photodiode Size Green Channel Photodiode Size Blue Channel Photodiode Size Channel Integration Time Green Channel Integration Time Blue Channel Integration Time
Sensor Output Registers obtain sensor value, `02' must written register before reading Sensor Output Registers.
Setup Value Photodiode Size following value written each photodiode size registers adjust gain sensor. default value after reset these registers 07H.
Value (Hex)
Address (Hex) Register
Acquire sensor analog digital converter (ADC) values when written. Reset when sensor acquisition completed Sensor channel value. Sensor Green channel value. Sensor Blue channel value.
ADCR ADCG ADCB
Photodiode Size
Full
Serial Interface Reference
Description programming interface ADJD-S312 2wire serial bus. consists serial clock (SCL) serial data (SDA) line. line bidirectional ADJD-S312 must connected through pull-up resistor positive power supply. When free, both lines HIGH. 2-wire serial ADJD-S312 requires device master while other devices must slaves. master device that initiates data transfer bus, generates clock signal terminates data transfer while device addressed master called slave. Slaves identified unique device addresses. Both master slave transmitter receiver master controls direction data transfer. transmitter device that sends data receiver device that receives data from bus. ADJD-S312 serial interface always operates slave transceiver with data transfer rate 100kbit/s. START/STOP Condition master initiates terminates serial data transfers. begin serial data transfer, master must send unique signal called START condition. This defined HIGH transition line while HIGH. master terminates serial data transfer sending another unique signal called STOP condition. This defined HIGH transition line while HIGH. considered busy after START condition. will considered free certain time after STOP condition. stays busy repeated START (Sr) sent instead STOP condition. START repeated START conditions functionally identical.
Data Transfer master initiates data transfer after START condition. Data transferred bits with master generating clock pulse each sent. data valid, data line must stable during HIGH period clock line. Only during period clock line data line change state either HIGH LOW.
Data valid Figure Data Transfer Data change
clock line synchronizes serial data transmission data line. always generated master. frequency clock line vary throughout transmission long still meets minimum timing requirements. master default drives data line. slave drives data line only when sending acknowledge after master writes data slave when master requests slave send data. data line driven master implemented negative edge clock line. master sample data driven slave positive edge clock line. Figure shows example master implementation clock line data line synchronized.
data sampled positive edge
data driven negative edge Figure Data Synchronization
START condition
STOP condition
Figure START/STOP Condition
complete data transfer 8-bits long 1-byte. Each byte sent most significant (MSB) first followed acknowledge acknowledge bit. Each data transfer send unlimited number bytes (depending data format). Figure Acknowledge/Not acknowledge receiver must always acknowledge each byte sent data transfer. case slave-receiver master-transmitter, slave-receiver does send acknowledge bit, master-transmitter either
STOP transfer generate repeated START start transfer. Figure case master-receiver slave-transmitter, master generates acknowledge signal data transfer slave-transmitter. master then send STOP repeated START condition begin data transfer. cases, master generates acknowledge acknowledge clock pulse. Figure
START repeated START condition
Figure Data Byte Transfer
STOP repeated START condition
pulled receiver (SLAVE-RECEIVER) (MASTER-TRANSMITTER) (MASTER) Acknowledge
left HIGH transmitter
Acknowledge clock pulse
Figure Slave-Receiver Acknowledge
(SLAVE-TRANSMITTER) (MASTER-RECEIVER) (MASTER)
left HIGH transmitter left HIGH receiver acknowledge Acknowledge clock pulse
Figure Master-Receiver Acknowledge
STOP repeated START condition
Addressing Each slave device serial needs have unique address. This first byte that sent master-transmitter after START condition. address defined first seven bits first byte. eighth least significant (LSB) determines direction data transfer. `one' first byte indicates that master will read data from addressed slave (master-receiver slavetransmitter). `zero' this position indicates that master will write data addressed slave (mastertransmitter slave-receiver). device whose address matches address sent master will respond with acknowledge first byte itself slave-transmitter slavereceiver depending first byte. slave address ADJD-S312 0x58 (7-bits).
Data format ADJD-S312 uses register-based programming architecture. Each register unique address controls specific function inside chip. write register, master first generates START condition. Then sends slave address device wants communicate with. least significant (LSB) slave address must indicate that master wants write slave. addressed device will then acknowledge master. master writes register address wants access waits slave acknowledge. master then writes register data. Once slave acknowledges, master generates STOP condition data transfer. figure read from register, master first generates START condition. Then sends slave address device wants communicate with. least significant (LSB) slave address must indicate that master wants write slave. addressed device will then acknowledge master. master writes register address wants access waits slave acknowledge. master then generates repeated START condition resends slave address sent previously. least significant (LSB) slave address must indicate that master wants read from slave. addressed device will then acknowledge master. master reads register data sent slave sends acknowledge signal stop reading. master then generates STOP condition data transfer. figure
Slave address
Figure Slave Addressing
Start condition
Master will write data
Stop condition
Master sends slave address
Master writes register address Slave acknowledge
Master writes register data Slave acknowledge
Slave acknowledge
Figure Register Byte Write Protocol
Start condition
Master will write data
Repeated start condition
Master will read data
Stop condition
Master sends slave address
Master writes register address Slave acknowledge Slave acknowledge
Master sends slave address
Master reads register data Slave acknowledge Master acknowledge
Figure Register Byte Read Protocol
Powering Device
Ground Connection AGND DGND must both preferably star-connected central power source shown application diagram. potential difference between AGND DGND cause diodes turn inadvertently.
Application Diagrams
HOST SYSTEM
SLEEP
DVDD
XRST HOST SYSTEM
XRST SDASLV SCLSLV
AVDD Voltage Regulator
AGND
DGND
DVDD Voltage Regulator
Star-connected ground
Information
NAME
AVDD AGND AGND SLEEP
TYPE
Power Ground Ground Input
DESCRIPTION
Analog power pin. analog ground. analog ground. When SLEEP=1, device goes into sleep mode. sleep mode, analog circuits powered down clock signal gated away from core logic resulting very current consumption. connect. Leave floating. connect. Leave floating. connect. Leave floating. connect. Leave floating. connect. Leave floating digital ground. SDASLV SCLSLV serial interface communications pins. SDASLV bidirectional data SCLSLV interface clock. pull-up resistor should tied SDASLV because goes tri-state output logic Digital power pin. analog ground. connect. Leave floating. Global, asynchronous, active-low system reset. When asserted low, XRST resets registers. Minimum reset pulse must provided external circuitry.
DGND SCLSLV SDASLV DVDD AGND XRST
connect connect connect connect connect Ground Input Input/Output (tri-state high) Power Ground connect Input
Configuration
AVDD DVDD
AGND DGND AGND
AGND SCLSLV
SLEEP SDASLV XRST
Package Dimensions
Note: Dimensions milimeters (mm) Standard tolerances (unless otherwise specified) Linear tolerance +/-0.1mm Angular tolerance +/-1°
Recommended Underfill Type Characteristic
moisture absorption type Total height underfill from plane cover Underfill cover side package
Height
Underfill
Recommended Reflow Profile
T-peak T-reflow
217~220 Delta-Flux max. °C/sec.
T-max.
180°C 160°C
TEMPERATURE
Delta-Cooling max. °C/sec.
T-min.
Delta-Ramp max. °C/sec.
sec.
t-comp t-pre
sec.
t-reflow
TIME
Recommended land design
NiAu flash over copper Diameter (C)= 0.20 NSMD Diameter (D)= 0.25 0.30
After soldering mounting precaution
Please ensure that soldered reflowed package that mounted exposed compression loading force directly perpendicular flat surface.
Precaution:
NSMD Excessive loading force directly perpendicular flat surface cause pre-mature failure.
Loading Force
Recommended Stencil Design
Stencil thickness Stencil type Stencil Aperture Type Stencil Aperture Additional Feature mils Electroforming Square Rounded square edge
Recommendations Handling Storage ADJD-S312
This product qualified Moisture Sensitive Level Jedec J-STD-020. Precautions when handling this moisture sensitive product important ensure reliability product. refer Avago Application Note AN5305 Handling Moisture Sensitive Surface Mount Devices details. Storage before Unopened moisture barrier (MBB) stored 30°C 90%RH less maximum year recommended open prior assembly (e.g. IQC) should also sealed with moisture absorbent material (Silica Gel) indicator card (cobalt chloride) indicate moisture within Control after opening humidity indicator card (HIC) shall read immediately upon opening components must kept <30°C/60%RH time high temperature related process including soldering, curing rework need completed within 168hrs Control unfinished reel unused components, they need stored sealed with desiccant desiccator <5%RH Control assembled boards soldered with components subjected other high temperature processes, need stored sealed with desiccant desiccator <5%RH ensure components have exceeded their floor life 168hrs Baking required "10%" "15%" indicator turns pink components exposed condition >30°C/60%RH time. components floor life exceeded 168hrs Recommended baking condition component form): 125°C 24hrs
Package Tape Reel Dimensions Carrier Tape Dimensions
4.00 0.10 NOTE 2.00 0.05 NOTE 1.55 0.05 0.50 TYP. 1.75 0.10 5.50 0.05 12.00 0.10 SECTION PITCH: WIDTH: 3.30 3.30 1.10 8.00 12.00
8.00 0.10
1.50 (MIN.)
0.30 0.05 SECTION NOTES: MEASURED ABOVE BASE POCKET. PITCHES CUMULATIVE TOLERANCE DIMENSIONS MILLIMETERS (mm).
Reel Dimensions
R10.65 +1.5* 12.4
R5.2
55.0 178.0
176.0 EMBOSSED RIBS RAISED: 0.25 WIDTH: 1.25
BACK VIEW
18.0 MAX.*
NOTES: *MEASURED AREA. FLANGE EDGES ROUNDED.
product information complete list distributors, please site:
www.avagotech.com
Avago, Avago Technologies, logo trademarks Avago Technologies, Limited United States other countries. Data subject change. Copyright 2007 Avago Technologies Limted. rights reserved. Obsoletes AV01-0402EN AV01-0687EN January 2007
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