Optical Mouse Sensor Description ADNS-2620 entry level, small for

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Optical Mouse Sensor Description ADNS-2620 entry level, small for

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ADNS-2620
Optical Mouse Sensor
Description ADNS-2620 entry level, small form factor optical mouse sensor. used implement nonmechanical tracking engine computer mice. Unlike predecessor, this optical mouse sensor allows more compact affordable optical mice designs. based optical navigation technology, which measures changes position optically acquiring sequential surface images (frames) mathematically determining direction magnitude movement. sensor housed 8-pin staggered dual inline package (DIP). designed with HDNS-2100 Lens, HLMP-ED80-xx000, HDNS-2200 Clip, providing optical mouse solution that compact affordable. There moving parts, precision optical alignment required, thereby facilitating high volume assembly. output format wire serial port. current information available registers accessed serial port. Resolution counts inch (cpi) with rates motion inches second (ips). Theory Operation ADNS-2620 based Optical Navigation Technology. contains Image Acquisition System (IAS), Digital Signal Processor (DSP) wire serial port. acquires microscopic surface images lens illumination system provided HDNS-2100, HDNS-2200, HLMP-ED80-xx000. These images processed determine direction distance motion.
Features Precise optical navigation technology Small form factor 12.5 footprint) mechanical moving parts Complete motion sensor Common interface general purpose controller Smooth surface navigation Programmable frame speed 3000 frames (fps) Accurate motion resolution High reliability High speed motion detector Wave solderable Single volt power supply Conforms suspend mode specifications Power conservation mode during times movement Serial port registers
Programming Data transfer
8-pin staggered dual inline package (DIP)
Applications Mice desktop PC's, workstations, portable PC's Trackballs Integrated input devices
Pinout ADNS-2620 Optical Mouse Sensor Number
OSC_IN OSC_OUT SDIO LED_CNTL REFA
Description
Oscillator input Oscillator output Serial Port Data (input output) Serial Port Clock (Input)
LED_CNTL
A2620 XYYWWZ
SDIO
OSC_OUT
OSC_IN
REFA
Digital Shutter Signal System Ground Input Internal reference Figure Mechanical drawing: view.
Figure Package outline drawing.
CAUTION: advisable that normal static precautions should taken handling assembly this component prevent damage and/or degradation which induced ESD.
Overview Optical Mouse Sensor Assembly NOTE: optical mouse sensor should inserted into reference point mechanical cutouts. Figures shown with HDNS-2100, HDNS-2200 HLMP-ED80-xx000. Avago Technologies provides IGES file drawing describing base plate molding features lens alignment. components shown Figure interlock they mounted onto defined features base plate. ADNS-2620 sensor designed mounting through hole PCB, looking down. There aperture stop features package that align lens. HDNS-2100 lens provides optics imaging surface well illumination surface optimum angle. Features lens align sensor, base plate, clip with LED. lens also large round flange provide long creepage path events that occur opening base plate. HDNS-2200 clip holds relation lens. LED's leads must formed first before inserting into clip. Then, both clip loaded PCB. clip interlocks sensor lens, through lens alignment features base plate. HLMP-ED80-xx000 recommended illumination. used with table shown Figure sufficient illumination guaranteed.
28.00 1.102 18.94 0.746 9.06 0.357 1.00 0.039
Clear Zone
3.50
0.138
12.60 0.496
11.10 0.437 1.25 0.049
1.35 4.91 0.053 0.193 29.15 1.148 0.80 0.031
7.45 0.293
13.73 0.541
DIMENSIONS
INCH
Figure Recommended mechanical cutouts spacing.
(Top view)
32.46 1.278
19.10 0.752
BASE PLATE
Dimensions mm/in. LENS RING
(Side view)
PLASTIC SPRING
CLIP
14.58 0.574
10.58 0.417
7.45 0.293
13.82 0.544
SENSOR
BASE PLATE ALIGNMENT POST
Figure assembly drawing ADNS-2620 shown with HLMP-ED80 (top side view).
HDNS-2200 (Clip) HLMP-ED80-xx000 ADNS-2620 (Sensor) Customer supplied
HDNS-2100 (Lens)
Customer supplied base plate with recommended alignment features IGES drawing
Figure Exploded view drawing.
SERIAL PORT
SDIO
SERIAL PORT
OSC_IN OSCILLATOR OSC_OUT RESONATOR
VOLTAGE REGULATOR POWER CONTROL
IMAGE PROCESSOR
REFA
VOLTAGE REFERENCE
Insert assembly over lens onto base plate aligning post retain assembly. sensor aperture ring should self-align lens. optical position reference base plate lens. Note that motion button presses must minimized maintain optical alignment. Install mouse case. There MUST feature case press down onto clip ensure components interlocked correct vertical height. Design Considerations Improving Performance flange lens been designed increase creepage clearance distance electrostatic discharge. table below shows typical values assuming base plate construction Avago supplied IGES file HDNS-2100 lens flange. Typical Distance
Creepage Clearance
VOLT POWER
CONTROL
CONTROL
Figure Block diagram ADNS-2620 optical mouse sensor.
Assembly Considerations Insert sensor other electrical components into PCB. Note: sensor should always reference point mechanical cutouts. Bend leads then insert into assembly clip until snap feature locks base. Insert LED/clip assembly into PCB. Wave solder entire assembly no-wash solder process utilizing solder fixture. solder fixture needed protect sensor during solder process. fixture should designed expose sensor leads solder while shielding
optical aperture from direct solder contact. solder fixture also used reference height sensor during wave soldering (Note: remove kapton tape during wave soldering). Place lens onto base plate. Remove protective kapton tape from optical aperture sensor. Care must taken keep contaminants from entering aperture. recommended place facing during entire mouse assembly process. should held vertically kapton removal process.
Millimeters
16.0
improved performance, lens flange sealed (i.e. glued) base plate. Note that lens material polycarbonate therefore, cyanoacrylate based adhesives other adhesives that damage lens should used.
Sensor Lens/Light Pipe
Clip
Base Plate Surface Figure Sectional view assembly highlighting optical mouse components (optical mouse sensor, clip, lens, LED, base plate).
D1.3 SHLD DVreg
Internal Image Sensor
HDNS 2100 Lens
100K ohms HLMP-ED80-xx000
SURFACE LED_CNTL ohms 2N3906
P0.5
Buttons
CYPRESS CY7C63723C-PC
SDIO
ADNS-2620
P1.0 P1.1
P0.6 P0.7 P0.3 P0.2
OSC_IN
Ceramic Resonaator
OSC_OUT
Murata CSALS24M0X53-B0 FCR24.0M2G
REFA
P0.0
P0.1
XTALOUT
XTALIN
(Optional)
HLMP-ED80
VALUE (Ohms) 32.0 32.0 32.0 32.0 32.0 61.2 32.0 73.9 32.0 84.4 32.0 32.0
Figure Circuit block diagram typical corded optical mouse using Avago ADNS-2620 optical mouse sensor.
Notes Bypass Capacitors Caps pins ground MUST have trace lengths LESS than caps must ceramic. Caps should have less than self inductance Caps should have less than ohms Surface mount parts recommended
Regulatory Requirements Passes worldwide analogous emission limits when assembled into mouse with unshielded cable following Avago recommendations. Passes EN61000-4-4/IEC801-4 EFTB tests when assembled into mouse with shielded cable following Avago recommendations. flammability level UL94 V-0.
Provides sufficient creepage/clearance distance avoid discharge when assembled into mouse according usage instructions above. safety consideration, please refer technical report available site www.Avago.com/ semiconductors.
Absolute Maximum Ratings Parameter
Storage Temperature Operating Temperature Lead Solder Temp Supply Voltage Input Voltage Input Voltage -0.5 -0.5 -0.5
Symbol
Minimum
Maximum
Units
Notes
seconds, below seating plane
pins, human body model Method 3015 SDIO, CLK, LED_CNTL OSC_IN, OSC_OUT, REFA
Recommended Operating Conditions Parameter
Operating Temperature Power Supply Voltage
Symbol
Minimum
Typical
Maximum
Units
Volts
Notes
Register values retained voltage transients below 4.10V greater than 3.9V
Power Supply Rise Time Supply Noise Clock Frequency Serial Port Clock Frequency Resonator Impedance Distance from Lens Reference Plane Surface Speed Acceleration Light Level onto SDIO Read Hold Time SDIO Serial Write-write Time SDIO Serial Write-read Time SDIO Serial Read-write Time SDIO Serial Read-read Time Data Delay after deactivated
fCLK SCLK XRES IRRINC tHOLD tSWW tSWR tSRW tSRR tCOMPUTE 23.0 24.0
25.0 fCLK/12 0.25 25,000 30,000
in/sec mW/m2 Results ±0.2 (See Figure frame rate 1500 frame rate 1500 Hold time valid data (Refer Figure Time between write commands (Refer Figure Time between write read operation (Refer Figure Time between read write operation (Refer Figure Time between read commands (Refer Figure After tCOMPUTE, registers contain data from first image after wakeup from Power-Down mode. additional frames stabilization movement occurred while Down. (Refer Data valid time before rising SCLK (Refer Figure Frame_Period register section Peak peak within 0-100 bandwidth ceramic resonator
Note that required mouse Power Figure SDIO Write Setup Time tSETUP
Frame Rate
1500
2300
frames/s
ADNS-2620
HDNS-2100
OBJECT SURFACE
Figure Distance from lens reference plane surface.
Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values 25°C, MHz, 1500 fps.
Parameter
Power Down (PD) Power after mode deactivated Power from Rise Fall Times SDIO
Symbol
tPUPD
Min.
1.33
Typ.
Max.
Units
Notes
clock cycle minimum after setting Configuration register. (Refer Figure From mode deactivation accurate reports frames (Refer Figure From valid accurate reports frames
(the rise time between 90%) (the fall time between 90%) Serial port will reset current transaction complete within tSPTT (Refer Figure supply current during ramp from 5.0V with rise time. Does include charging current bypass capacitors
Serial Port Transaction Timer Transient Supply Current
tSPTT IDDT
Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values 25°C, MHz, 1500 fps.
Parameter
Supply Current (mouse moving) Supply Current (mouse moving) Power Down Mode Current Input Voltage Input High Voltage Input Capacitance Input Resistance SDIO Input Voltage Input High Voltage Output Voltage Output High Voltage Drive Current Drive High Current Input Capacitance Input Resistance LED_CNTL Output Voltage Output High Voltage Drive Current Drive High Current OSC_IN Input Resistance Input Capacitance Input High Voltage Input Voltage
Symbol
IDDPD
Min.
Typ.
Max.
Units
Notes
VDD=4V, Load rise fall
External clock source External clock source
Timing
Note: timing circuits shown, from Figure onwards, based resonator frequency.
Power Down Deactivation (610)
Power Down deactivated
frames pupd
tCOMPUTE (See Figure
Figure Power timing mode.
Power Down deactivated Power Down Deactivation Oscillator Start CURRENT SCLK Reset Count Initialization 2410 Acquisition
Optional transactions with image data
tcompute
transactions with image data default frame rate
Figure Details wake-up timing after
Power-down Mode (PD) Timing ADNS-2620 placed power-down mode setting configuration register serial port write operation. Note that while writing configuration register, other bits must written with their original value order keep current configuration. After setting configuration register, wait least system clock cycles. chip
power-down mode, clear configuration register serial port write operation. (CAUTION! power-down mode, timeout SPTT will function. Therefore, partial command should sent. Otherwise, sensor into hang-up state). While sensor power-down mode, only data will written configuration register. Writing other configuration
register values will have effect. accurate report after power-up, wait total period before microcontroller able issue write/read operation ADNS-2620. sensor register settings, prior power-down mode, will remain during powerdown mode.
clock cycles
SDIO Figure Power-down timing.
address configuration register 1000000. Assume that original content configuration register 0x00.
Write Operation Configuration Register Address Configuration Register Data (0x40)
SDIO
Figure Power-down configuration register writing operation.
Setting power down simply sets analog circuitry into current state. Note: LED_CNTL, SDIO will tri-stated during power down mode.
Typical Performance Characteristics
Performance characteristics over recommended operating conditions. Typical values 25°C, MHz, 1500 fps.
Parameter
Path Error (Deviation) expressed surfaces.
Symbol
PError
Min.
Typ.
Max.
Units
Notes
Path Error (Deviation) error from ideal cursor path. percentage total travel measured over standard
following graphs (Figures 14-18) typical performance ADNS-2620 sensor, assembled shown assembly drawing with HDNS-2100 Lens/Prism, HDNS-2200 clip, HLMPED80-xx000 (See Figure
RELATIVE RESPONSIVITY
Burl Formica White Paper Manila Black Copy Black Walnut
White Paper Manila Black Copy
-0.8 -0.6 -0.4 -0.2 (mm)
1000
VELOCITY (ips)
WAVELENGTH (nm)
Figure Typical Resolution (comparative surfaces)
Figure Typical Resolution Velocity 1500 fps.
Figure Wavelength Responsivity[1].
100%
100%
-0.6 -0.2
Notes: ADNS-2620 designed optimal performance when used with HLMP-ED80-xx000 (red nm). with other colors (i.e., blue, green), please consult factory. When using alternate LEDs, there also performance degradation additional safety considerations. Distance from Lens Reference plane Surface. Depth Field.
-0.6
-0.2
(mm)
(mm)
Figure Typical Resolution Height different currents manila.
Figure Typical Resolution Height different currents black.
Synchronous Serial Port synchronous serial port used read parameters ADNS-2620, also read motion information. port wire, half duplex port. host microcontroller always initiates communication; ADNS-2620 never initiates data transfers.
SCK: serial port clock. always generated master (the microcontroller). SDIO: data line. Write Operation Write operations, where data going from microcontroller ADNS-2620, always initiated microcontroller
consists bytes. first byte contains address (seven bits) indicate data direction. second byte contains data. transfer synchronized SCK. microcontroller changes SDIO falling edges SCK. ADNS-2620 reads SDIO rising edges SCK.
Cycle
SDIO
DON'T CARE
SDIO Driven Microcontroller
Figure Write operation.
SDIO
tsetup
Figure SDIO setup hold times pulse width.
Read Operation read operation, meaning data that going from ADNS-2620 microcontroller, always initiated microcontroller consists bytes. first byte that contains address written microcontroller indicate data direc-
tion. second byte contains data driven ADNS-2620. transfer synchronized SCK. SDIO changed falling edges read every rising edge SCK. microcontroller must High-Z state after last address data bit. ADNS-2620 will High-Z state after
last data bit. Another thing note during read operation that needs delayed after last address data ensure that ADNS-2620 least prepare requested data. This shown timing diagrams below (See Figures 23).
Cycle SDIO
SDIO Driven Microcontroller Detail
SDIO Driven ADNS-2620 Detail
Figure Read operation.
HOLD
Detail
Microcontroller ADNS-2620 SDIO handoff SDIO
Hi-Z
Figure Microcontroller ADNS-2620 SDIO handoff.
Detail
ADNS-2620 Microcontroller SDIO handoff
SDIO
Released ADNS-2620
next address Driven microcontroller
Figure ADNS-2620 microcontroller SDIO handoff.
NOTE: high state minimum data hold time ADNS-2620. Since falling edge actually start next read write command, ADNS-2620 will hold state SDIO line until falling edge SCK. both write read operations, driven microcontroller.
Forcing SDIO Line Hi-Z State There times when SDIO line from ADNS-2620 should Hi-Z state. example, microprocessor completed write ADNS-2620, SDIO line will into Hi-Z state, because SDIO configured input. However, last operation from microprocessor read, ADNS-2620 will hold state SDIO until falling edge SCK. place SDIO into Hi-Z state, activate power-down mode writing configuration register. Then, powerdown mode stay activated, with ADNS-2620 shutdown state, powerdown mode deactivated, returning ADNS-2620 normal operation. both conditions, SDIO line will into Hi-Z state.
Timing
Activated
clock cycles
SDIO
Hi-Z
Figure SDIO Hi-z state timing.
Another method SDIO line into Hi-Z state, while maintaining ADNS-2620 normal mode, write data invalid address such 0x00 address 0x77. SDIO line will into Hi-Z state after write operations.
Required Timing between Read Write Commands (tsxx) There minimum timing requirements between read write commands serial port.
SCLK
Address Write Operation Data Address Write Operation Data
Figure Timing between write commands.
rising edge last data second write command occurs before
required delay, then first write command complete correctly.
Address
Data
Address
Write Operation
Next Read Operation
Figure Timing between write read commands.
rising edge last address read command occurs before
required delay, then write command complete correctly.
tSRW tSRR >250
Address
Data
Address
Read Operation
Figure Timing between read either write subsequent read commands.
Next Read Write Operation
falling edge first address either read write command must
least after last rising edge last data previous read operation.
Error Detection Recovery ADNS-2620 microcontroller might synchronization events, power supply droops microcontroller firmware flaws. ADNS-2620 transaction timer serial port. sixteenth rising edge spaced more than approximately milliseconds from first edge current transaction, serial port will reset. Invalid addresses: Writing invalid address will have effect. Reading from invalid address will return zeros. Collision detection SDIO only time that ADNS-2620 drives SDIO line during READ operation. avoid data collisions, microcontroller should relinquish SDIO before falling edge after last address bit. Then ADNS-2620 begins drive SDIO after next rising edge SCK. Next, ADNS-2620 relinquishes SDIO within falling edge after last data bit. microcontroller begin driving SDIO time after that. order maintain power consumption normal operation when
high, microcontroller should leave SDIO floating until next transmission (although that will cause communication difficulties). case synchronization failure, both ADNS-2620 microcontroller drive SDIO. ADNS-2620 withstand short circuit current will withstand infinite duration short circuit conditions. microcontroller verify successful write operation issuing read command same address comparing written data read data. microcontroller verify synchronization serial port periodically reading product from status register (Address: 0x41). Notes Power-up Serial Port sequence which VDD, SDIO during powerup affect operation serial port. diagram below shows what happen shortly after powerup when microprocessor tries read data from serial port. This diagram shows rising valid levels, some point microcontroller starts
program, sets SDIO lines outputs, sets them high. Then, microcontroller waits ensure ADNS-2620 powered ready communicate. microprocessor then tries read from location 0x41, Status register, expecting value 0x0b010XXXXX. receives this value, then knows that communication ADNS2620 operational. problem occurs ADNS-2620 powers before microprocessor sets SDIO lines outputs high. ADNS-2620 sees raising valid rising edge, clocks state SDIO first address (sets either read write depending upon state). case SDIO low, read operation will start. When microprocessor actually begins send address, ADNS-2620 already first address. When seventh sent microprocessor, ADNS-2620 valid address, drives SDIO line high within (see detail Figure Figure 20). This results fight SDIO. Since address wrong, data sent back will incorrect. case SDIO high, write operation will start. address data will synchronization, causing wrong data written wrong address. Solution solve problem waiting serial port timer time out.
SPTT
Address 0x41 Data 0x0b010XXXXX
SDIO
Don't Care State
Figure Power-up serial port sequence.
Serial Port Timer Timeout
SPTT
Address 0x41 Data 0x0b010XXXXX
SDIO
Don't Care State
Figure Power-up serial port timer sequence.
microprocessor waits least tSPTT from valid, will ensure that ADNS-2620 powered timer timed out. This assumes that microprocessor ADNS-2620 share same power supply. not, then microprocessor must wait tSPTT from ADNS-2620 valid. Then when toggles address, ADNS-2620 will sync with microprocessor. Resync Note microprocessor ADNS-2620 sync, then data either written read from registers will incorrect. easy solve this watchdog timer timeout sequence resync parts after incorrect read.
Power-up ADNS-2620 on-chip internal power-up reset (POR) circuit, which will reset chip when reaches valid value chip function. Soft Reset ADNS-2620 also given reset command time serial port. timing transactions same those just specified power-up mode previous section. proper perform soft reset ADNS-2620 microcontroller starts transaction sending write operation containing address configuration
register data value 0x80. Since reset set, ADNS-2620 will reset other bits written into configuration register this time properly written into Configuration Register. After chip been reset, very quickly, ADNS-2620 will clear reset there need microcontroller rewrite Configuration Register reset digital section ready takes frames analog section settle.
Reset Occurs here
SDIO
Figure ADNS-2620 soft reset sequence timing.
Soft reset will occur when writing 0x80 configuration register.
Write Operation
Configuration Register Address
Configuration Register Data
SDIO
Figure Soft reset configuration register writing operation.
Programming Guide Registers ADNS-2620 programmed through registers, serial port, configuration motion data read from these registers.
Register
Configuration Status Delta_Y Delta_X SQUAL sensor Maximum_Pixel Minimum_Pixel Pixel_Sum Pixel Data Shutter_Upper Shutter_Lower Frame Period
Address
0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B
Notes
Reset, Power Down, Forced Awake, Product Mouse state Asleep Awake Movement Movement Measure number features visible
Actual picture surface
Configuration Access: Read/Write
Field Data Type: field
Address: 0x40 Reset Value: 0x00
USAGE: Configuration register allows user change configuration sensor. Shown below bits, their default values, optional values.
Field Name
Description
Reset effect Reset part Power down Normal operation power down analog circuitry Shutter Mode Shutter mode (LED always even motion sec) Shutter mode (LED only when electronic shutter open) Reserved Forced Awake Mode Normal, fall asleep after second movement (1500 frames/s) Always awake
Status Access: Read
Field Data Type: Field
Address: 0x41 Reset Value: 0x41
Reserved Reserved Reserved Reserved Awake
USAGE: Status information type mouse sensor, current state mouse.
Field Name
Reserved Awake
Description
Product (010 ADNS-2620) Reserved future Mouse State Asleep Awake
Delta_Y Access: Read
Field
Address: 0x42 Reset Value: 0x00
Data Type: Eight complement number. USAGE: movement counted since last report. Absolute value determined resolution. Reading clears register.
Motion -128 -127
+126
+127
Delta_Y
Delta_X Access: Read
Field
Address: 0x43 Reset Value: 0x00
Data Type: Eight complement number. USAGE: movement counted since last report. Absolute value determined resolution. Reading clears register
Motion
-128
-127
+126
+127
Delta_X
SQUAL Access: Read
Address: 0x44 Reset Value: 0x00
Field
Data Type: Upper bits 9-bit integer. USAGE: SQUAL (Surface QUALity) measure number features visible sensor current frame. Number Features SQUAL Register Value maximum value 255. Since small changes current frame result changes SQUAL, variations SQUAL when looking surface expected. graph below shows sequentially acquired SQUAL values, while sensor moved slowly over white paper. SQUAL nearly equal zero when there surface below sensor.
SQUAL Values (White Paper)
SQUAL VALUE
1.50 1.25 1.00 0.75 0.50 0.25 -1.0
NORMALIZED SQUAL VALUE
focus point important could affect SQUAL value. Figure shows another setup with various z-heights. This graph clearly shows that SQUAL value dependent focus distance. Note: data obtained getting multiple readings over different heights.
-0.6
-0.2
DELTA FROM NOMINAL FOCUS (mm)
Figure Typical Mean SQUAL (white paper).
Maximum_Pixel Access: Read
Field
Address: 0x45 Reset Value: 0x00
Data Type: number. USAGE: Maximum Pixel value current frame. Minimum value maximum value maximum pixel value vary from frame frame. Shown below graph sequentially acquired maximum pixel values, while sensor moved slowly over white paper.
Pixel White Paper
pixel
Minimum_Pixel Access: Read
Field
Address: 0x46 Reset Value: 0x3f
Data Type: number. USAGE: Minimum Pixel value current frame. Minimum value maximum value minimum pixel value vary from frame frame.
Pixel White Paper
pixel
Pixel_Sum Access: Read
Field
Address: 0x47 Reset Value: 0x00
Data Type: Upper bits 15-bit unsigned integer. USAGE: This register used find average pixel value. reports upper bits 15-bit unsigned integer, which sums pixels current frame. described full divided 128. formula calculate average pixel value below: Average Pixel Register Value Pixel_Sum 0.395 maximum register value truncated integer). minimum pixel value vary from frame frame.
Pixel Data Access: Read/Write
Field Data_Valid
Address: 0x48 Reset Value: 0x00
Data Type: status bits, pixel data. USAGE: Digital Pixel data. Minimum value maximum value writes this register resets pixel hardware that next read from Pixel Data register will read pixel StartOfFrame will set. Subsequent reads will auto increment pixel number.
dump complete image, forced awake mode, write anything this register, then read times where DataValid set. 325th read, StartOfFrame will indicating that have completed frame pixels starting back pixel takes least frames complete image only read pixel frame. pixel hardware armed with read write Pixel Data register will output pixel data from next available frame. were write Pixel Data register, wait seconds then read Pixel Data register; reported pixel data from seconds ago.
Field Name
Description
Start Frame start frame Current pixel number start frame There valid data frame grabber pixel data
Data_Valid
Pixel (sensor facing down, looking through sensor surface) Last Pixel
First Pixel
Pixel Dump Pictures following images output Pixel Data command. data ranges from complete black, complete white. internal circuit adjusts shutter value keep brightest feature (max pixel) 50's.
White Paper
Manila Folder
Burl Formica
USAF Test Chart
Shutter_Upper Access: Read
Address: 0x49 Reset Value: 0x01
Field
Shutter_Lower Access: Read
Address: 0x4A Reset Value: 0x00
Field
Data Type: Sixteen word. USAGE: Units clock cycles; default value 0x0100HEX. Read Shutter_Upper first, then Shutter_Lower. They should read consecutively. sensor adjusts shutter keep average maximum pixel values within normal operating ranges. shutter value vary with every frame. Each time shutter changes, changes ±1/16 current value.
1.50
NORMALIZED SHUTTER VALUE (Counts)
1.25 1.00 0.75 0.50 0.25 -1.0
-0.6
-0.2
DISTANCE FROM NOMINAL FOCUS (mm)
Figure Typical Mean Shutter (white paper).
Note: This graph obtained getting multiple readings over different heights.
maximum value shutter dependent upon clock frequency. formula Frames/second
3000 1512
maximum shutter value shutter value clock freq 3476 Frame Rate
clock frequency MHz, following table shows maximum shutter value. clock cycle 41.67 nsec. Lower
Shutter Decimal
4524 12397 61564 0x11AC 0x306D 0xF07C
Shutter Upper
Frame_Period Access: Read/Write
Address: 0x4b Reset Value: 0xc2
Field
Data Type: Eight complement number that represents upper bits counter. USAGE: frame period counter counts until overflows. Units clock cycles. formula
Clock Rate Counts (decimal) Counts (hex) Counts (2's complement hex) Frame Rate Frame Rate (frames/sec)
1512 3000
Clocks/Frame Decimal
65024 15872 8000
Clocks/Frame (2's complement hex)
Maximum Frame Time Nominal Frame Time
Note: optimize tracking performance dark surfaces, recommended that adaptive frame rate based shutter value implemented frame rates greater than 1500. Changing frame rate results changes maximum speed, acceleration limits, dark surface performance.
Ordering Information Specify part number follows: ADNS-2620 8-pin staggered dual inline package (DIP), tube.
product information complete list distributors, please site:
www.avagotech.com
Avago, Avago Technologies, logo trademarks Avago Technologies, Limited United States other countries. Data subject change. Copyright 2006 Avago Technologies, Limited. rights reserved. Obsoletes 5988-9773EN 5989-3098EN August 2006
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