Optical Mouse Sensor ADNS-2051 cost optical sensor used implement
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ADNS-2051
Optical Mouse Sensor
ADNS-2051 cost optical sensor used implement non-mechanical tracking engine computer mice. based optical navigation technology, which measures changes position optically acquiring sequential surface images (frames) mathematically determining direction magnitude movement. sensor housed 16-pin staggered dual inline package (DIP) that designed with HDNS2100 Lens HDNS-2200 Clip HLMP-ED80XXXXX (639 illuminator source). There moving parts, precision optical alignment required, facilitating high volume assembly. output format channel quadrature direction) which emulates encoder photo-transistors. current information also available registers accessed serial port. Default resolution specified counts inch (cpi), with rates motion inches second (ips). Resolution also programmed cpi. part programmed wire serial port, through registers.
Features
Precise optical navigation technology mechanical moving parts Complete motion sensor Serial interface and/or quadrature interface Smooth surface navigation Programmable frame speed 2300 frames (fps) Accurate motion resolution High reliability High speed motion detector precision optical alignment Wave solderable Single volt power supply Shutdown suspend mode operation Power conservation mode during times movement chip drive with regulated current Serial port registers Programming Data transfer 16-pin staggered dual inline package (DIP)
Theory Operation
ADNS-2051 based Optical Navigation Technology. contains Image Acquisition System (IAS), Digital Signal Processor (DSP), two-channel quadrature output, wire serial port. acquires microscopic surface images lens illumination system provided HDNS2100, 2200, HLMP-ED80-XXXXX LED. These images processed determine direction distance motion. generates relative displacement values that converted into channel quadrature signals.
Applications
Mice desktop PCs, workstations, portable Trackballs Integrated input devices
Outline Drawing ADNS-2051 Optical Mouse Sensor Pinout
SCLK XY_LED REFA REFB OSC_IN OSC_OUT R_BIN SDIO Description Serial port clock (input) quadrature output quadrature output quadrature output quadrature output control Internal reference Internal reference Oscillator input System ground Oscillator output System ground volt power supply current resistor Power down pin, active high Serial data (input output)
Figure view.
REFA REFB OSC_IN XY_LED OSC_OUT SCLK SDIO R_BIN
A2051 XYYWWZ
A2051 XYYWWZ
12.85 SHOULDER) (0.506) 22.30 (0.878) 0.5° 9.10 (0.358) 0.01 (0.000)
0.99 (0.039)
3.18 (0.125)
2.98 (0.117) 5.16 (0.203) 0.50 CHAMFER 0.25 (0.010) 13.57 0.45 LEAD TIP) (0.534 0.018)
LEAD WIDTH 0.50 (0.020) 0.25 (0.010)
1.26 LEAD OFFSET (0.050) 2.54 LEAD PITCH (0.100)
6.18 (0.243)
GATE LOCATION SURFACE RECESSED 4.55 (0.179)
6.03 (0.237)
PROTECTIVE KAPTON TAPE 5.00
(MEASURED BASE) 5.60 0.03 (0.220 0.001) 1.85 0.03 (0.073 0.001)
GROOVE 7.28 0.03 (0.287 0.001)
0.06 (0.002)
0.80 0.03 CLEAR OPTICAL PATH 13.38 (0.527)
*1.5° DRAFT SECTION
1.43 0.03 (0.056 0.001)
2.80 (0.110)
NOTES: DIMENSIONS MILLIMETERS (INCHES). DIMENSIONAL TOLERANCE: COPLANARITY LEADS: LEAD PITCH TOLERANCE: 0.15 CUMULATIVE PITCH TOLERANCE: 0.15 ANGULAR TOLERANCE: DEGREES. MAXIMUM FLASH CHAMFER DEGREES TAPER SIDE LEAD. THESE DIMENSIONS REFERENCES ONLY SHOULD USED MECHANICALLY REFERENCE SENSOR.
Figure Package outline drawing.
Overview Optical Mouse Sensor Assembly Assembly Drawing ADNS-2051 Figures shown with HDNS-2100, HDNS-2200, HLMP-ED80-XXXXX. Avago Technologies provides IGES file drawing describing base plate molding features lens alignment. components interlock they mounted onto defined features base plate. ADNS-2051 sensor designed mounting through hole PCB, looking down. There aperture stop features package that align lens (see Figure HDNS-2100 lens provides optics imaging surface well illumination surface optimum angle. Features lens align sensor, base plate, clip with LED. lens also large round flange provide long creepage path events that occur opening base plate (see Figure HDNS-2200 clip holds relation lens. must inserted into clip LED's leads formed prior loading PCB. clip interlocks sensor lens, through lens alignment features base plate. HLMP-ED80-XXXXX recommended illumination. used with table, sufficient illumination guaranteed.
12.60 (0.498) 11.38 (0.448) 1.27 (0.050) 2.32 (0.091)
40.53 (1.596) 39.39 (1.551) 30.32 (1.194)
3.50 (1.38)
5.10 (0.201)
13.88 (0.546)
REF. 1.28 (0.050) CLEAR ZONE REF. 0.80 RECOMMENDED PLACES) (0.031) 7.50 (0.295) 1.22 (0.048)
DIMENSIONS MILLIMETERS (INCHES)
Figure Recommended mechanical cutouts spacing (top view).
VIEW
44.29 (1.744)
19.10 (0.752)
BASE PLATE LENS RING
SIDE VIEW
PLASTIC SPRING CLIP
14.58 (0.574)
13.82 (0.544)
10.58 (0.417)
7.45 (0.293)
SENSOR
BASE PLATE ALIGNMENT POST
DIMENSIONS MILLIMETERS (INCHES).
Figure assembly drawing ADNS-2051 (top side view).
HDNS-2200 (CLIP)
HLMP-ED80-XXXXX (LED) ADNS-2051 (SENSOR)
CUSTOMER SUPPLIED
HDNS-2100 (LENS)
CUSTOMER SUPPLIED BASE PLATE WITH RECOMMENDED ALIGNMENT FEATURES IGES DRAWING
Figure Exploded view drawing.
Assembly Considerations Insert sensor other electrical components into PCB. Bend leads then insert into assembly clip until snap feature locks base. Insert LED/clip assembly into PCB. Wave Solder entire assembly no-wash solder process utilizing solder fixture. solder fixture needed protect sensor during solder process. fixture should designed expose sensor leads solder while shielding optical aperture from direct solder contact. solder fixture also used
reference height sensor during wave soldering (Note: remove kapton tape during wave soldering). Place lens onto base plate. Remove protective kapton tape from optical aperture sensor. Care must taken keep contaminants from entering aperture. recommended place facing during entire mouse assembly process. should held vertically during kapton removal process.
Insert assembly over lens onto base plate aligning post retain assembly. sensor aperture ring should self-align lens. optical position reference base plate lens. Note that motion button presses must minimized maintain optical alignment. Install mouse case. There MUST feature case press down onto clip ensure components interlocked correct vertical height.
SCLK SERIAL PORT SDIO SERIAL PORT OSCILLATOR
OSC_IN RESONATOR OSC_OUT REFA
QUADRATURE OUTPUT
QUADRATURE OUTPUTS R_BIN XY_LED
VOLTAGE REGULATOR POWER CONTROL
POWER RESET
REFB
VOLTAGE REFERENCE
IMAGE PROCESSOR
DRIVE
VOLT POWER
Figure Block diagram ADNS-2051 optical mouse sensor.
Design Considerations Improving Performance flange lens been designed increase creepage clearance distance electrostatic discharge. table right shows typical values assuming base plate construction Avago supplied IGES file HDNS-2100 lens flange.
Typical Distance Creepage Clearance
Millimeters 16.0
therefore, cyanoacrylatebased adhesives other adhesives that damage lens should used. trimmed lens, HDNS2100#001, recommended corded applications spec requirement.
improved performance, lens flange sealed (i.e. glued) base plate. Note that lens material polycarbonate
LENS/LIGHT PIPE
BASE PLATE
SURFACE
Figure assembly.
;;;;;;; ;;;;; ;;;;; ;;;;;;; ;;;; ;;;;; ;;;;
SENSOR CLIP
Recommended Typical Application using SDIO Pins
D1.3 SHLD
INTERNAL IMAGE SENSOR
HDNS-2100 LENS
HLMP-ED80
SURFACE XY_LED CERAMIC RESONATOR REFB R_BIN VALUE 15.0 15.0 15.0 15.0 15.0 15.0 18.0 15.0 22.0 15.0 27.0 15.0 33.0 15.0 37.0 MURATA CSALS18M0X53-B0 FCR18.0M2G
CYPRESS CY7C63723A-PC
VREG
P0.4 P0.5 P0.6 P0.7 P0.3 P0.2 BUTTONS
SDIO
OSC_IN
ADNS 2051
OSC_OUT
P1.0 P1.1
REFA SCLK
Z-WHEEL ENCODER
P0.0
P0.1
XTALOUT XTALIN
Figure Application using SDIO pins.
Notes Bypass Capacitors: Caps pins MUST have trace lengths LESS than caps must ceramic. Caps should have less than self inductance Caps should have less than Surface mount parts recommended.
Regulatory Requirements Passes worldwide analogous emission limits when assembled into mouse with unshielded cable following Avago recommendations. Passes EN61000-4-4/IEC801-4 tests when assembled into mouse with unshielded cable following Avago recommendations. flammability level UL94 V-0. Provides sufficient creepage/clearance distance avoid
discharge when assembled into mouse according usage instructions above. safety consideration, please refer technical report available site, http://www.Avago.com 15.0 resistor determined absolute maximum rating HLMP-ED80-XXXXX. other resistor values brighter bins will guarantee good signals with reduced power.
Alternative Application using Quadrature Output Pins
CEXT
INTERNAL IMAGE SENSOR
HDNS-2100 LENS
HLMP-ED80-XXXXX
SURFACE XY_LED CERAMIC RESONATOR KBR-18-00-MSA MURATA CSALS18M0X55-B0
0.33 SHLD
CYPRESS CY7C63001A-PC
P0.1 P0.0 P0.2 P0.3 P1.1 XTALOUT P1.2 P0.5 P0.4 P1.3 P1.0
OSC_IN
ADNS-2051
OSC_OUT REFA
XTALIN
SCLK REFB R_BIN
SDIO
VALUE 15.0 15.0 15.0 15.0 15.0 15.0 18.0 15.0 22.0 15.0 27.0 15.0 33.0 15.0 37.0
P0.6 P0.7
BUTTONS
PANASONIC SERIES ENCODER Z-WHEEL
RESISTOR CONNECTION ALTERNATIVE RESISTOR CONNECTION
REGULATOR LP2950AC Z-3.3
Figure Application using quadrature output pins.
Notes Bypass Capacitors: Caps pins MUST have trace lengths LESS than caps must ceramic. Caps should have less than self inductance Caps should have less than Surface mount parts recommended. SDIO SCLK pins should grounded used. Absolute Maximum Ratings Parameter Storage Temperature Operating Temperature Lead Solder Temperature Supply Voltage Input Voltage Input Voltage Symbol Min. Max. Units Notes
seconds, below seating plane. pins, human body model Method 3015 SDIO, SCLK, XY_LED, R_BIN OSC_IN, OSC_OUT, REF_A
-0.5
-0.5 -0.5
Recommended Operating Conditions Parameter Operating Temperature Power Supply Voltage Symbol Min. 4.25 Typ. Max. Units volts Notes Register values retained voltage transients below 4.25 greater than Peak peak within 0-100 MHz. ceramic resonator.
Power Supply Rise Time Supply Noise Clock Frequency Serial Port Clock Frequency Resonator Impendance Distance from Lens Reference Plane Surface Speed Acceleration Light Level onto SDIO Read Hold Time SDIO Serial Write-Write Time SDIO Serial Write-Read Time SDIO Serial Read-Write Time SDIO Serial Read-Read Time Data Delay after
fCLK SCLK XRES IRRINC tHOLD tSWW tSWR tSRW tSRR tCOMPUTE 17.4 18.0
18.7 fCLK/4 0.15 25,000 30,000
in/sec mW/m2
Results ±0.2 DOF. (See Figure 10.) frame rate 1500/second. frame rate 1500/second. Hold time valid data. (Refer Figure 28.) Time between write commands. (Refer Figure 31.) Time between write read operation. (Refer Figure 32.) Time between read write operation. (Refer Figure 33.) Time between read commands. (Refer Figure 33.) After tCOMPUTE, registers contain data from first image after Note that additional frames (shutter) stabilization required mouse movement occurred while high. (Refer Figure 12.) Data valid time before rising SCLK. (Refer Figure 26.) Pulse width initiate power down cycle 1500 fps. (Refer Figure Figure 14.)
SDIO Write Setup Time Pulse Width power down chip) Pulse Width reset serial port)
tSETUP tPDW
tPDR
Frame Rate Resistor
1500
Pulse width reset serial port 1500 (but also initiate power down cycle. Normal recovery sequence followed. (Refer Figure 15.) frames/s Frame_Period register section. Refer Figure
ADNS-2051
HDNS-2100
OBJECT SURFACE
Figure Distance from lens reference plane surface.
Electrical Specifications Electrical Characteristics over recommended operating conditions. Typical values 25°C, 1500 fps, MHz. Parameter Power Down Symbol Min. Typ. Max. Units Notes From Time uncertainty firmware delay. (Refer Figure 12.) From valid quad signals µsec frames. (Refer Figure 12.) From valid quad signals µsec frames (the rise time between 90%) (the fall time between 90%) (the rise time between 90%) (the fall time between 90%) With HLMP-ED80-XXXXX (the rise time between 90%) With HLMP-ED80-XXXXX (the fall time between 90%) Serial port will reset current transaction complete within tSPTT. (Refer Figure 36.) Max. supply current during ramp from with rise time. Does include charging current bypass capacitors.
Power from
tPUPD
Power from
Rise Fall Times:
SDIO
ILED
Serial Port Transaction Timer
tSPTT
Transient Supply Current
IDDT
Electrical Specifications Electrical Characteristics over recommended operating conditions. Typical values 25°C, MHz. Parameter Supply Current (mouse moving) Peak Supply Current (mouse moving) Supply Current (mouse moving) Supply Current (power down) SCLK, SDIO, Input Voltage Input High Voltage Output Voltage Output High Voltage Output Voltage (XA, Output High Voltage (XA, Output Voltage (XY_LED) Current Current (fault mode) REF_A (normal mode) REF_A (power down mode) Symbol Min. Typ. Max. Units Notes load SCLK, SDIO. Excluding current. load SCLK, SDIO. Excluding current. load SCLK, SDIO. Excluding current. high; SCLK, SDIO VDD; 4.25 5.25
PEAK
IDDPD
ILED ILED VREFA VREFA Typ-15% 630/R1
(SDIO only) (SDIO only) Refer Figure Refer Figure table below. GND, low. GND, high.
Typical Current Table Value current (typical)
NORMALIZED ILED
Figure Typical characteristic ADNS-2051 XY_LED pin.
Timing
FRAMES tpupd tCOMPUTE (SEE FIGURE
Figure timing normal mode.
SCLK
tPDW
REGISTER READ OPERATION tCOMPUTE
(POWER DOWN)
Figure timing sleep mode.
Figure minimum pulse width.
OSCILLATOR START CURRENT RESET COUNT INITIALIZATION 2410 ACQUISITION
SCLK OPTIONAL TRANSACTIONS WITH IMAGE DATA tCOMPUTE TRANSACTIONS WITH IMAGE DATA DEFAULT FRAME RATE
Figure Detail falling edge timing.
Quadrature Mode Timing output waveforms emulate output from encoders. With resolution cpi, from five quadrature states exist within frame time. minimum state time resolution
cpi, then quadrature states exist within frame time. motion within frame greater than these values, extra motion will reported next frame. following diagrams (see Figures show timing
positive motion, right positive motion, power down occurs during transfer, transfer will resume after de-asserted. timing that quadrature state will increased length time.
MOTION RIGHT MOTION XA/YA FIVE MORE XB/YB
XA/YA FOUR XB/YB
XA/YA THREE XB/YB
XA/YA XB/YB
XA/YA XB/YB
667µs 1500 FRAMES/SECOND
FRAME
Figure Quadrature states frame (400 mode).
MOTION RIGHT MOTION
XA/YA MORE XB/YB 66.7 66.7 66.7 66.7 66.7 66.7 66.7 66.7 66.7 66.7
XA/YA NINE XB/YB 66.7 66.7 66.7 66.7 66.7 66.7 66.7 66.7
XA/YA EIGHT XB/YB 66.7 66.7 66.7 66.7 66.7 66.7 66.7
XA/YA SEVEN XB/YB 66.7 66.7 66.7 66.7 66.7 66.7
XA/YA XB/YB 66.7 66.7 66.7 66.7 66.7
667µs 1500 FRAMES/SECOND
FRAME
Figure Quadrature states frame (800 mode).
MOTION RIGHT MOTION XA/YA FIVE XB/YB 66.7 66.7 66.7 66.7
XA/YA FOUR XB/YB 66.7 66.7 66.7
XA/YA THREE XB/YB 66.7 66.7
XA/YA XB/YB 66.7
XA/YA XB/YB
667µs 1500 FRAMES/SECOND
FRAME
Figure Quadrature states frame (800 mode).
Quadrature State Machine following state machine shows states quadrature pins. things note that while asserted, state machine halted. Once de-asserted, state machine picks from where left off. State entered after power reset.
STATE
STATE
OUTPUT
STATE
STATE STATE
Figure Quadrature state machine.
Quadrature Output Waveform channel quadrature outputs volt CMOS outputs. count used generate signals, count used signals.
LEFT MOTION (-DIRECTION) MOTION COUNT
DOWN MOTION DIRECTION) MOTION COUNT
RIGHT MOTION DIRECTION) MOTION COUNT
MOTION DIRECTION) MOTION COUNT
Figure Quadrature output waveform.
Typical Performance Characteristics Performance characteristics over recommended operating conditions. Typical values 25°C, MHz. Parameter Path Error (Deviation) Symbol PERROR Min. Typ. Max. Units Notes Path Error (Deviation) error from ideal cursor path. expressed percentage total travel measured over standard surfaces.
following graphs (Figures typical performance ADNS-2051 sensor, assembled shown assembly drawing with HDNS-2100 Lens/Prism, HDNS-2200 clip, HLMP-ED80-XXXXX (page Figure
TYPICAL RESOLUTION HEIGHT COUNTS INCH
RELATIVE RESPONSIVITY 1000
RECOMMENDED OPERATING REGION WHITE PAPER MANILA FOLDER BURL FORMICA DARK WALNUT BLACK COPY
HEIGHT (2.4 NOMINAL FOCUS)
WAVELENGTH (nm)
Figure Typical resolution (comparative surfaces).[2,3]
Figure Wavelength responsitivity.[1]
TYPICAL RESOLUTION HEIGHT DIFFERENT CURRENT LEVELS [BRIGHTNESS] (MANILA FOLDER)
TYPICAL RESOLUTION HEIGHT DIFFERENT CURRENT LEVELS [BRIGHTNESS] (BLACK COPY)
COUNTS INCH
COUNTS INCH
RECOMMENDED OPERATING REGION
RECOMMENDED OPERATING REGION
100%
100%
HEIGHT (2.4 NOMINAL FOCUS)
HEIGHT (2.4 NOMINAL FOCUS)
Figure Typical resolution (manila folder variation).[2,3]
Figure Typical resolution (black copy variation).[2,3]
Note: ADNS-2051 designed optimal performance when used with HLMP-ED80-XXXXX (red nm). with other colors (i.e., blue, green), please consult factory. When using alternate LEDs, there also performance degradation additional safety considerations. Distance from Lens Reference plane Surface. Depth Field.
Synchronous Serial Port synchronous serial port used read parameters ADNS-2051, used read motion information instead quadrature data pins. port wire, half duplex port. host micro-controller always initiates communication; ADNS-2051 never initiates data transfers.
SCLK: serial port clock. always generated master (the microcontroller). SDIO: data line. third line sometimes involved. (Power Down) usually used place ADNS-2051 power mode meet suspend specification. also used force re-synchronization between micro-controller ADNS-2051 case error.
Write Operation Write operations, where data going from micro-controller ADNS-2051, always initiated micro-controller consists bytes. first byte contains address (seven bits) indicate data direction. second byte contains data. transfer synchronized SCLK. micro-controller changes SDIO falling edges SCLK. ADNS-2051 reads SDIO rising edges SCLK.
SCLK CYCLE SCLK
SDIO
DON'T CARE
SDIO DRIVEN MICRO-CONTROLLER
Figure Write operation.
SCLK
SDIO MIN. tsetup MIN.
Figure SDIO setup hold times SCLK pulse width.
Read Operation read operation, which means that data going from ADNS-2051 microcontroller, always initiated micro-controller consists bytes. first byte contains address, written micro-controller, indicate data
direction. second byte contains data driven ADNS-2051. transfer synchronized SCLK. SDIO changed falling edges SCLK read every rising edge SCLK. micro-controller must high state after last address data bit. ADNS-2051 will high state after
last data (see detail Figure 28). other thing note during read operation that SCLK will need delayed after last address data ensure that ADNS-2051 least prepare requested data. This shown timing diagrams below.
SCLK CYCLE SCLK SDIO
SDIO DRIVEN MICRO-CONTROLLER DETAIL
SDIO DRIVEN ADNS-2051 DETAIL
Figure Read operation.
MAX. DETAIL tHOLD MIN. SCLK MICROCONTROLLER ADNS-2051 SDIO HANDOFF SDIO MIN. MIN. MIN. Hi-Z MIN. MAX.
Figure Microcontroller ADNS-2051 SDIO handoff.
DETAIL
MIN. SCLK
ADNS-2051 MICROCONTROLLER SDIO HANDOFF SDIO
MAX. NEXT ADDRESS
RELEASED 2051
DRIVEN MICRO
Figure ADNS-2051 microcontroller SDIO handoff.
Note: high state SCLK minimum data hold time ADNS-2051. Since falling edge SCLK actually start next read write command, ADNS-2051 will hold state SDIO line until falling edge SCLK. both write read operations, SCLK driven micro-controller. Serial port communications allowed while (power down) high. "Error Detection Recovery" regarding re-synchronizing
Forcing SDIO Line Hi-Z State There times when SDIO line from ADNS-2051 should Hi-Z state. microprocessor completed write ADNS-2051, SDIO line Hi-Z, since SDIO still configured input. However, last operation from microprocessor read, ADNS-2051 will hold state SDIO until falling edge SCLK.
place SDIO into Hi-Z state, raise (min). stay high, with ADNS-2051 shutdown state, lowered, returning ADNS-2051 normal operation. SDIO line will Hi-Z state.
SDIO
tSWW >100 ADDRESS
Hi-Z
Figure SDIO Hi-Z state timing.
Required timing between Read Write Commands (tsxx) There minimum timing requirements between read write commands serial port. rising edge SCLK last data second write command occurs before microsecond required delay, then first write command complete correctly.
SCLK ADDRESS DATA DATA
WRITE OPERATION
WRITE OPERATION
Figure Timing between write commands.
tSWR >100
rising edge SCLK last address read command occurs before microsecond required delay, then write command complete correctly.
SCLK ADDRESS DATA ADDRESS
WRITE OPERATION
NEXT READ OPERATION
Figure Timing between write read commands.
falling edge SCLK first address either read write command must least after last SCLK rising edge last data previous read operation.
tHOLD >100
tSRW, tSRR >120
SCLK ADDRESS READ OPERATION DATA ADDRESS
NEXT READ WRITE OPERATION
Figure Timing between read either write subsequent read commands.
SCLK DATA
Figure Timing between SCLK rising edge.
Error Detection Recovery ADNS-2051 micro-controller might synchronization events, power supply droops micro-controller firmware flaws. such case, micro-controller should raise ADNS-2051 will reset serial port will reset registers prepared beginning transmission. ADNS-2051 transaction timer serial port. sixteenth SCLK rising edge spaced more than approximately seconds from first SCLK edge current transaction, serial port will reset. Invalid addresses: Writing invalid address will have effect. Reading from invalid address will return zeros. Collision detection SDIO only time that ADNS-2051 drives SDIO line during READ operation. avoid data collisions, microcontroller should relinquish SDIO before falling edge SCLK after last
address bit. ADNS-2051 begins drive SDIO after next rising edge SCLK. ADNS-2051 relinquishes SDIO within falling SCLK edge after last data bit. microcontroller begin driving SDIO time after that. order maintain power consumption normal operation when pulled high, micro-controller should leave SDIO floating until next transmission (although that will cause communication difficulties). case synchronization failure, both ADNS-2051 micro-controller drive SDIO. ADNS-2051 withstand short circuit current will withstand infinite duration short circuit conditions. Termination transmission micro-controller sometimes required (for example, suspend interrupt during read operation). accomplish this micro-controller should raise ADNS-2051 will write register will reset serial port (but
nothing else) prepared beginning future transmissions after goes low. micro-controller verify success write operations issuing read command same address comparing written data read data. micro-controller verify synchronization serial port periodically reading product register.
Notes Power Serial Port sequence which VDD, SCLK, SDIO during powerup affect operation serial port. diagram below shows what happen shortly after powerup when microprocessor tries read data from serial port. This diagram shows rising valid levels, some point microcontroller starts program, sets SCLK SDIO lines outputs, sets them high. then waits ensure that ADNS-2051 powered ready communicate. microprocessor then tries read from location 0x00, Product_ID,
Figure Power serial port watchdog timer sequence.
;;;;; ;;;;;
SCLK ADDRESS 0x00 DATA 0x02 SDIO PROBLEM AREA
expecting value 0x02. receives this value, then knows that communication ADNS-2051 operational. problem occurs ADNS-2051 powers before microprocessor sets SCLK SDIO lines outputs high. ADNS-2051 sees raising SCLK valid rising edge, clocks state SDIO first address (sets either read write depending upon state). case SDIO low, then read operation started. When microprocessor begins actually send address, ADNS-2051 already first address. When seventh sent micro, ADNS-2051 valid address, drives SDIO line high within (see detail Figure Figure 28). This results fight SDIO. Since address wrong, data sent back will incorrect. case SDIO high, write operation started. address data synchronization, wrong data will written wrong address. Solutions There different ways solve problem, waiting serial port watchdog timer time out, using line reset serial port.
SCLK SDIO
Serial Port Watchdog Timer Timeout
tSPTT
ADDRESS 0x00
DATA 0x02
Figure Power serial port watchdog timer sequence.
microprocessor waits least tSPTT from valid, will ensure that ADNS-2051 powered watchdog timer timed out. This assumes that microprocessor ADNS-2051 share same power supply. not, then microprocessor must wait tSPTT from ADNS-2051 valid. Then when SCLK toggles address, ADNS-2051 will sync with microprocessor. Sync
SCLK SDIO
ADDRESS 0x00
DATA 0x02
Figure Power serial port sync sequence.
line used resync serial port. microprocessor waits from valid, then outputs valid pulse (see Figure 15), then serial port will ready data.
Resync Note microprocessor ADNS-2051 sync, then data either written read from registers will incorrect. easy solve this output pulse resync parts after incorrect read.
communication code Cypress CY7C63000 CY7C63001 (Please consult factory CY7C63722 CY7C63723 codes.)
Note: This programming sequence covered Avago's product warranty. only recommended example when using mentioned Cypress microcontrollers. latest updates Cypress microcontrollers, please contact Cypress email: usbapps@cypress.com call (858) 613-7929 (US).
following code used implement data communications. schematic Figure
Notes: CY7C63001 20pin package ADNS-2051 SDIO line connected pin5 (P1.0) connected (P1.1) SCLK line connected pin15 (P1.3)
port Port1_Data: Port1_Interrupt: Port1_Pullup:
GPIO data port Interrupt enable port Pullup resistor control port
Port definitions SDIO: SCLK: Pt1_Current: GPIO Isink registers Port1_Isink: Port1_Isink0: Port1_Isink1: Port1_Isink3: data memory variables spi_addr: spi_data: bit_counter: port1_wrote:
port1 current setting
address data what
writes writes counter wrote last
initialize Port Pt1_Current iowr Port1_Isink0 iowr Port1_Isink1 iowr Port1_Isink3 iowr Port1_Pullup ~(PD|SDIO) [port1_wrote], [port1_wrote] iowr Port1_Data iowr Port1_Interrupt select setting isink current Port bit[0] isink current Port bit[1] isink current Port bit[3]
enable Port [7:0] pullups
turn ADNS-2051
low, SCLK, SDIO
disable port interrupts
There possible instructionsbefore assumed that These instructions
problems with port microcontroller starts executing ADNS-2051 sensor powered page details. power microcontroller next instructions executed. will reset port sensor.
Resync_sensor:
A,~(SCLK|SDIO|PD) SCLK, SDIO lines [port1_wrote], [port1_wrote]
iowr Port1_Data power sensor needs more time stabilize, insert delay here call call call call call call delay700us delay700us delay700us delay700us delay700us delay700us wait about milliseconds sensor oscillator stabilize
(SCLK|SDIO|PD [port1_wrote], [port1_wrote] iowr Port1_Data call delay700us [port1_wrote], [port1_wrote] iowr Port1_Data call call call call call call delay700us delay700us delay700us delay700us delay700us delay700us
SCLK, SDIO lines high this shuts down oscillator resets port
wait reset part line sensor back into normal operation
wait about milliseconds sensor oscillator stabilize
sensor port sync
ReadSPI routine Includes delays long traces cables between ADNS-2051 correct timing SCLK SDIO entry: spi_addr Address register ADNS-2051 spi_data undefined exit spi_addr undefined spi_data register contents from ADNS-2051
ReadSPI: Waitrspi:
[bit_counter],
wait 200us (optional) (about loop)
[bit_counter] Waitrspi read address
A,~80h [spi_addr], call writeaddr
lower address (read)
Waitrspi2:
A,64 [bit_counter],
wait 200us (about loop)(100us minimum required) wait data ready
[bit_counter] Waitrspi2
nextr:
rd1: rdx:
[spi_data], [bit_counter], SDIO [port1_wrote], [port1_wrote] iowr Port1_Data ~SCLK [port1_wrote], [port1_wrote] iowr Port1_Data A,[spi_data] [spi_data], iord Port1_Data SDIO [spi_data], SCLK [port1_wrote], [port1_wrote] iowr Port1_Data [bit_counter] nextr
clear data
write SDIO lower SCLK
wait cable settle ADNS-2051 connected short traces, then number NOPs reduced eliminated
shift next shift next read SDIO
raise SCLK
wait cable settle
WriteSPI routine Includes delays long traces cables between ADNS-2051. correct timing SCLK SDIO entry: spi_addr Address register ADNS-2051 spi_data Data written register exit spi_addr undefined spi_data undefined
WriteSPI: Waitspi:
[bit_counter],
wait 200us (optional) about loop
[bit_counter] Waitspi write address
[spi_addr], call writeaddr wrdata writeaddr: nexta: [bit_counter], ~SCLK [port1_wrote], [port1_wrote] iowr Port1_Data [spi_addr] [spi_addr], addr0 SDIO [port1_wrote], addrx ~SDIO [port1_wrote], [port1_wrote] iowr Port1_Data SCLK [port1_wrote], [port1_wrote] iowr Port1_Data [bit_counter] nexta [bit_counter], ~SCLK [port1_wrote], [port1_wrote] iowr Port1_Data [spi_data] [spi_data], SDIO [port1_wrote], ~SDIO [port1_wrote], [port1_wrote] iowr Port1_Data SCLK
address (write)
bits shift lower SCLK
shift next
addr1:
raise SDIO
addr0: addrx:
lower SDIO
wait cable settle
raise SCLK
ADNS-2051 reads address wait cable settle
wrdata: nextw:
bits data lower SCLK
shift next
wr1:
raise SDIO
wr0: wrx:
lower SDIO
wait cable settle
raise SCLK
[port1_wrote], [port1_wrote] iowr Port1_Data [bit_counter] nextw delay700us: [bit_counter], waitd0: [bit_counter] waitd0
ADNS-2051 reads data wait cable settle
wait 710us reuse bit_counter
Example calling syntax
WriteSPI register 40h, blink mode [spi_addr], [spi_data], call WriteSPI move address into move address into spi_addr move data into move data into spi_data call WriteSPI routine, return, spi_addr spi_data will undefined
ReadSPI Read register 02h, motion register [spi_addr], call ReadSPI move address into move address into spi_addr call ReadSPI, return, data spi_data, spi_addr undefined
Registers ADNS-2051 programmed through registers, serial port, configuration motion data read from these registers. Address 0x00 0x01 0x02 0x03 0x04 0x05 Register Product_ID Revision_ID Motion Delta_X Delta_Y SQUAL Address 0x06 0x07 0x08 0x09 0x0a 0x0b Register Average_Pixel Maximum_Pixel Reserved Reserved Configuration_bits Reserved Address 0x0c 0x0d 0x0e 0x0f 0x10 0x11 Register Data_Out_Lower Data_Out_Upper Shutter_Lower Shutter_Upper Frame_Period_Lower Frame_Period_Upper
Product_ID Access: Read Field PID7
PID6
PID5
Address: 0x00 Reset Value: 0x02 PID4 PID3 PID2
PID1
PID0
Data Type: Eight number with product identifier. USAGE: value this register does change, used verify that serial communications link
Revision_ID Access: Read
Address: 0x01 Reset Value: 0xNN
RID1
RID0
Field RID7 RID6 RID5 RID4 RID3 RID2 Data Type: Eight number with current revision
USAGE: value between which represent current design revision device.
Motion Access: Read
Reserved
Address: 0x02 Reset Value: 0x00 FAULT OVFY
OVFX
Reserved
Reserved
Field Data Type: field
USAGE: Register 0x02 allows user determine motion occurred since last time read. then user should read registers 0x03 0x04 accumulated motion. also tells motion buffers have overflowed whether fault occurred since last reading. current resolution also shown.
Field Name
Description Motion since last report motion Motion occurred, data ready reading Delta_X Delta_Y registers Reserved future Fault detected when R_BIN high, shorts Ground fault Fault detected Motion overflow buffer overflowed since last report overflow Overflow occurred Motion overflow buffer overflowed since last report overflow Overflow occurred Reserved future Reserved future Resolution counts inch
Reserved FAULT
OVFY
OVFX
Reserved Reserved
Notes Motion: Reading this register freezes Delta_X Delta_Y register values. Read this register before reading Delta_X Delta_Y registers. Delta_X Delta_Y read before motion register read second time, data Delta_X Delta_Y will lost. Avago RECOMMENDS that registers 0x02, 0x03 0x04 read sequentially. Internal buffers accumulate more than eight bits motion either internal buffers overflows, then absolute path data lost, OVFX OVFY set. These bits (OVFX OVFY) cleared once some motion been read from Delta_X Delta_Y registers, buffers full scale. Since more data present buffers, cycle reading Motion, Delta_X Delta_Y registers should repeated until motion (MOT) cleared. Until cleared, either Delta_X Delta_Y registers will read either positive negative full scale. motion register been read long time, take read cycles clear buffers, cpi, cycles. FAULT sticky that cleared reading Motion register. signifies that fault occurred since last time motion register read. Once fault cleared, hardware will drive normally.
Delta_X Access: Read Field
Address: 0x03 Reset Value: 0x00
Data Type: Eight complement number. USAGE: movement counts since last report. Absolute value determined resolution. Reading clears register.
MOTION
-128
-127
+126
+127
DELTA_X
Delta_Y Access: Read Field
Address: 0x04 Reset Value: 0x00
Data Type: Eight complement number. USAGE: movement counts since last report. Absolute value determined resolution. Reading clears register.
MOTION -128 -127 +126 +127
DELTA_Y
Surface_Quality Access: Read
Address: 0x05 Reset Value: 0x00
Field Data Type: Eight number.
USAGE: SQUAL measure number features visible sensor current frame. maximum value 255. Since small changes current frame result changes SQUAL, variations SQUAL when looking surface expected. graph below shows sequentially acquired SQUAL values, while sensor moved slowly over white paper. SQUAL nearly equal zero, there surface below sensor.
SQUAL VALUES (WHITE PAPER)
SQUAL VALUE
NORMALIZED SQUAL COUNTS
focus point important could affect squal value, graph below showing another setup with various z-height. graph clearly shows that squal count dependent focus distance. Note: This graph obtained getting multiple readings over different heights.
-1.0 -0.8 -0.5 -0.3 0.25 0.75
DELTA FROM NOMINAL FOCUS (mm)
Figure Typical mean squal (white paper).
Average_Pixel Access: Read Field
Address: 0x06 Reset Value: 0x00
Data Type: number. USAGE: Average Pixel value current frame. Minimum value maximum average pixel value adjusted every frame. Shown below graph sequentially acquired average pixel values, while sensor moved slowly over white paper.
AVERAGE PIXEL (WHITE PAPER)
AVERAGE PIXEL VALUE
Maximum_Pixel Access: Read Field
Address: 0x07 Reset Value: 0x00
Data Type: number. USAGE: Maximum Pixel value current frame. Minimum value maximum value maximum pixel value adjusted every frame. Shown below graph sequentially acquired maximum pixel values, while sensor moved slowly over white paper.
MAXIMUM PIXEL (WHITE PAPER)
MAXIMUM PIXEL VALUE
Reserved Reserved
Address: 0x08 Address: 0x09
Configuration_bits Access: Read/Write Field RESET Data Type: field
LED_MODE
Address: 0x0a Reset Value: 0x00 Test
PixDump
Reserved
Reserved
Sleep
USAGE: Register 0x0a allows user change configuration sensor. Shown below bits, their default values, optional values.
Field Name RESET
Description Power defaults (bit always reads effect Reset registers bits power default settings (bold entries) Shutter Mode Shutter mode (LED always (even motion sec.) Shutter mode (LED only when electronic shutter open) System Tests (bit always reads tests perform system tests, output Data_Out_Upper Data_Out_Lower registers.
LED_MODE
Test
Dump
Reserved Reserved Sleep
Note: Since part system test test, will overwritten with default values when test done. configuration changes from default needed operation, make changes AFTER system test run. This operation requires substantially more time complete than other register transactions. Resolution counts inch Dump pixel array through Data_Out_Upper Data_Out_Lower, bytes disabled dump pixel array Reserved Reserved Sleep Mode Normal, fall asleep after second movement (1500 frames/s) Always awake
Address: 0x0b
Reserved
Data_Out_Lower Access: Read Field
Address: 0x0c Reset Value: undefined
Data_Out_Upper Access: Read
Address: 0x0d Reset Value: undefined DO12 DO11 DO10
Field DO15 DO14 DO13 Data Type: Sixteen word.
USAGE: Data written these registers from system self test, pixel dump command. data read 0x0d, 0x0d first, then 0x0c.
System test result System test result Pixel Dump command
Data_Out_Upper Pixel Address
Data_Out_Lower Pixel Data (Lower bits)
Note results returned. These values subject change with each device design revision.
Once pixel dump command given, sensor writes address value first pixel into Data_Out_Upper Data_Out_Lower registers. Data_Out_Lower status data. high, data valid. Once low, data that particular read valid should saved. pixel address data will then incremented next frame. Once pixel dump complete, PixDump register 0x0a should zero. obtain accurate image, needs turned changing sleep mode configuration register 0x0a always awake.
Pixel Address (Looking through HDNS-2100 Lens)
LAST PIXEL FIRST PIXEL
X-RAY VIEW MOUSE
POSITIVE
A2051 YYWW
POSITIVE
Figure Directions complete mouse, with HDNS-2100 lens.
Pixel Dump Pictures following images (Figure output pixel dump command. data ranges from zero complete black, complete white. internal circuit adjusts shutter value keep brightest feature (max. pixel) 50s.
White Paper
Manila Folder
Neoprene Mouse (Gray)
USAF Test Chart Group Element line pairs
Figure Pixel dump pictures.
Shutter_Lower Access: Read Field
Address: 0x0e Reset Value: 0x64
Shutter_Upper Access: Read Field
Address: 0x0f Reset Value: 0x00
Data Type: Sixteen word. USAGE: Units clock cycles; default value Read Shutter_Upper first, then Shutter_Lower. They should read consecutively. shutter adjusted keep average maximum pixel values within normal operating ranges. shutter value adjusted value every frame. When shutter adjusts, changes ±1/16 current value. Shown below graph sequentially acquired shutter values, while sensor moved slowly over white paper.
SHUTTER VALUES (WHITE PAPER)
SHUTTER VALUE (CLOCK CYCLES)
focus point important could affect shutter value. graph below shows another setup with various z-height. This graph clearly shows that shutter value dependent focus distance.
TYPICAL SHUTTER (WHITE PAPER)
-1.0 -0.8 -0.5 -0.3 0.25 0.75
NORMALIZED SHUTTER VALUE (COUNTS)
DISTANCE FROM NOMINAL FOCUS (mm)
Figure Typical shutter (white paper).
Note: This graph shows average readings over different heights.
maximum value shutter dependent upon frame rate clock frequency. formula maximum shutter value Max. Shutter Value Clock Frequency -2816 Frame Rate
clock frequency MHz, following table shows maximum shutter value. clock cycle 55.56 nsec. Shutter Frames/second 2300 2000 1500 1000 Decimal 5010 6184 9184 15184 33184 0x1392 0x1828 0x23E0 0x3B50 0x81A0 Shutter Upper Lower Default Max. Shutter
Frame_Period_Lower Access: Read/Write Field
Address: 0x10 Reset Value: 0x20
Frame_Period_Upper Access: Read/Write
Address: 0x11 Reset Value: 0xd1 FP11 FP10
Field FP15 FP14 FP13 FP12 Data Type: Sixteen complement word.
USAGE: frame period counter counts until overflows. Units clock cycles. formula Counts (hex)
clock, here Frame_Period values popular frame rates. Counts Decimal 7826 9000 12000 18000 36000 Frame_Period Upper Lower Default Frame Time Minimum Frame Time
Frames/second 2300* 2000* 1500 1000
0x1E92 0x2328 0x2EE0 0x4650 0x8CA0
Comp 0xE16E 0xDCD8 0xD120 0xB9B0 0x7360
*Note: optimize tracking performance dark surfaces, recommended that adaptive frame rate based shutter value implemented, frame rates greater than 1500. Changing frame rate results changes maximum speed, acceleration limits, dark surface performance. read from registers, read Frame_Period_Upper first followed Frame_Period_Lower. write registers, write Frame_Period_Lower first followed Frame_Period_Upper.
Clock Rate Counts (decimal) Frame Rate
Counts (2`s complement hex)
Register State after Reset (power setting register 0x0a) Address 0x01 0x02 Register Product_ID Revision_ID Motion Value 0x02 0xNN 0x00 Meaning Product (Fixed value) Revision (Fixed value). (For each device design revision.) Motion Fault data overflow data overflow Resolution counts inch motion motion image measure image measure image measure
0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a
Delta_X Delta_Y SQUAL Average_Pixel Maximum_Pixel Reserved Reserved Configuration_bits
0x00 0x00 0x00 0x00 0x00 0x00
Part Reset Shutter Mode System tests Resolution counts inch Pixel Dump disabled Sleep mode enabled data read data read Initial shutter value Initial shutter value Initial frame period value (corresponds 1500 fps) Initial frame period value (corresponds 1500 fps)
0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11
Reserved Data_Out_Lower Data_Out_Upper Shutter_Lower
undefined undefined 0x64
Shutter_Upper 0x00 Frame_Period_Lower 0x20 Frame_Period_Upper 0xd1
Optical Mouse Design References
Application Note AN1179 Safety calculation AN1228
Ordering Information
Specify part number follows: ADNS-2051 Sensor 16-pin staggered DIP, tube. ADNB-2050 Sensor HDNS-2100 round lens bundle kit, 1000 incremental ADNB-2051 Sensor HDNS-2100#001 Round lens bundle kit, 1000 incremental HDNS-2100 Round Optical Mouse Lens HDNS-2100#001 Trimmed Optical Mouse Lens HDNS-2200 Assembly Clip (Black) HDNS-2200#001 Assembly Clip (Clear) HLMP-ED80-XXXXX
product information complete list distributors, please website:
www.avagotech.com
Avago, Avago Technologies, logo trademarks Avago Technologies, Pte. United States other countries. Data subject change. Copyright 2006 Avago Technologies Pte. rights reserved. Obsoletes 5988-4289EN 5988-8477EN 2006
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