2-Wire Serial EEPROMs with Permanent Software Write Protect 128K

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2-Wire Serial EEPROMs with Permanent Software Write Protect 128K

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One-Time Programmable (OTP) Feature Low-Voltage Standard-Voltage Operation
2-Wire Serial EEPROMs with Permanent Software Write Protect
128K (16,384 256K (32,768
Description
AT24CS128/256 provides 131,072/262,144 bits serial electrically erasable programmable read only memory (EEPROM) organized 16,384/32,768 words bits each. device's cascadable feature allows devices share common 2-wire bus. device also features one-time programmable 2048 array, which once enabled, becomes read-only cannot overwritten. enabled, section will function part normal memory array. device optimized many industrial commercial applications where power voltage operation essential. devices available space-saving 8-pin JEDEC PDIP (AT24CS128/256), 8-pin EIAJ (AT24CS128/256), 8-pin JEDEC SOIC (AT24CS128) packages. addition, entire family available 5.0V (4.5V 5.5V), 2.7V (2.7V 5.5V) 1.8V (1.8V 3.6V) versions.
AT24CS128 AT24CS256 Advanced Information
Configurations
Name Function Address Inputs Serial Data Serial Clock Input Write Protect
8-Pin PDIP
8-Pin SOIC
Rev. 1152A-09/98
Absolute Maximum Ratings*
Operating Temperature -55°C +125°C Storage Temperature -65°C +150°C Voltage with Respect Ground .-1.0V +7.0V Maximum Operating Voltage. 6.25V Output Current. *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Block Diagram
Description
SERIAL CLOCK (SCL): input used positive edge clock data into each EEPROM device negative edge clock data each device. SERIAL DATA (SDA): bidirectional serial data transfer. This open-drain driven wire-ORed with number other open-drain open collector devices. DEVICE/PAGE ADDRESSES (A2, A0): pins device address inputs that hardwired left connected hardware compatibility with AT24C32/64. When pins hardwired, many four 128K/256K devices addressed single system (device addressing discussed detail under Device Addressing section). When pins hardwired,
default zero. device address input "don't care" input. WRITE PROTECT (WP): write protect input, when tied GND, allows normal write operations. When tied high VCC, write operations memory inhibited. left unconnected, internally pulled down GND. Switching prior write operation creates software write protect function.
Memory Organization
AT24CS128/256, 128K/256K SERIAL EEPROM: 128K/256K internally organized 256/512 pages 64bytes each. Random word addressing requires 14/15-bit data word address.
AT24CS128/256
AT24CS128/256
Capacitance(1)
Applicable over recommended operating range from 25°C, MHz, +1.8V.
Symbol CI/O Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, SCL) This parameter characterized 100% tested. Units Conditions VI/O
Characteristics
Applicable over recommended operating range from: -40°C +85°C, +1.8V +5.5V, +70°C, +1.8V +5.5V (unless otherwise noted).
Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ISB1 Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Standby Current (1.8V option) Standby Current (2.7V option) Standby Current (5.0V option) Input Leakage Current Output Leakage Current Input Level(1) Input High Level
Test Condition
Units
5.0V 5.0V 1.8V 3.6V 2.7V 5.5V 5.5V VOUT
READ WRITE
ISB2 ISB3 VOL2 VOL1 Note:
0.10 0.05 -0.6
Output Level Output Level
VCC3 3.0V 1.8V
0.15
reference only tested
Characteristics
Applicable over recommended operating range from -40°C +85°C, +1.8V +5.5V, (unless otherwise noted). Test conditions listed Note
1.8-volt Symbol fSCL tLOW tHIGH tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tSU.STO Endurance(1) Notes: Parameter Clock Frequency, Clock Pulse Width Clock Pulse Width High Clock Data Valid Time must free before transmission start(1) Start Hold Time Start Set-up Time Data Hold Time Data Set-up Time Inputs Rise Time Inputs Fall Time
2.7-volt 1000
5.0-volt 1000 Units 0.55 0.25 100K Write Cycles
100K
0.05 0.25 0.25
0.55
0.05 0.25 0.25
0.25 100K
Stop Set-up Time Data Hold Time Write Cycle Time 5.0V, 25°C, Page Mode
This parameter characterized 100% tested. measurement conditions: (connects VCC): 1.3K (2.7V, 5V), (1.8V) Input pulse voltages: 0.3VCC 0.7VCC Input rise fall times: 50ns Input output timing reference voltages: 0.5VCC
Device Operation
CLOCK DATA TRANSITIONS: normally pulled high with external device. Data change only during time periods (refer Data Validity timing diagram). Data changes during high periods will indicate start stop condition defined below. START CONDITION: high-to-low transition with high start condition which must precede other command (refer Start Stop Definition timing diagram). STOP CONDITION: low-to-high transition with high stop condition. After read sequence, stop command will place EEPROM standby power mode (refer Start Stop Definition timing diagram). ACKNOWLEDGE: addresses data words serially transmitted from EEPROM 8-bit words. EEPROM sends zero during ninth clock cycle acknowledge that received each word. STANDBY MODE: AT24CS128/256 features power standby mode which enabled: upon power-up after receipt STOP completion internal operations. MEMORY RESET: After interruption protocol, power loss system reset, 2-wire part reset following these steps: Clock cycles, look high each cycle while high then create start condition high.
AT24CS128/256
AT24CS128/256
Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
WORD
STOP CONDITION
START CONDITION
Note:
write cycle time time from valid stop condition write sequence internal clear/write cycle.
Data Validity
Start Stop Definition
Output Acknowledge
AT24CS128/256
AT24CS128/256
Device Addressing
128K/256K EEPROM requires 8-bit device address word following start condition enable chip read write operation (refer Figure device address word consists mandatory one, zero sequence first five most significant bits shown. This common 2-wire EEPROM devices. 128K/256K uses device address bits allow many four devices same bus. These bits must compare their corresponding hardwired input pins. pins internal proprietary circuit that biases them logic condition pins allowed float. eighth device address read/write operation select bit. read operation initiated this high write operation initiated this low. Upon compare device address, EEPROM will output zero. compare made, device will return standby state. DATA SECURITY: AT24CS128/256 hardware data protection scheme that allows user write protect whole memory when VCC. than data words transmitted EEPROM, data word address will "roll over" previous data will overwritten. address "roll over" during write from last byte current page first byte same page. ACKNOWLEDGE POLLING: Once internally-timed write cycle started EEPROM inputs disabled, acknowledge polling initiated. This involves sending start condition followed device address word. read/write representative operation desired. Only internal write cycle completed will EEPROM respond with zero, allowing read write sequence continue.
Description/Operation
feature provides user with 2048-bit (256 security section, which once programmed enabled, becomes read-only data cannot changed overwritten. section located upper section memory array AT24CS128/256. enabled, section will function part normal memory array. enable section: Inputs must connected: Don't Care, Initiate programming sequence:
START 1010 1100 11xx xxxx xxxx xxxx xxxx xxxx STOP
Write Operations
BYTE WRITE: write operation requires 8-bit data word addresses following device address word acknowledgment. Upon receipt this address, EEPROM will again respond with zero then clock first 8-bit data word. Following receipt 8-bit data word, EEPROM will output zero. addressing device, such microcontroller, then must terminate write sequence with stop condition. this time EEPROM enters internally-timed write cycle, tWR, nonvolatile memory. inputs disabled during this write cycle EEPROM will respond until write complete (refer Figure PAGE WRITE: 128K/256K EEPROM capable 64byte page writes. page write initiated same byte write, microcontroller does send stop condition after first data word clocked Instead, after EEPROM acknowledges receipt first data word, microcontroller transmit more data words. EEPROM will respond with zero after each data word received. microcontroller must terminate page write sequence with stop condition (refer Figure data word address lower bits internally incremented following receipt each data word. higher data word address bits incremented, retaining memory page location. When word address, internally generated, reaches page boundary, following byte placed beginning same page. more
Once enabled, previously written data cannot changed. status section only confirmed initiating programming sequence section verifying read command. write protect (WP) feature utilized with without enabling function.
Read Operations
Read operations initiated same write operations with exception that read/write select device address word one. There three read operations: current address read, random address read sequential read. CURRENT ADDRESS READ: internal data word address counter maintains last address accessed during last read write operation, incremented one. This address stays valid between operations long chip power maintained. address "roll over" during read from last byte last memory page, first byte first page. Once device address with read/write select clocked acknowledged EEPROM, current address data word serially clocked out. microcontroller does respond with input zero does generate following stop condition (refer Figure
RANDOM READ: random read requires "dummy" byte write sequence load data word address. Once device address word data word address clocked acknowledged EEPROM, microcontroller must generate another start condition. microcontroller initiates current address read sending device address with read/write select high. EEPROM acknowledges device address serially clocks data word. microcontroller does respond with zero does generate following stop condition (refer Figure Figure Device Address
SEQUENTIAL READ: Sequential reads initiated either current address read random address read. After microcontroller receives data word, responds with acknowledge. long EEPROM receives acknowledge, will continue increment data word address serially clock sequential data words. When memory address limit reached, data word address will "roll over" sequential read will continue. sequential read operation terminated when microcontroller does respond with zero does generate following stop condition (refer Figure
Figure Byte Write
Figure Page Write
DON'T CARE bit) DON'T CARE 128K)
AT24CS128/256
AT24CS128/256
Figure Current Address Read
Figure Random Read
DON'T CARE bit) DON'T CARE 128K)
Figure Sequential Read
AT24CS128 Ordering Information
(max) (ms) (max) (µA) 3000 (max) (µA) fMAX (kHz) 1000 Ordering Code AT24CS128-10PC AT24CS128N-10SC AT24CS128W-10SC AT24CS128-10PI AT24CS128N-10SI AT24CS128W-10SI AT24CS128-10PC-2.7 AT24CS128N-10SC-2.7 AT24CS128W-10SC-2.7 AT24CS128-10PI-2.7 AT24CS128N-10SI-2.7 AT24CS128W-10SI-2.7 AT24CS128-10PC-1.8 AT24CS128N-10SC-1.8 AT24CS128W-10SC-1.8 AT24CS128-10PI-1.8 AT24CS128N-10SI-1.8 AT24CS128W-10SI-1.8 Package Operation Range Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C)
3000
1000
1500
1500
Package Type Blank -2.7 -1.8 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Options Standard Operation (4.5V 5.5V) Low-Voltage (2.7V 5.5V) Low-Voltage (1.8V 3.6V)
AT24CS128/256
AT24CS128/256
AT24CS256 Ordering Information
(max) (ms) (max) (µA) 3000 3000 1500 1500 (max) (µA) fMAX (kHz) 1000 1000 Ordering Code AT24CS256-10PC AT24CS256W-10SC AT24CS256-10PI AT24CS256W-10SI AT24CS256-10PC-2.7 AT24CS256W-10SC-2.7 AT24CS256-10PI-2.7 AT24CS256W-10SI-2.7 AT24CS256-10PC-1.8 AT24CS256W-10SC-1.8 AT24CS256-10PI-1.8 AT24CS256W-10SI-1.8 Package Operation Range Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C)
Package Type Blank -2.7 -1.8 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Options Standard Operation (4.5V 5.5V) Low-Voltage (2.7V 5.5V) Low-Voltage (1.8V 3.6V)
Packaging Information
8P3, 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions Inches (Millimeters)
JEDEC STANDARD MS-001
8S1, 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions Inches (Millimeters)
.400 (10.16) .355 (9.02) .280 (7.11) .240 (6.10) .037 (.940) .027 (.690)
.020 (.508) .013 (.330)
.157 (3.99) .150 (3.81)
.244 (6.20) .228 (5.79)
.300 (7.62)
.050 (1.27)
.100 (2.54)
.210 (5.33) SEATING PLANE .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14)
.196 (4.98) .189 (4.80)
.015 (.380) .022 (.559) .014 (.356)
.068 (1.73) .053 (1.35)
.010 (.254) .004 (.102)
.325 (8.26) .300 (7.62)
.012 (.305) .008 (.203)
.430 (10.9)
.050 (1.27) .016 (.406)
.010 (.254) .007 (.203)
8S2, 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Dimensions Inches (Millimeters)
.020 (.508) .012 (.305)
.213 (5.41) .205 (5.21)
.330 (8.38) .300 (7.62)
.050 (1.27)
.212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78)
.013 (.330) .004 (.102) .035 (.889) .020 (.508) .010 (.254) .007 (.178)
AT24CS128/256
AT24CS128/256
AT24CS128/256
AT24CS128/256
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1152A-09/98/xM
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2-Wire Serial EEPROMs with Permanent Software Write Protect 128K

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