Translation Existing ASIC Designs only been last years that desig

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Translation Existing ASIC Designs only been last years that desig

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CMOS ASIC
Translation Existing ASIC Designs
only been last years that designers users application specific integrated circuits (ASIC) have been able obtain additional sources these types integrated circuits. introduction design synthesis software companies made task converting from ASIC vendor's library into another's, feasible task even most dense designs. user application specific integrated circuit desires flexibility security offered having multiple sources what often system components, user requires improvement performance offered advanced process technologies, have easy path satisfy their needs. That path Atmel's Design Translation ASIC design flow, shown Figure Design Translation flow highlights major steps that taken converting netlist into Atmel's gate array cells, verifying translation, performing layout realizing desired circuit performance, fabricating testing resulting silicon product. This application note describes types data required from ASIC user process steps followed Atmel successfully translate existing ASIC design, presents results translation efforts. first effort where Atmel device performance required match that original ASIC. second translation where improved performance Atmel's device required. process been proven through successful translation designs from such vendors Logic, NEC, Fujitsu, Oki, into series gate array family.
ASIC Design Translation Application Note
Process
Simply stated, Design Translation process maps cells from original design into cells contained Atmel's cell library. These cells equivalent primitives soft macros which include several primitives. choice Atmel cell will depend upon required performance objective, and, some instances, hard macros created replace soft macros achieve performance goals design. Once mapping complete, process follows Atmel's normal ASIC design flow, including cell placement routing, resimulation using Atmel's "golden" simulator, comparison predicted versus desired performance and, after approval design user, tape prototype fabrication.
Translation Existing ASIC Designs
0074G
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Database Required
ASIC design accomplished variety platforms, with variety software tools some open, some proprietary. Designs completed using generic and/or vendor-specific library cells well. This level flexibility available ASIC designer does hinder translation effort. Most design tools capable providing netlist EDIF (EDIF 2.0.0) format. Other netlist formats which acceptable Atmel listed below: Cadence- Verilog-XL, EDIF 2.0.0 Logic NDLMentor- MIFSynopsys- EDIF Viewlogic- EDIF 2.0.0 addition netlist original design, several other pieces information needed successfully translate design. Also required are: description original design library Functional test vectors, print-on-change format Device specifications Identification critical and/or asynchronous paths "As-routed" delay data from original design make assessment whether desired performance match improvement been achieved, understanding starting point must reached. description original cell library, with functional timing information each cell, also essential definition starting point.
Figure Design Translation Flow
Customer
Database Acceptance
Atmel
Netlist Translation, Simulation Verification
Atmel
Customer
Preliminary Design Review
Atmel
Physical Design
Atmel
Customer
Final Design Review
Atmel
Customer
Prototype Delivery
Atmel
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CMOS ASIC
CMOS ASIC
sample parts original design provided, performance data actual silicon used help establish baseline. functional vector ASCII TSSI, print-onchange format) serves purposes. functional vector set, when converted into tester-specific format used conjunction with sample devices, provides mechanism establishing detailed performance attributes original design. These attributes, such maximum frequency, path timing performance, buffer characteristics name few, provide base cell buffer selection match improve design. Individual performance attributes also used input waveform comparison tool. This tool, using actual data functional test vectors, converted simulator format, permits Atmel designer determine when where timing mismatches occur adjust netlist accordingly. device specification provides information concerning required device pin-out, system loading each pin, desired performance, range operating conditions. Figure Maximum Operating Frequency, 25°C, VDD=5.0V
Performance Matching
first example ASIC translation presents results work performed military application, where interchangeability with original designs required. original design Logic series gate array approximately 5,000 gates. design asynchronous multiple clocks. Samples representing original designs were available outset were characterized supplement specification requirements. data presented direct comparison Logic Atmel silicon. Figure depicting maximum operating frequency constant temperature voltage, shows closely performance matched. Figures depict average performance nine critical paths, low-to-high transitions, both function supply voltage temperature. finally, Figures depict rise fall time bidirectional buffers. performance match extremely close. customer performed extensive tester-based characterization qualification Atmel device insure that pin-for-pin compatible, drop-in
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Figure Atmel Package Test Results Critical Paths, tPLH, +25°C
Figure Atmel Package Test Results Critical Paths, tPLH,
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CMOS ASIC
CMOS ASIC
replacement original Logic part. parts were then assembled onto boards tested again. Atmel parts were interchanged mixed matched boards. complete system evaluation performed tests Atmel parts proved equal superior gate array.
Figure Output Rise Time, Bidirectional Buffer, 25°C, Load,
Figure Output Fall Time, Bidirectional Buffer 25°C, Load,
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Performance Improvement
second example ASIC translation presents results work performed commercial application. This design required approximately 8,000 gates, completely synchronous, operating MHz. customer desired improvement performance MHz. achieve this speed, Atmel compared performance cells those original design, samples were available. This evaluation indicated that percent speed improvement could realized over existing design. Atmel also employed higher drive cells where appropriate further enhance performance. Extensive board level testing, performed customer, confirmed that Atmel implementation exceeded design goal over rated voltage temperature ranges. Atmel's CMOS Gate Array Design Manual provides more detailed information about gate arrays, design methodologies, individual cell timing, should used reference evaluating ASIC performance.
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CMOS ASIC

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