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ATL60 CMOS Gate Array
DESCRIPTION: flip-flop
cell data sheets
Truth Table:
at60Cells
Q(T+1) Q(T)
VDD! VDD!
VDD!
VSS! VDD!
VDD!
VSS! VSS!
VSS! VDD!
VSS!
VSS!
VDD!
VDD!
VSS!
VSS!
($Revision: 1.27
12:12:47 1996
ATL60 CMOS Gate Array
DESCRIPTION: flip-flop
cell data sheets
SITES: Core Ring LOADS: D=2.0 CLK=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.032110 Setup -0.122040
(NomProc,25degC,trf=2ns)
Rise -0.809730 Hold -0.091070 Fall Slope -0.021440 Fall -0.870560
TIMING TABLE
Path -CLK Path Rise Slope -0.027590 Setup -0.331830
(NomProc,25degC,trf=2ns)
Rise -0.546160 Hold -0.021220 Fall Slope -0.016680 Fall -0.558750
Typical Case Path Delays rise fall
Typical Case Path Delays rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:12:47 1996
DFFBCPX ATL60 CMOS Gate Array
cell data sheets
DESCRIPTION: flip-flop with asynchronous clear preset with complementary outputs
at60Cells
Truth Table: Q(T+1) QB(T+1) Q(T) QB(T)
DFFBCPX
VDD! VDD! VDD!
N108
VDD! VDD!
P146
VDD!
N104 N112 VSS! P111 N106
VDD! VSS! VDD! VSS!
VSS!
N147
VDD! VDD! VSS!
P107
N102 N103
VSS! VDD!
P123 N105 N119
P141
N131
VDD! VSS!
N116
P113 N109 P110
VSS!
P114 P115 N117 N118
VDD!
P150 N152
VDD! VSS!
VDD!
VDD!
N100 N101
VSS! VSS!
P129 N125
VSS!
P136
N132
VSS!
VSS!
($Revision: 1.27
12:12:47 1996
DFFBCPX ATL60 CMOS Gate Array
cell data sheets
DESCRIPTION: flip-flop with asynchronous clear preset with complementary outputs
SITES: Core Ring LOADS: D=2.0 CLK=1.0 C=2.0 P=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.032900 0.030530 0.010570 0.026170 0.025430 0.011320 Setup -0.310700
(NomProc,25degC,trf=2ns)
Rise -1.333660 1.300120 1.449440 0.925770 1.090430 1.260550 Hold -0.050340 Fall Slope -0.015780 0.015180 0.000000 0.017720 0.017900 0.000000 Fall -1.558450 1.043630 0.000000 0.689470 0.748080 0.000000
TIMING TABLE
Path -CLK Path Rise Slope -0.026270 0.026370 0.020340 0.026190 0.020720 0.010630 Setup -0.169540
(NomProc,25degC,trf=2ns)
Rise -0.942810 0.902790 0.606210 0.945010 0.726020 0.884530 Hold -0.043830 Fall Slope -0.012500 0.012230 0.014470 0.000000 0.014490 0.000000 Fall -1.098330 0.735050 0.519780 0.000000 0.549400 0.000000
DFFBCPX Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
DFFBCPX Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:12:47 1996
DFFBSRX ATL60 CMOS Gate Array
cell data sheets
DESCRIPTION: flip-flop with asynchronous reset with complemntary outputs
at60Cells
Truth Table: Q(T+1) QB(T+1) Q(T) QB(T)
DFFBSRX
VDD!
VDD!
VSS!
VDD!
VDD!
VDD! VDD!
VSS!
P100
VDD!
VSS!
VSS!
VDD! VDD!
VSS!
VSS! VDD!
VSS! VDD! VDD!
VSS!
VSS! VSS! VDD! VDD!
P116 N113
VSS!
P126
VSS!
N125
VSS!
VSS!
($Revision: 1.27
12:14:08 1996
DFFBSRX ATL60 CMOS Gate Array
cell data sheets
DESCRIPTION: flip-flop with asynchronous reset with complemntary outputs
SITES: Core Ring LOADS: D=2.0 CLK=1.0 R=2.0 S=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.066410 0.065530 0.065050 0.000000 0.000000 0.065930 Setup -0.421040
(NomProc,25degC,trf=2ns)
Rise -1.278890 1.038710 0.746000 0.000000 0.000000 0.618160 Hold -0.077170 Fall Slope -0.029030 0.031460 0.028510 0.030110 0.029370 0.028750 Fall -1.397330 1.208020 0.818610 1.226730 1.169140 0.686900
TIMING TABLE
Path -CLK Path Rise Slope -0.056450 0.058440 0.057270 0.000000 0.000000 0.054720 Setup -0.330870
(NomProc,25degC,trf=2ns)
Rise -0.894040 0.680850 0.497140 0.000000 0.000000 0.402810 Hold -0.124400 Fall Slope -0.024350 0.024010 0.024320 0.026970 0.024190 0.024170 Fall -0.960710 0.813390 0.589140 0.836000 0.816390 0.495110
DFFBSRX Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
DFFBSRX Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:14:08 1996
DFFC ATL60 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous clear
cell data sheets
Truth Table:
at60Cells
DFFC
Q(T+1) Q(T)
VDD! VDD! VDD! VDD!
VDD! VSS!
VDD!
VSS! VDD!
VDD!
VDD! VSS!
VSS!
VSS!
VSS!
VDD!
VDD!
VSS!
VSS!
($Revision: 1.27
12:14:08 1996
DFFC ATL60 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous clear
cell data sheets
SITES: Core Ring LOADS: D=2.0 CLK=1.0 C=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.033110 0.000000 Setup -0.209740
(NomProc,25degC,trf=2ns)
Rise -0.826510 0.000000 Hold -0.059900 Fall Slope -0.017520 0.016920 Fall -0.861280 0.920860
TIMING TABLE
Path -CLK Path Rise Slope -0.027200 0.000000 Setup -0.507510
(NomProc,25degC,trf=2ns)
Rise -0.603560 0.000000 Hold -0.012760 Fall Slope -0.014530 0.012630 Fall -0.569050 0.638610
DFFC Typical Case Path Delays rise fall rise fall
DFFC Typical Case Path Delays rise fall rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:14:08 1996
DFFR ATL60 CMOS Gate Array
DESCRIPTION: flip-flop with asychronous reset
cell data sheets
Truth Table:
at60Cells
DFFR
Q(T+1) Q(T)
VDD!
VDD!
VDD! VDD!
P180
VDD!
VSS!
P149 N152 N155
P154 N112
N182
VDD! VSS!
P122
P175 N174
VSS! VDD!
P125
P124 P131 VDD! P110 N139
VSS!
VSS!
VDD!
P162 N166 N164
VSS!
P163
VSS! VDD! VDD!
P136
P114 N101 N104
VSS!
VSS!
($Revision: 1.27
12:14:08 1996
DFFR ATL60 CMOS Gate Array
DESCRIPTION: flip-flop with asychronous reset
cell data sheets
SITES: Core Ring LOADS: D=2.0 CLK=1.0 R=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.034380 0.000000 Setup -0.275380
(NomProc,25degC,trf=2ns)
Rise -0.940870 0.000000 Hold -0.051300 Fall Slope -0.021230 0.018960 Fall -0.869510 1.111480
TIMING TABLE
Path -CLK Path Rise Slope -0.028540 0.000000 Setup -0.365430
(NomProc,25degC,trf=2ns)
Rise -0.616300 0.000000 Hold -0.005590 Fall Slope -0.017030 0.015830 Fall -0.548070 0.723970
DFFR Typical Case Path Delays rise fall rise fall
DFFR Typical Case Path Delays rise fall rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:14:08 1996
DFFS ATL60 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous
cell data sheets
Truth Table:
at60Cells
DFFS
Q(T+1) Q(T)
VDD!
P114
VDD! VDD!
P100
N120
P117 N118 N121 P122 VDD! P123 P124 N125
VSS! VSS! VSS!
N113
VDD! VSS!
P119
P116 N115
VSS!
VDD!
N106
VSS!
N101
VSS!
VSS!
N126
VDD!
VDD!
P110
P111 N109 N112
VSS!
VSS!
($Revision: 1.27
12:14:08 1996
DFFS ATL60 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous
cell data sheets
SITES: Core Ring LOADS: D=2.0 CLK=1.0 S=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.031620 0.032380 Setup -0.511200
(NomProc,25degC,trf=2ns)
Rise -0.828990 0.612450 Hold -0.059890 Fall Slope -0.026700 0.000000 Fall -1.020380 0.000000
TIMING TABLE
Path -CLK Path Rise Slope -0.027750 0.027410 Setup -0.434630
(NomProc,25degC,trf=2ns)
Rise -0.538540 0.394180 Hold -0.103700 Fall Slope -0.019810 0.000000 Fall -0.616860 0.000000
DFFS Typical Case Path Delays rise fall rise fall
DFFS Typical Case Path Delays rise fall rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:14:08 1996
DFFSR ATL60 CMOS Gate Array
DESCRIPTION: flip-flop with asynchrounous reset
cell data sheets
Truth Table:
at60Cells
DFFSR
Q(T+1) Q(T)
VDD!
VDD!
VDD! VDD!
VDD! VSS!
VSS!
VSS!
VDD!
VSS!
VSS! VDD!
VSS!
VSS!
VSS!
VDD! VDD!
VSS! VSS! VSS!
VSS!
VSS!
($Revision: 1.27
12:14:08 1996
DFFSR ATL60 CMOS Gate Array
DESCRIPTION: flip-flop with asynchrounous reset
cell data sheets
SITES: Core Ring LOADS: D=2.0 CLK=1.0 R=2.0 S=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.031970 0.032080 0.030560 Setup -0.421040
(NomProc,25degC,trf=2ns)
Rise -1.303810 0.719410 1.041520 Hold -0.059880 Fall Slope -0.015920 0.015830 0.000000 Fall -1.221100 0.633630 0.000000
TIMING TABLE
Path -CLK Path Rise Slope -0.026660 0.027360 0.027320 Setup -0.341250
(NomProc,25degC,trf=2ns)
Rise -0.870560 0.504420 0.678560 Hold -0.021370 Fall Slope -0.012370 0.013370 0.000000 Fall -0.790230 0.425940 0.000000
DFFSR Typical Case Path Delays rise fall rise fall rise fall
DFFSR Typical Case Path Delays rise fall rise fall rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:14:08 1996
ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop
cell data sheets
Truth Table:
at60Cells
Q(T+1) Q(T)
VDD!
VDD!
VDD!
VDD!
N101
VSS!
VSS! VDD!
VSS! VDD!
P111
N105
VDD!
N110
VDD! VSS!
P122 N120
P103
VSS!
VSS!
VDD! VSS!
VSS! VDD! VDD!
P127 N128
VSS!
VSS!
VSS!
($Revision: 1.27
12:15:27 1996
ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.020400 Setup -0.757910 0.757560 0.981890
(NomProc,25degC,trf=2ns)
Rise -0.883410 Hold -0.000000 0.000000 0.000000 Fall Slope -0.012500 Fall -1.029120
TIMING TABLE
Path -CLK Path Rise Slope -0.017550 Setup -0.581550 0.619370 0.732020
(NomProc,25degC,trf=2ns)
Rise -0.623420 Hold -0.000000 0.000000 0.000000 Fall Slope -0.009880 Fall -0.739750
Typical Case Path Delays rise fall
Typical Case Path Delays rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:15:27 1996
DSSBCPY ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop with clear preset
cell data sheets
at60Cells
Truth Table:
Q(T+1) QB(T+1) Q(T) QB(T)
DSSBCPY
VDD!
VDD!
P106
VDD!
VDD!
VDD! VDD! VSS!
VSS! VDD!
P243 N246
VDD! VSS!
N117
P224
N222
VSS!
VSS! VDD! VDD!
N124
VDD!
P231 N233 VDD!
VSS!
VSS! VDD!
P114
N108
VSS! VDD! VDD!
VSS!
P248 N247
VDD! VSS!
VSS! VSS!
P252 N256
VSS!
VSS!
($Revision: 1.27
12:16:44 1996
DSSBCPY ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop with clear preset
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0 C=2.0 P=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.033140 0.033260 0.032400 0.000000 0.000000 0.032500 Setup -1.192100 0.961180 1.184300
(NomProc,25degC,trf=2ns)
Rise -1.526330 0.779160 0.532730 0.000000 0.000000 0.474530 Hold -0.000000 0.000000 0.000000 Fall Slope -0.016960 0.016850 0.018790 0.017600 0.019760 0.016460 Fall -1.404120 1.283180 1.105290 1.229260 1.381250 0.903520
TIMING TABLE
Path -CLK Path Rise Slope -0.026870 0.027980 0.027460 0.000000 0.000000 0.027160 Setup -0.674190 0.828190 1.002000
(NomProc,25degC,trf=2ns)
Rise -1.079880 0.533490 0.376310 0.000000 0.000000 0.339160 Hold -0.000000 0.000000 0.000000 Fall Slope -0.013130 0.014200 0.015900 0.013220 0.014330 0.014060 Fall -0.983330 0.906950 0.720520 0.913230 0.995970 0.609950
DSSBCPY Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
DSSBCPY Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:16:44 1996
DSSBR ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop with reset
cell data sheets
Truth Table:
at60Cells
Q(T+1) QB(T+1) Q(T) QB(T)
DSSBR
VDD!
P306
VDD! VDD! VDD!
N286
P279 N280
VSS!
N250
P274 P273
N231
P240 N212 N244 P234 VDD! P252 P257 N263
VSS! VSS! VSS!
N302
VDD! VSS!
P214
P284 N294
VDD!
P311 N315
VSS! VDD!
P215 N241 VDD! P203
N269
VSS!
N265
VSS!
P223 N198
VSS!
P289 P283
P338 N343 N256
VDD! VSS!
N297
VSS! VDD!
VDD!
P344 N335
P200
P222 N237 N229
VSS! VSS!
VSS!
($Revision: 1.27
12:16:44 1996
DSSBR ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop with reset
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0 R=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.032590 0.032630 0.032380 0.000000 Setup -1.145400 1.153300 1.307100
(NomProc,25degC,trf=2ns)
Rise -1.191110 0.864450 0.540630 0.000000 Hold -0.000000 0.000000 0.000000 Fall Slope -0.016090 0.014970 0.000000 0.015550 Fall -1.477210 0.981730 0.000000 0.991560
TIMING TABLE
Path -CLK Path Rise Slope -0.027160 0.028820 0.027200 0.000000 Setup -0.859100 0.861530 0.938440
(NomProc,25degC,trf=2ns)
Rise -0.824690 0.561440 0.358470 0.000000 Hold -0.000000 0.000000 0.000000 Fall Slope -0.013090 0.012310 0.000000 0.012660 Fall -1.031530 0.694440 0.000000 0.687230
DSSBR Typical Case Path Delays rise fall rise fall rise fall rise fall
DSSBR Typical Case Path Delays rise fall rise fall rise fall rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:16:44 1996
DSSBS ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop with
cell data sheets
at60Cells
Truth Table:
Q(T+1) QB(T+1) Q(T) QB(T)
DSSBS
VDD!
VDD!
P158
P114
VDD! VDD! VDD!
VDD!
N155
VSS!
N135
P128 N131
VSS!
P100
N106
N120
P117 N118 N121 P122 VDD!
VSS! VDD!
N113
VDD! VSS!
P119
P116 N115
P134 N139
N101
VDD! VSS!
VSS! VSS!
P124 N125 N126
P123
VSS! VDD!
P140
VDD!
P162 N173
VDD! VSS!
P146
VDD!
VDD!
P110
P169 P111 N170 N112
VSS!
N147
VSS!
N109
VSS!
VSS!
($Revision: 1.27
12:16:44 1996
DSSBS ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop with
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0 S=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.033080 0.032420 0.000000 0.032490 Setup -0.982060 0.979840 1.255400
(NomProc,25degC,trf=2ns)
Rise -1.287210 0.809100 0.000000 1.103000 Hold -0.000000 0.000000 0.000000 Fall Slope -0.015700 0.015840 0.015660 0.000000 Fall -1.232980 1.050710 0.846250 0.000000
TIMING TABLE
Path -CLK Path Rise Slope -0.027350 0.027970 0.000000 0.027080 Setup -0.730690 0.728960 0.901410
(NomProc,25degC,trf=2ns)
Rise -0.951060 0.557310 0.000000 0.754710 Hold -0.000000 0.000000 0.000000 Fall Slope -0.012420 0.012350 0.012650 0.000000 Fall -0.869720 0.768030 0.571740 0.000000
DSSBS Typical Case Path Delays rise fall rise fall rise fall rise fall
DSSBS Typical Case Path Delays rise fall rise fall rise fall rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:16:44 1996
DSSR ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop with reset
cell data sheets
at60Cells
Truth Table:
Q(T+1) Q(T)
DSSR
VDD! VDD!
VDD!
VDD!
N286
P279 N280
VSS!
N250
P274 P273
N231
P240 N212 N244 P234 VDD! P252 P257 N263
VSS! VSS! VSS!
P306
P214
N302
VDD! VSS!
P284 N294
VDD!
P215 N241 VDD! P203
N269
VSS!
N265
VSS!
P311 N315
VSS!
P223 N198
VSS!
P289 P283
N297
VSS! VDD!
N256
VDD!
P200
P222 N237 N229
VSS!
VSS!
($Revision: 1.27
12:16:44 1996
DSSR ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop with reset
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0 R=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.032610 0.000000 Setup -1.498200 1.497500 1.561400
(NomProc,25degC,trf=2ns)
Rise -0.847600 0.000000 Hold -0.000000 0.000000 0.000000 Fall Slope -0.014850 0.014730 Fall -0.995890 0.809180
TIMING TABLE
Path -CLK Path Rise Slope -0.028360 0.000000 Setup -0.846410 0.845390 0.922710
(NomProc,25degC,trf=2ns)
Rise -0.595580 0.000000 Hold -0.000000 0.000000 0.000000 Fall Slope -0.012870 0.011940 Fall -0.688700 0.536800
DSSR Typical Case Path Delays rise fall rise fall
DSSR Typical Case Path Delays rise fall rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:16:44 1996
DSSS ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop with
cell data sheets
at60Cells
Truth Table:
Q(T+1) Q(T)
DSSS
VDD!
VDD!
P158
P114
VDD! VDD! VDD!
VDD!
N135
N155 VSS! P128 N131
P100
N106 N101
N120
P117
VSS!
N113
P119 N121
N118 P122 VDD!
VSS! VDD! VDD!
P134
P116 N115
VSS!
VSS!
VDD! VSS!
N139
VSS! VDD! VDD!
P124
P123
P140
VDD!
N125 N126
VSS!
P146
N147
VSS!
P110 N109
VSS!
P111 N112
VSS!
($Revision: 1.27
12:16:44 1996
DSSS ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop with
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0 S=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.032500 0.032440 Setup -0.865570 0.861030 1.151000
(NomProc,25degC,trf=2ns)
Rise -0.792680 1.018430 Hold -0.000000 0.000000 0.000000 Fall Slope -0.015670 0.000000 Fall -1.046430 0.000000
TIMING TABLE
Path -CLK Path Rise Slope -0.027900 0.028350 Setup -0.680440 0.728960 0.901410
(NomProc,25degC,trf=2ns)
Rise -0.551070 0.675440 Hold -0.000000 0.000000 0.000000 Fall Slope -0.012850 0.000000 Fall -0.755700 0.000000
DSSS Typical Case Path Delays rise fall rise fall
DSSS Typical Case Path Delays rise fall rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:16:44 1996
DSSSR ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop with reset
cell data sheets
at60Cells
DSSSR
Truth Table:
Q(T+1) Q(T)
VDD!
P136
VDD!
P134
VSS!
N140
VDD! VDD! VDD!
N115
N132
VDD! VDD!
VSS! VDD!
VSS! VDD! VDD!
P119 N108
P123 N126 P120
VSS!
VDD! VDD! VSS!
VSS! VDD!
VSS!
VDD!
VSS!
VSS!
P124
N113
VDD!
VDD!
VSS!
VSS!
VSS!
($Revision: 1.27
12:17:53 1996
DSSSR ATL60 CMOS Gate Array
DESCRIPTION: scan flip-flop with reset
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0 R=1.0 S=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.034000 0.032130 0.032280 Setup -0.865570 0.861050 1.081500
(NomProc,25degC,trf=2ns)
Rise -0.908260 0.673180 1.166480 Hold -0.000000 0.000000 0.000000 Fall Slope -0.016070 0.015430 0.000000 Fall -1.051570 0.770420 0.000000
TIMING TABLE
Path -CLK Path Rise Slope -0.028430 0.028520 0.027410 Setup -0.680730 0.653770 0.837810
(NomProc,25degC,trf=2ns)
Rise -0.641160 0.484240 0.791260 Hold -0.000000 0.000000 0.000000 Fall Slope -0.012480 0.012730 0.000000 Fall -0.773000 0.536570 0.000000
DSSSR Typical Case Path Delays rise fall rise fall rise fall
DSSSR Typical Case Path Delays rise fall rise fall rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:17:53 1996
ATL60 CMOS Gate Array
DESCRIPTION: flip flop
cell data sheets
Truth Table:
at60Cells
Q(T+1) Q(T) Q(T) Q(T)BAR
VDD!
I130 I133
VDD! VDD! VDD! VSS!
VDD!
I120 I115 I114 VDD! I118 I121
VSS! VSS! VSS!
I126 I127
I129 I132
VSS! VDD!
I131 I134
VSS!
I124
VSS!
P109
I112 I113 VDD!
VSS!
VDD!
I128 I139
I116 I122 I123 I117
I135 I137
VSS!
($Revision: 1.27
12:20:12 1996
ATL60 CMOS Gate Array
DESCRIPTION: flip flop
cell data sheets
SITES: Core Ring LOADS: J=2.0 K=1.0 CLK=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.034340 Setup -0.595570 0.831010
(NomProc,25degC,trf=2ns)
Rise -0.706950 Hold -0.115270 0.000000 Fall Slope -0.017230 Fall -0.875630
TIMING TABLE
Path -CLK Path Rise Slope -0.028400 Setup -0.514230 0.785820
(NomProc,25degC,trf=2ns)
Rise -0.491240 Hold -0.105500 0.000000 Fall Slope -0.014230 Fall -0.564470
Typical Case Path Delays rise fall
Typical Case Path Delays rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:20:12 1996
JKFBCPX ATL60 CMOS Gate Array
cell data sheets
DESCRIPTION: Clear preset flip-flop with asynchronous clear preset complementary outputs
at60Cells
Truth Table:
Q(T+1) QB(T+1) Q(T) QB(T) Q(T) QB(T) QB(T) Q(T)
JKFBCPX
VDD! VDD! VDD! VDD! VDD! VDD!
VDD!
P189 N188
P155
P146
VSS! VDD!
N156 N153
VDD!
VDD!
P158
P105 N103
P167
VSS!
VSS!
N157 N160
VSS! VDD! VDD!
VSS! VDD!
VDD!
VDD!
VDD! VSS!
P175
P198 N200
VDD!
P172
P184
VSS!
N100
VSS! VDD!
N168
N171
N183
P199 N197
VSS!
VSS!
VSS! VSS!
VSS! VDD! VDD!
P117 N115
P124 N119
VSS!
VSS!
($Revision: 1.27
12:20:12 1996
JKFBCPX ATL60 CMOS Gate Array
cell data sheets
DESCRIPTION: Clear preset flip-flop with asynchronous clear preset complementary outputs
SITES: Core Ring LOADS: J=1.0 K=1.0 CLK=1.0 C=2.0 P=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.033050 0.033040 0.032840 0.032760 0.033150 0.032650 Setup -1.346700 1.326000
(NomProc,25degC,trf=2ns)
Rise -1.446230 0.923960 1.075710 0.528290 0.867400 1.184240 Hold -0.000000 0.000000 Fall Slope -0.015920 0.015150 0.000000 0.015340 0.017220 0.000000 Fall -1.511680 1.077970 0.000000 0.551010 0.720090 0.000000
TIMING TABLE
Path -CLK Path Rise Slope -0.027930 0.028250 0.028330 0.026400 0.026920 0.028070 Setup -1.003700 0.978870
(NomProc,25degC,trf=2ns)
Rise -1.027190 0.650760 0.805130 0.380510 0.634130 0.834690 Hold -0.000000 0.000000 Fall Slope -0.013690 0.012260 0.000000 0.012410 0.012760 0.000000 Fall -1.064750 0.752130 0.000000 0.395610 0.539270 0.000000
JKFBCPX Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
JKFBCPX Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:20:12 1996
JKFC ATL60 CMOS Gate Array
DESCRIPTION: flip flop with asynchronous clear
cell data sheets
at60Cells
Truth Table: Q(T+1) Q(T) Q(T) Q(T)BAR
JKFC
VDD!
I130 I133
VDD! VDD! VDD! VDD! VSS!
VDD!
I119 I115 I114 VDD! I118 I121
VSS! VSS! VSS!
I120 I124 I125
VSS!
I126 I127
I129 I132
VSS! VDD! VDD!
I131 I134
VSS!
P109
I112 I113 VDD!
VSS!
VDD!
I128 I139
I116 I122 I123 I117
I135 I137 I138
VSS!
I136
($Revision: 1.27
12:20:12 1996
JKFC ATL60 CMOS Gate Array
DESCRIPTION: flip flop with asynchronous clear
cell data sheets
SITES: Core Ring LOADS: J=2.0 K=1.0 CLK=1.0 C=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.033310 0.000000 Setup -0.475880 1.075800
(NomProc,25degC,trf=2ns)
Rise -0.809720 0.000000 Hold -0.106660 0.000000 Fall Slope -0.018570 0.016470 Fall -0.828670 0.820030
TIMING TABLE
Path -CLK Path Rise Slope -0.027270 0.000000 Setup -0.612590 0.817460
(NomProc,25degC,trf=2ns)
Rise -0.583100 0.000000 Hold -0.156190 0.000000 Fall Slope -0.014550 0.013520 Fall -0.556520 0.554160
JKFC Typical Case Path Delays rise fall rise fall
JKFC Typical Case Path Delays rise fall rise fall
Delay (ns)
Delay (ns)
Number unit loads
Number unit loads
($Revision: 1.27
12:20:12 1996

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