DESCRIPTION: inverter cell data sheets Truth Table: ATL
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Top Searches for this datasheet
INV1 ATL35 CMOS Gate Array
DESCRIPTION: inverter
cell data sheets
Truth Table:
ATL55Cells
INV1
VDD!
VSS!
($Revision: 1.35
15:33:06 1997
INV1 ATL35 CMOS Gate Array
DESCRIPTION: inverter
cell data sheets
SITES: Core LOADS: I=1.0
Ring
TIMING TABLE
Path Rise Slope -0.02795
(NomProc,25degC,Nom trf)
Rise -0.15984 Fall Slope -0.02586 Fall -0.11502
INV1 Typical Case Path Delays rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:33:06 1997
INV1D ATL35 CMOS Gate Array
DESCRIPTION: Dual inverters
cell data sheets
Truth Table:
ATL55Cells
INV1D
VDD!
VSS!
VDD!
VSS!
($Revision: 1.35
15:33:06 1997
INV1D ATL35 CMOS Gate Array
DESCRIPTION: Dual inverters
cell data sheets
SITES: Core Ring LOADS: I0=1.0 I1=1.0
TIMING TABLE
Path Rise Slope -0.02797 0.02795
(NomProc,25degC,Nom trf)
Rise -0.15911 0.15984 Fall Slope -0.02586 0.02586 Fall -0.11583 0.11502
INV1D Typical Case Path Delays rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:33:06 1997
INV1Q ATL35 CMOS Gate Array
DESCRIPTION: Quad inverters
cell data sheets
ATL55Cells
Truth Table:
INV1Q
VDD!
VDD!
VSS! VDD!
VSS! VDD!
VSS!
VSS!
($Revision: 1.35
15:33:56 1997
INV1Q ATL35 CMOS Gate Array
DESCRIPTION: Quad inverters
cell data sheets
SITES: Core Ring LOADS: I0=1.0 I1=1.0 I2=1.0 I3=1.0
TIMING TABLE
Path Rise Slope -0.02795 0.02795 0.02795 0.02795
(NomProc,25degC,Nom trf)
Rise -0.15984 0.15984 0.15984 0.15984 Fall Slope -0.02586 0.02586 0.02586 0.02586 Fall -0.11502 0.11502 0.11502 0.11502
INV1Q Typical Case Path Delays rise fall rise fall rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:33:56 1997
INV1TQ ATL35 CMOS Gate Array
DESCRIPTION: Quad tristate inverter
cell data sheets
ATL55Cells
Truth Table:
INV1TQ
VDD!
VSS! VDD!
VDD!
VDD!
VDD!
VSS!
VSS!
VSS! VDD!
VSS! VDD!
VSS!
($Revision: 1.35
15:33:56 1997
INV1TQ ATL35 CMOS Gate Array
DESCRIPTION: Quad tristate inverter
cell data sheets
SITES: Core Ring LOADS: O0=1.0 O1=1.0 O2=1.0 O3=1.0 I0=1.0 I1=1.0 I2=1.0 I3=1.0 E0=1.0 E1=1.0
TIMING TABLE
Path Rise Slope -0.05259 0.05259 0.05259 0.05259 0.05312 0.05312 0.05312 0.05312 0.05321 0.05321 0.05321 0.05321
(NomProc,25degC,Nom trf)
Rise -0.17307 0.17307 0.17307 0.17307 0.36906 0.36906 0.36906 0.36906 0.33947 0.33947 0.33947 0.33947 Fall Slope -0.04213 0.04213 0.04213 0.04213 0.04231 0.04231 0.04231 0.04231 0.04237 0.04237 0.04237 0.04237 Fall -0.13167 0.13167 0.13167 0.13167 0.39667 0.39667 0.39667 0.39667 0.35237 0.35237 0.35237 0.35237
INV1TQ Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall rise fall rise fall rise fall rise fall rise fall rise
Delay (ns)
Number unit loads
($Revision: 1.35
15:33:56 1997
INV2 ATL35 CMOS Gate Array
DESCRIPTION: inverter
cell data sheets
Truth Table:
ATL55Cells
INV2
VDD!
VSS! VDD!
VSS!
($Revision: 1.35
15:33:56 1997
INV2 ATL35 CMOS Gate Array
DESCRIPTION: inverter
cell data sheets
SITES: Core LOADS: I=2.0
Ring
TIMING TABLE
Path Rise Slope -0.01400
(NomProc,25degC,Nom trf)
Rise -0.15331 Fall Slope -0.01294 Fall -0.10996
INV2 Typical Case Path Delays rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:33:56 1997
INV2T ATL35 CMOS Gate Array
DESCRIPTION: tristate inverter with active high enable
cell data sheets
Truth Table:
ATL55Cells
INV2T
VDD!
VSS! VDD!
VSS!
VDD!
VSS!
($Revision: 1.35
15:33:56 1997
INV2T ATL35 CMOS Gate Array
DESCRIPTION: tristate inverter with active high enable
cell data sheets
SITES: Core Ring LOADS: O=1.0 I=2.0 E=1.5
TIMING TABLE
Path Rise Slope -0.02685 0.02658
(NomProc,25degC,Nom trf)
Rise -0.14804 0.08180 Fall Slope -0.02304 0.02372 Fall -0.11026 0.05141
INV2T Typical Case Path Delays rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:33:56 1997
INV3 ATL35 CMOS Gate Array
DESCRIPTION: inverter
cell data sheets
Truth Table:
ATL55Cells
INV3
VDD!
VSS! VDD!
VSS! VDD!
VSS!
($Revision: 1.35
15:33:56 1997
INV3 ATL35 CMOS Gate Array
DESCRIPTION: inverter
cell data sheets
SITES: Core LOADS: I=3.0
Ring
TIMING TABLE
Path Rise Slope -0.00933
(NomProc,25degC,Nom trf)
Rise -0.15470 Fall Slope -0.00863 Fall -0.11146
INV3 Typical Case Path Delays rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:33:56 1997
INV4 ATL35 CMOS Gate Array
DESCRIPTION: inverter
cell data sheets
Truth Table:
ATL55Cells
INV4
VDD!
VSS! VDD!
VSS! VDD!
VSS! VDD!
VSS!
($Revision: 1.35
15:34:55 1997
INV4 ATL35 CMOS Gate Array
DESCRIPTION: inverter
cell data sheets
SITES: Core LOADS: I=4.0
Ring
TIMING TABLE
Path Rise Slope -0.00700
(NomProc,25degC,Nom trf)
Rise -0.15317 Fall Slope -0.00647 Fall -0.10981
INV4 Typical Case Path Delays rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:34:55 1997
INV8 ATL35 CMOS Gate Array
DESCRIPTION: inverter
cell data sheets
Truth Table:
ATL55Cells
INV8
VDD!
VSS! VDD!
VSS! VDD!
VSS! VDD!
VSS! VDD!
VSS! VDD!
VSS! VDD!
VSS! VDD!
VSS!
($Revision: 1.35
15:34:55 1997
INV8 ATL35 CMOS Gate Array
DESCRIPTION: inverter
cell data sheets
SITES: Core LOADS: I=8.0
Ring
TIMING TABLE
Path Rise Slope -0.00350
(NomProc,25degC,Nom trf)
Rise -0.15309 Fall Slope -0.00324 Fall -0.10974
INV8 Typical Case Path Delays rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:34:55 1997
INV10 ATL35 CMOS Gate Array
DESCRIPTION: inverter
cell data sheets
Truth Table:
ATL55Cells
INV10
VDD!
VDD!
VDD!
VDD! VSS!
VDD! VSS!
VDD! VSS!
VSS! VDD!
VSS! VDD!
VSS! VDD!
VDD!
VSS!
VSS! VDD!
VSS! VDD!
VSS!
VSS! VDD!
VSS! VDD!
VSS!
VSS!
($Revision: 1.35
15:34:55 1997
INV10 ATL35 CMOS Gate Array
DESCRIPTION: inverter
cell data sheets
SITES: Core LOADS: I=1.0
Ring
TIMING TABLE
Path Rise Slope -0.00276
(NomProc,25degC,Nom trf)
Rise -0.42094 Fall Slope -0.00251 Fall -0.38635
INV10 Typical Case Path Delays rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:34:55 1997
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